diff options
Diffstat (limited to 'arm64-96boards-Rock960-CE-board-support.patch')
| -rw-r--r-- | arm64-96boards-Rock960-CE-board-support.patch | 1339 |
1 files changed, 1339 insertions, 0 deletions
diff --git a/arm64-96boards-Rock960-CE-board-support.patch b/arm64-96boards-Rock960-CE-board-support.patch new file mode 100644 index 000000000..e65156791 --- /dev/null +++ b/arm64-96boards-Rock960-CE-board-support.patch @@ -0,0 +1,1339 @@ +From 18c1ec0b6501f2aa0aabcc8ca75824f9f49bcd91 Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +Date: Mon, 10 Sep 2018 20:43:53 +0530 +Subject: [PATCH 1/4] arm64: dts: rockchip: Split out common nodes for Rock960 + based boards + +Since the same family members of Rock960 boards (Rock960 and Ficus) +share the same configuration, split out the common nodes into a common +dtsi file for reducing code duplication. The board specific nodes for +Ficus boards are then placed in corresponding board DTS file. + +Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +--- + arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 429 +---------------- + .../boot/dts/rockchip/rk3399-rock960.dtsi | 439 ++++++++++++++++++ + 2 files changed, 440 insertions(+), 428 deletions(-) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +index 8978d924eb83..7f6ec37d5a69 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +@@ -7,8 +7,7 @@ + */ + + /dts-v1/; +-#include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" ++#include "rk3399-rock960.dtsi" + + / { + model = "96boards RK3399 Ficus"; +@@ -25,31 +24,6 @@ + #clock-cells = <0>; + }; + +- vcc1v8_s0: vcc1v8-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_s0"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- }; +- +- vcc_sys: vcc-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- }; +- +- vcc3v3_sys: vcc3v3-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_sys"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- vin-supply = <&vcc_sys>; +- }; +- + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; +@@ -75,46 +49,6 @@ + regulator-always-on; + vin-supply = <&vcc_sys>; + }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 0>; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_l>; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; +-}; +- +-&emmc_phy { +- status = "okay"; + }; + + &gmac { +@@ -133,263 +67,6 @@ + status = "okay"; + }; + +-&hdmi { +- ddc-i2c-bus = <&i2c3>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hdmi_cec>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <400000>; +- i2c-scl-rising-time-ns = <168>; +- i2c-scl-falling-time-ns = <4>; +- status = "okay"; +- +- vdd_cpu_b: regulator@40 { +- compatible = "silergy,syr827"; +- reg = <0x40>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_b"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- status = "okay"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_gpu: regulator@41 { +- compatible = "silergy,syr828"; +- reg = <0x41>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_gpu"; +- regulator-min-microvolt = <712500>; +- regulator-max-microvolt = <1500000>; +- regulator-ramp-delay = <1000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- rk808: pmic@1b { +- compatible = "rockchip,rk808"; +- reg = <0x1b>; +- interrupt-parent = <&gpio1>; +- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; +- rockchip,system-power-controller; +- wakeup-source; +- #clock-cells = <1>; +- clock-output-names = "xin32k", "rk808-clkout2"; +- +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc6-supply = <&vcc_sys>; +- vcc7-supply = <&vcc_sys>; +- vcc8-supply = <&vcc3v3_sys>; +- vcc9-supply = <&vcc_sys>; +- vcc10-supply = <&vcc_sys>; +- vcc11-supply = <&vcc_sys>; +- vcc12-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- +- regulators { +- vdd_center: DCDC_REG1 { +- regulator-name = "vdd_center"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_l: DCDC_REG2 { +- regulator-name = "vdd_cpu_l"; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_ddr: DCDC_REG3 { +- regulator-name = "vcc_ddr"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_1v8: DCDC_REG4 { +- regulator-name = "vcc_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc1v8_dvp: LDO_REG1 { +- regulator-name = "vcc1v8_dvp"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca1v8_hdmi: LDO_REG2 { +- regulator-name = "vcca1v8_hdmi"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcca_1v8: LDO_REG3 { +- regulator-name = "vcca_1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vcc_sd: LDO_REG4 { +- regulator-name = "vcc_sd"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vcc3v0_sd: LDO_REG5 { +- regulator-name = "vcc3v0_sd"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc_1v5: LDO_REG6 { +- regulator-name = "vcc_1v5"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1500000>; +- }; +- }; +- +- vcca0v9_hdmi: LDO_REG7 { +- regulator-name = "vcca0v9_hdmi"; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <900000>; +- }; +- }; +- +- vcc_3v0: LDO_REG8 { +- regulator-name = "vcc_3v0"; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3000000>; +- }; +- }; +- +- vcc3v3_s3: SWITCH_REG1 { +- regulator-name = "vcc3v3_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc3v3_s0: SWITCH_REG2 { +- regulator-name = "vcc3v3_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&i2c1 { +- status = "okay"; +-}; +- +-&i2c2 { +- status = "okay"; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- status = "okay"; +-}; +- +-&io_domains { +- bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ +- audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ +- sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ +- gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +- status = "okay"; +-}; +- + &pcie_phy { + status = "okay"; + }; +@@ -403,11 +80,6 @@ + status = "okay"; + }; + +-&pmu_io_domains { +- pmu1830-supply = <&vcc_1v8>; +- status = "okay"; +-}; +- + &pinctrl { + gmac { + rgmii_sleep_pins: rgmii-sleep-pins { +@@ -416,31 +88,6 @@ + }; + }; + +- sdmmc { +- sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = +- <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = +- <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, +- <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, +- <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, +- <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; +- }; +- +- sdmmc_clk: sdmmc-clk { +- rockchip,pins = +- <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; +- }; +- +- sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = +- <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; +- }; +- }; +- + pcie { + pcie_drv: pcie-drv { + rockchip,pins = +@@ -448,23 +95,6 @@ + }; + }; + +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = +- <1 21 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- +- vsel1_gpio: vsel1-gpio { +- rockchip,pins = +- <1 17 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- +- vsel2_gpio: vsel2-gpio { +- rockchip,pins = +- <1 14 RK_FUNC_GPIO &pcfg_pull_down>; +- }; +- }; +- + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = +@@ -473,37 +103,6 @@ + }; + }; + +-&pwm2 { +- status = "okay"; +-}; +- +-&pwm3 { +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- non-removable; +- status = "okay"; +-}; +- +-&sdmmc { +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- clock-frequency = <100000000>; +- clock-freq-min-max = <100000 100000000>; +- disable-wp; +- sd-uhs-sdr104; +- vqmmc-supply = <&vcc_sd>; +- card-detect-delay = <800>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +- status = "okay"; +-}; +- + &tcphy0 { + status = "okay"; + }; +@@ -538,16 +137,6 @@ + status = "okay"; + }; + +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_xfer &uart0_cts>; +- status = "okay"; +-}; +- +-&uart2 { +- status = "okay"; +-}; +- + &usb_host0_ehci { + status = "okay"; + }; +@@ -581,19 +170,3 @@ + status = "okay"; + dr_mode = "host"; + }; +- +-&vopb { +- status = "okay"; +-}; +- +-&vopb_mmu { +- status = "okay"; +-}; +- +-&vopl { +- status = "okay"; +-}; +- +-&vopl_mmu { +- status = "okay"; +-}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +new file mode 100644 +index 000000000000..5a5d8e28ef55 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +@@ -0,0 +1,439 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2018 Collabora Ltd. ++ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2018 Linaro Ltd. ++ */ ++ ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ vcc1v8_s0: vcc1v8-s0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_s0"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 0>; ++ regulator-name = "vdd_log"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ status = "okay"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc_sys>; ++ vcc10-supply = <&vcc_sys>; ++ vcc11-supply = <&vcc_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_hdmi: LDO_REG2 { ++ regulator-name = "vcca1v8_hdmi"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG3 { ++ regulator-name = "vcca_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sd: LDO_REG4 { ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc3v0_sd: LDO_REG5 { ++ regulator-name = "vcc3v0_sd"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca0v9_hdmi: LDO_REG7 { ++ regulator-name = "vcca0v9_hdmi"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-name = "vcc_3v0"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++}; ++ ++&i2c2 { ++ status = "okay"; ++}; ++ ++&i2c3 { ++ status = "okay"; ++}; ++ ++&i2c4 { ++ status = "okay"; ++}; ++ ++&io_domains { ++ bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ ++ audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ ++ sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ ++ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ sdmmc { ++ sdmmc_bus1: sdmmc-bus1 { ++ rockchip,pins = ++ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; ++ }; ++ ++ sdmmc_bus4: sdmmc-bus4 { ++ rockchip,pins = ++ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, ++ <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, ++ <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, ++ <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; ++ }; ++ ++ sdmmc_clk: sdmmc-clk { ++ rockchip,pins = ++ <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; ++ }; ++ ++ sdmmc_cmd: sdmmc-cmd { ++ rockchip,pins = ++ <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <1 21 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = ++ <1 17 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = ++ <1 14 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&pwm3 { ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ clock-frequency = <100000000>; ++ clock-freq-min-max = <100000 100000000>; ++ disable-wp; ++ sd-uhs-sdr104; ++ vqmmc-supply = <&vcc_sd>; ++ card-detect-delay = <800>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; +-- +2.19.0.rc1 + +From afb33f3ec13b5ca3d7f2acd0a03dd707cba90638 Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +Date: Mon, 10 Sep 2018 20:43:54 +0530 +Subject: [PATCH 2/4] dt-bindings: arm: rockchip: Add binding for Rock960 board + +Add devicetree binding for Rock960 board from Vamrs Limited. + +Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +--- + Documentation/devicetree/bindings/arm/rockchip.txt | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt +index d46c5d43e27f..4ed03f7e8eb2 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.txt ++++ b/Documentation/devicetree/bindings/arm/rockchip.txt +@@ -5,6 +5,10 @@ Rockchip platforms device tree bindings + Required root node properties: + - compatible = "vamrs,ficus", "rockchip,rk3399"; + ++- 96boards RK3399 Rock960 (ROCK960 Consumer Edition) ++ Required root node properties: ++ - compatible = "vamrs,rk3399-rock960", "rockchip,rk3399"; ++ + - Amarula Vyasa RK3288 board + Required root node properties: + - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; +-- +2.19.0.rc1 + +From d7c58c9061b4aee405e328d1c8a60850605aac94 Mon Sep 17 00:00:00 2001 +From: Peter Robinson <pbrobinson@gmail.com> +Date: Mon, 10 Sep 2018 18:26:45 +0100 +Subject: [PATCH 3/4] arm64: boot: dts: rockchip: Add support for Rock960 board + +Add devicetree support for Rock960 board, one of the Consumer Edition +boards of the 96Boards family. This board support utilizes the common +Rock960 family board support that includes Ficus 96Board. + +Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +Signed-off-by: Peter Robinson <pbrobinson@gmail.com> +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-rock960.dts | 139 ++++++++++++++++++ + 2 files changed, 140 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock960.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 2811fb701f12..458cce9e1a05 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -13,5 +13,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts +new file mode 100644 +index 000000000000..281f3d79b38e +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts +@@ -0,0 +1,139 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2018 Linaro Ltd. ++ */ ++ ++/dts-v1/; ++#include "rk3399-rock960.dtsi" ++ ++/ { ++ model = "96boards Rock960"; ++ compatible = "vamrs,rk3399-rock960", "rockchip,rk3399"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_drv>; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&host_vbus_drv>; ++ regulator-name = "vcc5v0_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++}; ++ ++&pinctrl { ++ pcie { ++ pcie_drv: pcie-drv { ++ rockchip,pins = ++ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb2 { ++ host_vbus_drv: host-vbus-drv { ++ rockchip,pins = ++ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; ++ num-lanes = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_clkreqn_cpm>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ status = "okay"; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&u2phy1_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++ dr_mode = "otg"; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; +-- +2.19.0.rc1 + +From defb2d89461057066a7d233a3072010da24d774c Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +Date: Mon, 10 Sep 2018 20:43:56 +0530 +Subject: [PATCH 4/4] arm64: dts: rockchip: Enable SD card detection for + Rock960 boards + +For proper working of SD cards, let's add the Card Detect GPIO property +to the common devicetree for Rock960 family boards. + +Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +--- + arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +index 5a5d8e28ef55..f68254831ad9 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +@@ -403,6 +403,7 @@ + cap-sd-highspeed; + clock-frequency = <100000000>; + clock-freq-min-max = <100000 100000000>; ++ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; +-- +2.19.0.rc1 +From patchwork Tue Oct 16 14:00:20 2018 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Daniel Lezcano <daniel.lezcano@linaro.org> +X-Patchwork-Id: 1000432 +Return-Path: <SRS0=e/xi=M4=vger.kernel.org=linux-kernel-owner@kernel.org> +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 41BB8C04EBD + for <linux-kernel@archiver.kernel.org>; Tue, 16 Oct 2018 14:01:24 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) + by mail.kernel.org (Postfix) with ESMTP id 032862089E + for <linux-kernel@archiver.kernel.org>; Tue, 16 Oct 2018 14:01:24 +0000 (UTC) +Authentication-Results: mail.kernel.org; + dkim=pass (1024-bit key) header.d=linaro.org header.i=@linaro.org + header.b="OwrJnI6D" +DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 032862089E +Authentication-Results: mail.kernel.org; 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+ Tue, 16 Oct 2018 07:01:19 -0700 (PDT) +From: Daniel Lezcano <daniel.lezcano@linaro.org> +To: heiko@sntech.de +Cc: linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, + Mark Rutland <mark.rutland@arm.com>, + Vicente Bergas <vicencb@gmail.com>, + Shawn Lin <shawn.lin@rock-chips.com>, + Ezequiel Garcia <ezequiel@collabora.com>, + Enric Balletbo i Serra <enric.balletbo@collabora.com>, + Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, + devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED + DEVICE TREE BINDINGS), + linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC + support), + linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC + support) +Subject: [PATCH] DT: rockchip: Fix stability issues with the 'performance' + governor on rock960 +Date: Tue, 16 Oct 2018 16:00:20 +0200 +Message-Id: <1539698431-12616-1-git-send-email-daniel.lezcano@linaro.org> +X-Mailer: git-send-email 2.7.4 +Sender: linux-kernel-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-kernel.vger.kernel.org> +X-Mailing-List: linux-kernel@vger.kernel.org + +When the performance governor is set as default, the rock960 hangs +around one minute after booting, whatever the activity is (idle, key +pressed, loaded, ...). + +Based on the commit log found at https://patchwork.kernel.org/patch/10092377/ + +"vdd_log has no consumer and therefore will not be set to a specific +voltage. Still the PWM output pin gets configured and thence the vdd_log +output voltage will changed from it's default. Depending on the idle +state of the PWM this will slightly over or undervoltage the logic supply +of the RK3399 and cause instability with GbE (undervoltage) and PCIe +(overvoltage). Since the default value set by a voltage divider is the +correct supply voltage and we don't need to change it during runtime we +remove the rail from the devicetree completely so the PWM pin will not +be configured." + +After removing the vdd-log from the rock960's specific DT, the board +does no longer hang and shows a stable behavior. + +Apply the same change for the rock960 by removing the vdd-log from the +DT. + +Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> +Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +--- + arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 12 ------------ + 1 file changed, 12 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +index 6c8c4ab..56abbb0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +@@ -57,18 +57,6 @@ + regulator-always-on; + vin-supply = <&vcc_sys>; + }; +- +- vdd_log: vdd-log { +- compatible = "pwm-regulator"; +- pwms = <&pwm2 0 25000 0>; +- regulator-name = "vdd_log"; +- regulator-min-microvolt = <800000>; +- regulator-max-microvolt = <1400000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vcc_sys>; +- }; +- + }; + + &cpu_l0 { |