diff options
Diffstat (limited to 'arm64-96boards-RK3399-Ficus-board.patch')
| -rw-r--r-- | arm64-96boards-RK3399-Ficus-board.patch | 947 |
1 files changed, 947 insertions, 0 deletions
diff --git a/arm64-96boards-RK3399-Ficus-board.patch b/arm64-96boards-RK3399-Ficus-board.patch new file mode 100644 index 000000000..83359b50f --- /dev/null +++ b/arm64-96boards-RK3399-Ficus-board.patch @@ -0,0 +1,947 @@ +From b41023282d07b61a53e2c9b9508912b1e7ce7b4f Mon Sep 17 00:00:00 2001 +From: Randy Li <ayaka@soulik.info> +Date: Thu, 21 Jun 2018 21:32:10 +0800 +Subject: arm64: dts: rockchip: add some common pin-settings to rk3399 + +Those pins would be used by many boards. + +Signed-off-by: Randy Li <ayaka@soulik.info> +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 86 ++++++++++++++++++++++++++------ + 1 file changed, 72 insertions(+), 14 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index adb037cd80fe..87350c694b38 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1923,19 +1923,49 @@ + drive-strength = <12>; + }; + ++ pcfg_pull_none_13ma: pcfg-pull-none-13ma { ++ bias-disable; ++ drive-strength = <13>; ++ }; ++ ++ pcfg_pull_none_18ma: pcfg-pull-none-18ma { ++ bias-disable; ++ drive-strength = <18>; ++ }; ++ ++ pcfg_pull_none_20ma: pcfg-pull-none-20ma { ++ bias-disable; ++ drive-strength = <20>; ++ }; ++ ++ pcfg_pull_up_2ma: pcfg-pull-up-2ma { ++ bias-pull-up; ++ drive-strength = <2>; ++ }; ++ + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + ++ pcfg_pull_up_18ma: pcfg-pull-up-18ma { ++ bias-pull-up; ++ drive-strength = <18>; ++ }; ++ ++ pcfg_pull_up_20ma: pcfg-pull-up-20ma { ++ bias-pull-up; ++ drive-strength = <20>; ++ }; ++ + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + +- pcfg_pull_up_2ma: pcfg-pull-up-2ma { +- bias-pull-up; +- drive-strength = <2>; ++ pcfg_pull_down_8ma: pcfg-pull-down-8ma { ++ bias-pull-down; ++ drive-strength = <8>; + }; + + pcfg_pull_down_12ma: pcfg-pull-down-12ma { +@@ -1943,9 +1973,22 @@ + drive-strength = <12>; + }; + +- pcfg_pull_none_13ma: pcfg-pull-none-13ma { +- bias-disable; +- drive-strength = <13>; ++ pcfg_pull_down_18ma: pcfg-pull-down-18ma { ++ bias-pull-down; ++ drive-strength = <18>; ++ }; ++ ++ pcfg_pull_down_20ma: pcfg-pull-down-20ma { ++ bias-pull-down; ++ drive-strength = <20>; ++ }; ++ ++ pcfg_output_high: pcfg-output-high { ++ output-high; ++ }; ++ ++ pcfg_output_low: pcfg-output-low { ++ output-low; + }; + + clock { +@@ -2468,45 +2511,60 @@ + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = +- <4 18 RK_FUNC_1 &pcfg_pull_none>; ++ <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; ++ }; ++ ++ pwm0_pin_pull_down: pwm0-pin-pull-down { ++ rockchip,pins = ++ <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>; + }; + + vop0_pwm_pin: vop0-pwm-pin { + rockchip,pins = +- <4 18 RK_FUNC_2 &pcfg_pull_none>; ++ <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; ++ }; ++ ++ vop1_pwm_pin: vop1-pwm-pin { ++ rockchip,pins = ++ <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = +- <4 22 RK_FUNC_1 &pcfg_pull_none>; ++ <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; + }; + +- vop1_pwm_pin: vop1-pwm-pin { ++ pwm1_pin_pull_down: pwm1-pin-pull-down { + rockchip,pins = +- <4 18 RK_FUNC_3 &pcfg_pull_none>; ++ <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = +- <1 19 RK_FUNC_1 &pcfg_pull_none>; ++ <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; ++ }; ++ ++ pwm2_pin_pull_down: pwm2-pin-pull-down { ++ rockchip,pins = ++ <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; + }; + }; + + pwm3a { + pwm3a_pin: pwm3a-pin { + rockchip,pins = +- <0 6 RK_FUNC_1 &pcfg_pull_none>; ++ <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm3b { + pwm3b_pin: pwm3b-pin { + rockchip,pins = +- <1 14 RK_FUNC_1 &pcfg_pull_none>; ++ <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + +-- +cgit 1.2-0.3.lf.el7 +From 7c41a3f42a51d88e271c989c16be178bd6d38dfe Mon Sep 17 00:00:00 2001 +From: Peter Robinson <pbrobinson@gmail.com> +Date: Mon, 10 Sep 2018 18:17:36 +0100 +Subject: [PATCH 1/4] arm64: dts: rockchip: add 96boards RK3399 Ficus board + +The RK3399 Ficus board is an Enterprise Edition board +manufactured by Vamrs Ltd., based on the Rockchip RK3399 SoC. + +The board exposes a bunch of nice peripherals, including +SATA, HDMI, MIPI CSI, Ethernet, WiFi, and PCIe. + +Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> +Reviewed-by: Rob Herring <robh@kernel.org> +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +Signed-off-by: Peter Robinson <pbrobinson@gmail.com> +--- + .../devicetree/bindings/arm/rockchip.txt | 5 + + arch/arm64/boot/dts/rockchip/Makefile | 1 + + arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 514 ++++++++++++++++++ + 3 files changed, 520 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-ficus.dts + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt +index 1c1d62d03c4f..d46c5d43e27f 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.txt ++++ b/Documentation/devicetree/bindings/arm/rockchip.txt +@@ -1,5 +1,10 @@ + Rockchip platforms device tree bindings + --------------------------------------- ++ ++- 96boards RK3399 Ficus (ROCK960 Enterprise Edition) ++ Required root node properties: ++ - compatible = "vamrs,ficus", "rockchip,rk3399"; ++ + - Amarula Vyasa RK3288 board + Required root node properties: + - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 48a83f882947..2811fb701f12 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +new file mode 100644 +index 000000000000..0d14183dd4a9 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +@@ -0,0 +1,514 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2018 Collabora Ltd. ++ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. ++ * ++ * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw ++ */ ++ ++/dts-v1/; ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ model = "96boards RK3399 Ficus"; ++ compatible = "vamrs,ficus", "rockchip,rk3399"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc1v8_s0: vcc1v8-s0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_s0"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_drv>; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_pcie"; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 0>; ++ regulator-name = "vdd_log"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ /* for rockchip boot on */ ++ rockchip,pwm_id= <2>; ++ rockchip,pwm_voltage = <900000>; ++ ++ vin-supply = <&vcc_sys>; ++ }; ++ ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc3v3_sys>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x28>; ++ rx_delay = <0x11>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ status = "okay"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc_sys>; ++ vcc10-supply = <&vcc_sys>; ++ vcc11-supply = <&vcc_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_hdmi: LDO_REG2 { ++ regulator-name = "vcca1v8_hdmi"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG3 { ++ regulator-name = "vcca_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sd: LDO_REG4 { ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc3v0_sd: LDO_REG5 { ++ regulator-name = "vcc3v0_sd"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca0v9_hdmi: LDO_REG7 { ++ regulator-name = "vcca0v9_hdmi"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-name = "vcc_3v0"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++}; ++ ++&i2c2 { ++ status = "okay"; ++}; ++ ++&i2c3 { ++ status = "okay"; ++}; ++ ++&i2c4 { ++ status = "okay"; ++}; ++ ++&io_domains { ++ bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ ++ audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ ++ sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ ++ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; ++ num-lanes = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_clkreqn_cpm>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gmac { ++ rgmii_sleep_pins: rgmii-sleep-pins { ++ rockchip,pins = ++ <3 15 RK_FUNC_GPIO &pcfg_output_low>; ++ }; ++ }; ++ ++ sdmmc { ++ sdmmc_bus1: sdmmc-bus1 { ++ rockchip,pins = ++ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; ++ }; ++ ++ sdmmc_bus4: sdmmc-bus4 { ++ rockchip,pins = ++ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, ++ <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, ++ <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, ++ <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; ++ }; ++ ++ sdmmc_clk: sdmmc-clk { ++ rockchip,pins = ++ <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; ++ }; ++ ++ sdmmc_cmd: sdmmc-cmd { ++ rockchip,pins = ++ <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; ++ }; ++ }; ++ ++ pcie { ++ pcie_drv: pcie-drv { ++ rockchip,pins = ++ <1 24 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <1 21 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = ++ <1 17 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = ++ <1 14 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&pwm3 { ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ clock-frequency = <100000000>; ++ clock-freq-min-max = <100000 100000000>; ++ disable-wp; ++ sd-uhs-sdr104; ++ vqmmc-supply = <&vcc_sd>; ++ card-detect-delay = <800>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; +-- +2.19.0.rc1 + +From 2e3f4fb6f0a94b6cf56407536414b93bd3c45471 Mon Sep 17 00:00:00 2001 +From: Enric Balletbo i Serra <enric.balletbo@collabora.com> +Date: Sat, 14 Jul 2018 14:09:22 -0300 +Subject: [PATCH 2/4] arm64: dts: rockchip: add USB 2.0 and 3.0 support on + Ficus board + +The board exposes two types A ports, one is USB 3.0, up to 5.0Gbps and +another one is USB 2.0 up to 480Mbps. Enable the USB PHYs and the USB +controllers to enable theses devices. + +Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> +Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 88 +++++++++++++++++++ + 1 file changed, 88 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +index 0d14183dd4a9..890b9e13cfe8 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +@@ -61,6 +61,19 @@ + vin-supply = <&vcc3v3_sys>; + }; + ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&host_vbus_drv>; ++ regulator-name = "vcc5v0_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 0>; +@@ -454,6 +467,13 @@ + <1 14 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; ++ ++ usb2 { ++ host_vbus_drv: host-vbus-drv { ++ rockchip,pins = ++ <4 27 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + + &pwm2 { +@@ -487,6 +507,40 @@ + status = "okay"; + }; + ++&tcphy0 { ++ status = "okay"; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&u2phy1_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; +@@ -497,6 +551,40 @@ + status = "okay"; + }; + ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ + &vopb { + status = "okay"; + }; +-- +2.19.0.rc1 + +From d875193399378e17911829b9df9d27fd4a1ba195 Mon Sep 17 00:00:00 2001 +From: Enric Balletbo i Serra <enric.balletbo@collabora.com> +Date: Sat, 14 Jul 2018 14:09:22 -0300 +Subject: [PATCH 3/4] arm64: dts: rockchip: add voltage properties for + vcc3v3_pcie on rk3399 ficus + +The vcc3v3_pcie regulator supplies 3.3V so add voltage properties +for it. + +Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> +Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> +[split off from original patch] +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +index 890b9e13cfe8..6295483b701f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +@@ -58,6 +58,8 @@ + pinctrl-0 = <&pcie_drv>; + regulator-boot-on; + regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + +-- +2.19.0.rc1 + +From 416756dbf32ff2394b320fa88c09e9461496fc4c Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner <heiko@sntech.de> +Date: Mon, 16 Jul 2018 18:52:44 +0200 +Subject: [PATCH 4/4] arm64: dts: rockchip: drop out-of-tree properties from + rk3399-ficus regulator + +The pwm-regulator for vdd_log uses additional unreviewed properties in the +vendor kernel, which slipped in with the devicetree. +As written, they are unreviewed and unused in all mainline implementations +so drop them again. + +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +index 6295483b701f..8978d924eb83 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +@@ -84,11 +84,6 @@ + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; +- +- /* for rockchip boot on */ +- rockchip,pwm_id= <2>; +- rockchip,pwm_voltage = <900000>; +- + vin-supply = <&vcc_sys>; + }; + +-- +2.19.0.rc1 + |