diff options
-rw-r--r-- | arm64-pwm-rockchip-Keep-enabled-PWMs-running-while-probing.patch | 141 | ||||
-rw-r--r-- | arm64-rockchip-pinebookpro-add-fuel-gauge.patch | 59 | ||||
-rw-r--r-- | arm64-tegra-enable-dfll-on-jetson-nano.patch | 86 | ||||
-rw-r--r-- | iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch | 48 | ||||
-rw-r--r-- | kernel.spec | 19 |
5 files changed, 350 insertions, 3 deletions
diff --git a/arm64-pwm-rockchip-Keep-enabled-PWMs-running-while-probing.patch b/arm64-pwm-rockchip-Keep-enabled-PWMs-running-while-probing.patch new file mode 100644 index 000000000..4bdb5cb76 --- /dev/null +++ b/arm64-pwm-rockchip-Keep-enabled-PWMs-running-while-probing.patch @@ -0,0 +1,141 @@ +From patchwork Sat Sep 19 19:33:06 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: Simon South <simon@simonsouth.net> +X-Patchwork-Id: 11787259 +Return-Path: + <SRS0=uBh2=C4=lists.infradead.org=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@kernel.org> +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D0780618 + for <patchwork-linux-arm@patchwork.kernel.org>; + Sat, 19 Sep 2020 19:33:55 +0000 (UTC) +Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by mail.kernel.org (Postfix) with ESMTPS id 9DF4C21707 + for <patchwork-linux-arm@patchwork.kernel.org>; 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Sat, 19 Sep 2020 19:33:37 +0000 (UTC) +Received: from jupiter.simonsouth.net (unknown [108.162.141.195]) + (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) + (No client certificate requested) + by mailout.easymail.ca (Postfix) with ESMTPSA id 77C83A025D; + Sat, 19 Sep 2020 19:33:27 +0000 (UTC) +From: Simon South <simon@simonsouth.net> +To: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, + lee.jones@linaro.org, heiko@sntech.de, linux-pwm@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org +Subject: [PATCH v2] pwm: rockchip: Keep enabled PWMs running while probing +Date: Sat, 19 Sep 2020 15:33:06 -0400 +Message-Id: <20200919193306.1023-1-simon@simonsouth.net> +X-Mailer: git-send-email 2.28.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20200919_153338_624271_ABEEE8C4 +X-CRM114-Status: GOOD ( 16.76 ) +X-Spam-Score: -2.3 (--) +X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: + Content analysis details: (-2.3 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, + medium trust [64.68.200.34 listed in list.dnswl.org] + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + -0.0 SPF_PASS SPF: sender matches SPF record +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: <linux-arm-kernel.lists.infradead.org> +List-Unsubscribe: + <http://lists.infradead.org/mailman/options/linux-arm-kernel>, + <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe> +List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/> +List-Post: <mailto:linux-arm-kernel@lists.infradead.org> +List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help> +List-Subscribe: + <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, + <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe> +Cc: Simon South <simon@simonsouth.net> +Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> +Errors-To: + linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org + +Following commit cfc4c189bc70 ("pwm: Read initial hardware state at +request time") the Rockchip PWM driver can no longer assume a device's +pwm_state structure has been populated after a call to pwmchip_add(). +Consequently, the test in rockchip_pwm_probe() intended to prevent the +driver from stopping PWM devices already enabled by the bootloader no +longer functions reliably and this can lead to the kernel hanging +during startup, particularly on devices like the Pinebook Pro that use +a PWM-controlled backlight for their display. + +Avoid this by querying the device directly at probe time to determine +whether or not it is enabled. + +Fixes: cfc4c189bc70 ("pwm: Read initial hardware state at request time") +Signed-off-by: Simon South <simon@simonsouth.net> +Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> +Reviewed-by: Heiko Stuebner <heiko@sntech.de> +--- + drivers/pwm/pwm-rockchip.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c +index eb8c9cb645a6..098e94335cb5 100644 +--- a/drivers/pwm/pwm-rockchip.c ++++ b/drivers/pwm/pwm-rockchip.c +@@ -288,6 +288,7 @@ static int rockchip_pwm_probe(struct platform_device *pdev) + const struct of_device_id *id; + struct rockchip_pwm_chip *pc; + struct resource *r; ++ u32 enable_conf, ctrl; + int ret, count; + + id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); +@@ -362,7 +363,9 @@ static int rockchip_pwm_probe(struct platform_device *pdev) + } + + /* Keep the PWM clk enabled if the PWM appears to be up and running. */ +- if (!pwm_is_enabled(pc->chip.pwms)) ++ enable_conf = pc->data->enable_conf; ++ ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); ++ if ((ctrl & enable_conf) != enable_conf) + clk_disable(pc->clk); + + return 0; diff --git a/arm64-rockchip-pinebookpro-add-fuel-gauge.patch b/arm64-rockchip-pinebookpro-add-fuel-gauge.patch new file mode 100644 index 000000000..5decda78a --- /dev/null +++ b/arm64-rockchip-pinebookpro-add-fuel-gauge.patch @@ -0,0 +1,59 @@ +From c7c4d698cd2882c4d095aeed43bbad6fc990e998 Mon Sep 17 00:00:00 2001 +From: Tobias Schramm <t.schramm@manjaro.org> +Date: Thu, 28 May 2020 19:25:50 +0200 +Subject: arm64: dts: rockchip: add fuel gauge to Pinebook Pro dts + +This commit adds cw2015 fuel gauge and battery to the Pinebook Pro dts. + +Signed-off-by: Tobias Schramm <t.schramm@manjaro.org> +Link: https://lore.kernel.org/r/20200528172550.2324722-2-t.schramm@manjaro.org +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3399-pinebook-pro.dts | 25 ++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index cb0245d2226d5..8f5b2df01560e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -28,6 +28,13 @@ + pwms = <&pwm0 0 740740 0>; + }; + ++ bat: battery { ++ compatible = "simple-battery"; ++ charge-full-design-microamp-hours = <9800000>; ++ voltage-max-design-microvolt = <4350000>; ++ voltage-min-design-microvolt = <3000000>; ++ }; ++ + edp_panel: edp-panel { + compatible = "boe,nv140fhmn49"; + backlight = <&backlight>; +@@ -741,6 +748,24 @@ + }; + }; + }; ++ ++ cw2015@62 { ++ compatible = "cellwise,cw2015"; ++ reg = <0x62>; ++ cellwise,battery-profile = /bits/ 8 < ++ 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63 ++ 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36 ++ 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69 ++ 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59 ++ 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17 ++ 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D ++ 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB ++ 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11 ++ >; ++ cellwise,monitor-interval-ms = <5000>; ++ monitored-battery = <&bat>; ++ power-supplies = <&mains_charger>, <&fusb0>; ++ }; + }; + + &i2s1 { +-- +cgit 1.2.3-1.el7 diff --git a/arm64-tegra-enable-dfll-on-jetson-nano.patch b/arm64-tegra-enable-dfll-on-jetson-nano.patch new file mode 100644 index 000000000..8add84fd0 --- /dev/null +++ b/arm64-tegra-enable-dfll-on-jetson-nano.patch @@ -0,0 +1,86 @@ +From 72fd21b62055b985d3e3fb72a1e70e3d09596174 Mon Sep 17 00:00:00 2001 +From: Peter Robinson <pbrobinson@gmail.com> +Date: Sun, 27 Sep 2020 18:20:41 +0100 +Subject: [PATCH] arm64: tegra: Enable DFLL support on Jetson Nano + +Populate the DFLL node and corresponding PWM pin nodes in order to +enable CPUFREQ support on the Jetson Nano platform. + +Signed-off-by: Jon Hunter <jonathanh@nvidia.com> +Signed-off-by: Thierry Reding <treding@nvidia.com> +--- + .../boot/dts/nvidia/tegra210-p3450-0000.dts | 50 +++++++++++++++---- + 1 file changed, 40 insertions(+), 10 deletions(-) + +diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +index 9bc52fdb393c..4d980d753a98 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts ++++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +@@ -101,6 +101,22 @@ gpu@57000000 { + status = "okay"; + }; + ++ pinmux@700008d4 { ++ dvfs_pwm_active_state: dvfs_pwm_active { ++ dvfs_pwm_pbb1 { ++ nvidia,pins = "dvfs_pwm_pbb1"; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ }; ++ }; ++ ++ dvfs_pwm_inactive_state: dvfs_pwm_inactive { ++ dvfs_pwm_pbb1 { ++ nvidia,pins = "dvfs_pwm_pbb1"; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ }; ++ }; ++ }; ++ + /* debug port */ + serial@70006000 { + status = "okay"; +@@ -574,17 +590,31 @@ sdhci@700b0400 { + wakeup-source; + }; + +- clocks { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <0>; ++ clock@70110000 { ++ status = "okay"; + +- clk32k_in: clock@0 { +- compatible = "fixed-clock"; +- reg = <0>; +- #clock-cells = <0>; +- clock-frequency = <32768>; +- }; ++ nvidia,cf = <6>; ++ nvidia,ci = <0>; ++ nvidia,cg = <2>; ++ nvidia,droop-ctrl = <0x00000f00>; ++ nvidia,force-mode = <1>; ++ nvidia,sample-rate = <25000>; ++ ++ nvidia,pwm-min-microvolts = <708000>; ++ nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ ++ nvidia,pwm-to-pmic; ++ nvidia,pwm-tristate-microvolts = <1000000>; ++ nvidia,pwm-voltage-step-microvolts = <19200>; ++ ++ pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; ++ pinctrl-0 = <&dvfs_pwm_active_state>; ++ pinctrl-1 = <&dvfs_pwm_inactive_state>; ++ }; ++ ++ clk32k_in: clock@0 { ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ #clock-cells = <0>; + }; + + cpus { +-- +2.26.2 + diff --git a/iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch b/iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch new file mode 100644 index 000000000..381fb3659 --- /dev/null +++ b/iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch @@ -0,0 +1,48 @@ +From c461469e12073007ac4bbddd3a4830632c065738 Mon Sep 17 00:00:00 2001 +From: Peter Robinson <pbrobinson@gmail.com> +Date: Mon, 28 Sep 2020 11:34:09 +0100 +Subject: [PATCH] These two patches fix ACTIVE_TLB_LINES field setting in + tegra-smmu driver for Tegra210 platforms. + +This resend in series groups two previous seperate changes that're +corelated, being pointed out by Thierry. Also adding his Acked-by. + +Nicolin Chen (2): + iommu/tegra-smmu: Fix tlb_mask + memory: tegra: Correct num_tlb_lines for tegra210 + +Signed-off-by: Peter Robinson <pbrobinson@gmail.com> +--- + drivers/iommu/tegra-smmu.c | 2 +- + drivers/memory/tegra/tegra210.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c +index 7426b7666e2b..d5f1384ef6a1 100644 +--- a/drivers/iommu/tegra-smmu.c ++++ b/drivers/iommu/tegra-smmu.c +@@ -1022,7 +1022,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev, + smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; + dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", + mc->soc->num_address_bits, smmu->pfn_mask); +- smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1; ++ smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1; + dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines, + smmu->tlb_mask); + +diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c +index cc0482434c75..7212d1d7b348 100644 +--- a/drivers/memory/tegra/tegra210.c ++++ b/drivers/memory/tegra/tegra210.c +@@ -1073,7 +1073,7 @@ static const struct tegra_smmu_soc tegra210_smmu_soc = { + .num_groups = ARRAY_SIZE(tegra210_groups), + .supports_round_robin_arbitration = true, + .supports_request_limit = true, +- .num_tlb_lines = 32, ++ .num_tlb_lines = 48, + .num_asids = 128, + }; + +-- +2.26.2 + diff --git a/kernel.spec b/kernel.spec index 4988689c0..9a9002800 100644 --- a/kernel.spec +++ b/kernel.spec @@ -883,9 +883,6 @@ Patch103: arm64-tegra-Use-valid-PWM-period-for-VDD_GPU-on-Tegra210.patch # Goes away with 5.9 Patch105: 0001-platform-x86-thinkpad_acpi-lap-or-desk-mode-interfac.patch -# https://patchwork.kernel.org/patch/11796255/ -Patch106: arm64-dts-rockchip-disable-USB-type-c-DisplayPort.patch - # https://bugzilla.redhat.com/show_bug.cgi?id=1874117 Patch107: 0001-drivers-perf-xgene_pmu-Fix-uninitialized-resource-st.patch @@ -906,6 +903,19 @@ Patch114: v2-nfs-Fix-security-label-length-not-being-reset.patch # rhbz 1875339 1875828 1876997 Patch115: pdx86-SW_TABLET_MODE-fixes.patch +# https://patchwork.kernel.org/patch/11796255/ +Patch116: arm64-dts-rockchip-disable-USB-type-c-DisplayPort.patch + +# https://patchwork.kernel.org/patch/11787259/ +Patch117: arm64-pwm-rockchip-Keep-enabled-PWMs-running-while-probing.patch + +# Backport from 5.9 +Patch118: arm64-rockchip-pinebookpro-add-fuel-gauge.patch +Patch119: arm64-tegra-enable-dfll-on-jetson-nano.patch + +# https://www.spinics.net/lists/linux-tegra/msg53605.html +Patch120: iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch + # END OF PATCH DEFINITIONS %endif @@ -3022,6 +3032,9 @@ fi # # %changelog +* Mon Sep 28 06:48:48 CDT 2020 Justin M. Forbes <jforbes@fedoraproject.org> - 5.8.12-300 +- Linux v5.8.12 + * Wed Sep 23 06:58:55 CDT 2020 Justin M. Forbes <jforbes@fedoraproject.org> - 5.8.11-300 - Linux v5.8.11 - Fix (rhbz 1821946) |