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-rw-r--r--ARM-mvebu-change-order-of-ethernet-DT-nodes-on-Armada-38x.patch101
-rw-r--r--Fix-tegra-to-use-stdout-path-for-serial-console.patch318
-rw-r--r--Geekbox-device-tree-support.patch437
-rw-r--r--Initial-AllWinner-A64-and-PINE64-support.patch1882
-rw-r--r--config-arm-generic59
-rw-r--r--config-arm6428
-rw-r--r--config-armv724
-rw-r--r--config-armv7-generic75
-rw-r--r--kernel.spec17
9 files changed, 2881 insertions, 60 deletions
diff --git a/ARM-mvebu-change-order-of-ethernet-DT-nodes-on-Armada-38x.patch b/ARM-mvebu-change-order-of-ethernet-DT-nodes-on-Armada-38x.patch
new file mode 100644
index 000000000..cff3d3339
--- /dev/null
+++ b/ARM-mvebu-change-order-of-ethernet-DT-nodes-on-Armada-38x.patch
@@ -0,0 +1,101 @@
+From patchwork Wed Jan 27 15:08:19 2016
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: [1/2] ARM: mvebu: change order of ethernet DT nodes on Armada 38x
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+X-Patchwork-Id: 8134751
+Message-Id: <1453907300-28283-2-git-send-email-thomas.petazzoni@free-electrons.com>
+To: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
+ Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
+ Gregory Clement <gregory.clement@free-electrons.com>
+Cc: Nadav Haklai <nadavh@marvell.com>, Lior Amsalem <alior@marvell.com>,
+ Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
+ linux-arm-kernel@lists.infradead.org
+Date: Wed, 27 Jan 2016 16:08:19 +0100
+
+On Armada 38x, the available network interfaces are:
+
+ - port 0, at 0x70000
+ - port 1, at 0x30000
+ - port 2, at 0x34000
+
+Due to the rule saying that DT nodes should be ordered by register
+addresses, the network interfaces are probed in this order:
+
+ - port 1, at 0x30000, which gets named eth0
+ - port 2, at 0x34000, which gets named eth1
+ - port 0, at 0x70000, which gets named eth2
+
+(if all three ports are enabled at the board level)
+
+Unfortunately, the network subsystem doesn't provide any way to rename
+network interfaces from the kernel (it can only be done from
+userspace). So, the default naming of the network interfaces is very
+confusing as it doesn't match the datasheet, nor the naming of the
+interfaces in the bootloader, nor the naming of the interfaces on
+labels printed on the board.
+
+For example, on the Armada 388 GP, the board has two ports, labelled
+GE0 and GE1. One has to know that GE0 is eth1 and GE1 is eth0, which
+isn't really obvious.
+
+In order to solve this, this patch proposes to exceptionaly violate
+the rule of "order DT nodes by register address", and put the 0x70000
+node before the 0x30000 node, so that network interfaces get named in
+a more natural way.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+
+---
+arch/arm/boot/dts/armada-38x.dtsi | 30 +++++++++++++++++++++---------
+ 1 file changed, 21 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
+index e8b7f67..b50784d 100644
+--- a/arch/arm/boot/dts/armada-38x.dtsi
++++ b/arch/arm/boot/dts/armada-38x.dtsi
+@@ -429,6 +429,27 @@
+ reg = <0x22000 0x1000>;
+ };
+
++ /*
++ * As a special exception to the "order by
++ * register address" rule, the eth0 node is
++ * placed here to ensure that it gets
++ * registered as the first interface, since
++ * the network subsystem doesn't allow naming
++ * interfaces using DT aliases. Without this,
++ * the ordering of interfaces is different
++ * from the one used in U-Boot and the
++ * labeling of interfaces on the boards, which
++ * is very confusing for users.
++ */
++ eth0: ethernet@70000 {
++ compatible = "marvell,armada-370-neta";
++ reg = <0x70000 0x4000>;
++ interrupts-extended = <&mpic 8>;
++ clocks = <&gateclk 4>;
++ tx-csum-limit = <9800>;
++ status = "disabled";
++ };
++
+ eth1: ethernet@30000 {
+ compatible = "marvell,armada-370-neta";
+ reg = <0x30000 0x4000>;
+@@ -493,15 +514,6 @@
+ };
+ };
+
+- eth0: ethernet@70000 {
+- compatible = "marvell,armada-370-neta";
+- reg = <0x70000 0x4000>;
+- interrupts-extended = <&mpic 8>;
+- clocks = <&gateclk 4>;
+- tx-csum-limit = <9800>;
+- status = "disabled";
+- };
+-
+ mdio: mdio@72004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
diff --git a/Fix-tegra-to-use-stdout-path-for-serial-console.patch b/Fix-tegra-to-use-stdout-path-for-serial-console.patch
new file mode 100644
index 000000000..80a2d1b95
--- /dev/null
+++ b/Fix-tegra-to-use-stdout-path-for-serial-console.patch
@@ -0,0 +1,318 @@
+From 15b8caef5f380d9465876478ff5e365bc6afa5b6 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Sun, 6 Mar 2016 10:59:13 +0000
+Subject: [PATCH] Fix tegra to use stdout-path for serial console
+
+---
+ arch/arm/boot/dts/tegra114-dalmore.dts | 4 ++++
+ arch/arm/boot/dts/tegra124-jetson-tk1.dts | 4 ++++
+ arch/arm/boot/dts/tegra124-nyan.dtsi | 4 ++++
+ arch/arm/boot/dts/tegra124-venice2.dts | 4 ++++
+ arch/arm/boot/dts/tegra20-harmony.dts | 4 ++++
+ arch/arm/boot/dts/tegra20-iris-512.dts | 4 ++++
+ arch/arm/boot/dts/tegra20-medcom-wide.dts | 4 ++++
+ arch/arm/boot/dts/tegra20-paz00.dts | 4 ++++
+ arch/arm/boot/dts/tegra20-seaboard.dts | 4 ++++
+ arch/arm/boot/dts/tegra20-tamonten.dtsi | 4 ++++
+ arch/arm/boot/dts/tegra20-trimslice.dts | 4 ++++
+ arch/arm/boot/dts/tegra20-ventana.dts | 4 ++++
+ arch/arm/boot/dts/tegra20-whistler.dts | 4 ++++
+ arch/arm/boot/dts/tegra30-apalis-eval.dts | 4 ++++
+ arch/arm/boot/dts/tegra30-beaver.dts | 4 ++++
+ arch/arm/boot/dts/tegra30-cardhu.dtsi | 4 ++++
+ arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 4 ++++
+ arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 5 ++++-
+ arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 4 ++++
+ 19 files changed, 76 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
+index 8b7aa0d..b5748ee 100644
+--- a/arch/arm/boot/dts/tegra114-dalmore.dts
++++ b/arch/arm/boot/dts/tegra114-dalmore.dts
+@@ -18,6 +18,10 @@
+ serial0 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+index 66b4451..abf046a 100644
+--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
++++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+@@ -15,6 +15,10 @@
+ serial0 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
+index ec1aa64..e2cd39e 100644
+--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
++++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
+@@ -8,6 +8,10 @@
+ serial0 = &uarta;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
+index cfbdf42..604f4b7 100644
+--- a/arch/arm/boot/dts/tegra124-venice2.dts
++++ b/arch/arm/boot/dts/tegra124-venice2.dts
+@@ -13,6 +13,10 @@
+ serial0 = &uarta;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
+index b926a07..4b73c76 100644
+--- a/arch/arm/boot/dts/tegra20-harmony.dts
++++ b/arch/arm/boot/dts/tegra20-harmony.dts
+@@ -13,6 +13,10 @@
+ serial0 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
+index 1dd7d7b..bb56dfe 100644
+--- a/arch/arm/boot/dts/tegra20-iris-512.dts
++++ b/arch/arm/boot/dts/tegra20-iris-512.dts
+@@ -11,6 +11,10 @@
+ serial1 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ host1x@50000000 {
+ hdmi@54280000 {
+ status = "okay";
+diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
+index 9b87526..34c6588 100644
+--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
++++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
+@@ -10,6 +10,10 @@
+ serial0 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ pwm@7000a000 {
+ status = "okay";
+ };
+diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
+index ed7e100..81a10a9 100644
+--- a/arch/arm/boot/dts/tegra20-paz00.dts
++++ b/arch/arm/boot/dts/tegra20-paz00.dts
+@@ -14,6 +14,10 @@
+ serial1 = &uartc;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
+index aea8994..0aed748 100644
+--- a/arch/arm/boot/dts/tegra20-seaboard.dts
++++ b/arch/arm/boot/dts/tegra20-seaboard.dts
+@@ -13,6 +13,10 @@
+ serial0 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
+index 13d4e61..025e9e8 100644
+--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
++++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
+@@ -10,6 +10,10 @@
+ serial0 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
+index d99af4e..69d25ca 100644
+--- a/arch/arm/boot/dts/tegra20-trimslice.dts
++++ b/arch/arm/boot/dts/tegra20-trimslice.dts
+@@ -13,6 +13,10 @@
+ serial0 = &uarta;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
+index 04c58e9..c61533a 100644
+--- a/arch/arm/boot/dts/tegra20-ventana.dts
++++ b/arch/arm/boot/dts/tegra20-ventana.dts
+@@ -13,6 +13,10 @@
+ serial0 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
+index 340d811..bd76585 100644
+--- a/arch/arm/boot/dts/tegra20-whistler.dts
++++ b/arch/arm/boot/dts/tegra20-whistler.dts
+@@ -13,6 +13,10 @@
+ serial0 = &uarta;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
+index f2879cf..b914bcb 100644
+--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
++++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
+@@ -17,6 +17,10 @@
+ serial3 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ pcie-controller@00003000 {
+ status = "okay";
+
+diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
+index 3dede39..1eca3b2 100644
+--- a/arch/arm/boot/dts/tegra30-beaver.dts
++++ b/arch/arm/boot/dts/tegra30-beaver.dts
+@@ -12,6 +12,10 @@
+ serial0 = &uarta;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x80000000 0x7ff00000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
+index bb1ca15..de9d6cc 100644
+--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
++++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
+@@ -35,6 +35,10 @@
+ serial1 = &uartc;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+index 3ff019f..93e1ffd 100644
+--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
++++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+@@ -15,6 +15,10 @@
+ serial2 = &uartd;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
+index 62f33fc..3c0b4d7 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
+@@ -10,9 +10,12 @@
+ aliases {
+ rtc0 = "/i2c@0,7000d000/as3722@40";
+ rtc1 = "/rtc@0,7000e000";
++ serial0 = &uarta;
+ };
+
+- chosen { };
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
+
+ memory {
+ device_type = "memory";
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
+index ece0dec..73ba582 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
+@@ -9,6 +9,10 @@
+ serial0 = &uarta;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0xc0000000>;
+--
+2.5.0
+
diff --git a/Geekbox-device-tree-support.patch b/Geekbox-device-tree-support.patch
new file mode 100644
index 000000000..51caf8aaf
--- /dev/null
+++ b/Geekbox-device-tree-support.patch
@@ -0,0 +1,437 @@
+From a516bbf04744817e49e173b2a217a2a6366b5f9c Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Wed, 2 Mar 2016 18:12:09 +0000
+Subject: [PATCH] Geekbox device tree support
+
+---
+ Documentation/devicetree/bindings/arm/rockchip.txt | 9 +
+ arch/arm64/boot/dts/rockchip/Makefile | 2 +
+ .../dts/rockchip/rk3368-geekbox-landingship.dts | 56 ++++
+ arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts | 321 +++++++++++++++++++++
+ 4 files changed, 388 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-geekbox-landingship.dts
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+
+diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
+index 078c14f..c6d95f2 100644
+--- a/Documentation/devicetree/bindings/arm/rockchip.txt
++++ b/Documentation/devicetree/bindings/arm/rockchip.txt
+@@ -87,6 +87,15 @@ Rockchip platforms device tree bindings
+ "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
+ "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
+
++- GeekBuying GeekBox:
++ Required root node properties:
++ - compatible = "geekbuying,geekbox", "rockchip,rk3368";
++
++- GeekBuying Landingship:
++ Required root node properties:
++ - compatible = "geekbuying,landingship",
++ "geekbuying,geekbox", "rockchip,rk3368";
++
+ - Rockchip RK3368 evb:
+ Required root node properties:
+ - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index e3f0b5f..201bcd9 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -1,4 +1,6 @@
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox-landingship.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
+
+ always := $(dtb-y)
+diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox-landingship.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox-landingship.dts
+new file mode 100644
+index 0000000..e4a1175
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox-landingship.dts
+@@ -0,0 +1,56 @@
++/*
++ * Copyright (c) 2016 Andreas Färber
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "rk3368-geekbox.dts"
++
++/ {
++ model = "GeekBox on Landingship";
++ compatible = "geekbuying,landingship", "geekbuying,geekbox", "rockchip,rk3368";
++};
++
++&i2c1 {
++ status = "okay";
++};
++
++&i2c2 {
++ status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+new file mode 100644
+index 0000000..7e51876
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+@@ -0,0 +1,321 @@
++/*
++ * Copyright (c) 2016 Andreas Färber
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "rk3368.dtsi"
++
++/ {
++ model = "GeekBox";
++ compatible = "geekbuying,geekbox", "rockchip,rk3368";
++
++ chosen {
++ stdout-path = "serial2:115200n8";
++ };
++
++ memory {
++ device_type = "memory";
++ reg = <0x0 0x0 0x0 0x80000000>;
++ };
++
++ ext_gmac: gmac-clk {
++ compatible = "fixed-clock";
++ clock-frequency = <125000000>;
++ clock-output-names = "ext_gmac";
++ #clock-cells = <0>;
++ };
++
++ ir: ir-receiver {
++ compatible = "gpio-ir-receiver";
++ gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&ir_int>;
++ };
++
++ keys: gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwr_key>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ button@0 {
++ reg = <0>;
++ gpio-key,wakeup = <1>;
++ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
++ label = "GPIO Power";
++ linux,code = <116>;
++ };
++ };
++
++ leds: gpio-leds {
++ compatible = "gpio-leds";
++
++ blue {
++ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
++ label = "geekbox:blue:led";
++ default-state = "on";
++ };
++
++ red {
++ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
++ label = "geekbox:red:led";
++ default-state = "off";
++ };
++ };
++
++ vcc_sys: vcc-sys-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_sys";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ regulator-boot-on;
++ };
++};
++
++&emmc {
++ status = "okay";
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ clock-frequency = <150000000>;
++ disable-wp;
++ keep-power-in-suspend;
++ non-removable;
++ num-slots = <1>;
++ vmmc-supply = <&vcc_io>;
++ vqmmc-supply = <&vcc18_flash>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
++};
++
++&gmac {
++ status = "okay";
++ phy-supply = <&vcc_lan>;
++ phy-mode = "rgmii";
++ clock_in_out = "input";
++ assigned-clocks = <&cru SCLK_MAC>;
++ assigned-clock-parents = <&ext_gmac>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmii_pins>;
++ tx_delay = <0x30>;
++ rx_delay = <0x10>;
++};
++
++&i2c0 {
++ status = "okay";
++
++ rk808: pmic@1b {
++ compatible = "rockchip,rk808";
++ reg = <0x1b>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
++ rockchip,system-power-controller;
++ vcc1-supply = <&vcc_sys>;
++ vcc2-supply = <&vcc_sys>;
++ vcc3-supply = <&vcc_sys>;
++ vcc4-supply = <&vcc_sys>;
++ vcc6-supply = <&vcc_sys>;
++ vcc7-supply = <&vcc_sys>;
++ vcc8-supply = <&vcc_io>;
++ vcc9-supply = <&vcc_sys>;
++ vcc10-supply = <&vcc_sys>;
++ vcc11-supply = <&vcc_sys>;
++ vcc12-supply = <&vcc_io>;
++ clock-output-names = "xin32k", "rk808-clkout2";
++ #clock-cells = <1>;
++
++ regulators {
++ vdd_cpu: DCDC_REG1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <700000>;
++ regulator-max-microvolt = <1500000>;
++ regulator-name = "vdd_cpu";
++ };
++
++ vdd_log: DCDC_REG2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <700000>;
++ regulator-max-microvolt = <1500000>;
++ regulator-name = "vdd_log";
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vcc_ddr";
++ };
++
++ vcc_io: DCDC_REG4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_io";
++ };
++
++ vcc18_flash: LDO_REG1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc18_flash";
++ };
++
++ vcc33_lcd: LDO_REG2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc33_lcd";
++ };
++
++ vdd_10: LDO_REG3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-name = "vdd_10";
++ };
++
++ vcca_18: LDO_REG4 {
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca_18";
++ };
++
++ vccio_sd: LDO_REG5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vccio_sd";
++ };
++
++ vdd10_lcd: LDO_REG6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-name = "vdd10_lcd";
++ };
++
++ vcc_18: LDO_REG7 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_18";
++ };
++
++ vcc18_lcd: LDO_REG8 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc18_lcd";
++ };
++
++ vcc_sd: SWITCH_REG1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vcc_sd";
++ };
++
++ vcc_lan: SWITCH_REG2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vcc_lan";
++ };
++ };
++ };
++};
++
++&pinctrl {
++ ir {
++ ir_int: ir-int {
++ rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ keys {
++ pwr_key: pwr-key {
++ rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ pmic {
++ pmic_sleep: pmic-sleep {
++ rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
++ };
++
++ pmic_int: pmic-int {
++ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++};
++
++&tsadc {
++ status = "okay";
++ rockchip,hw-tshut-mode = <0>; /* CRU */
++ rockchip,hw-tshut-polarity = <0>; /* low */
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_otg {
++ status = "okay";
++};
++
++&wdt {
++ status = "okay";
++};
+--
+2.5.0
+
diff --git a/Initial-AllWinner-A64-and-PINE64-support.patch b/Initial-AllWinner-A64-and-PINE64-support.patch
new file mode 100644
index 000000000..d21cbc1ca
--- /dev/null
+++ b/Initial-AllWinner-A64-and-PINE64-support.patch
@@ -0,0 +1,1882 @@
+From 97f002d28e975991226ab70599731bd2ccc8c060 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Sun, 6 Mar 2016 12:06:41 +0000
+Subject: [PATCH] Initial AllWinner A64 and PINE64 support
+
+---
+ Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
+ Documentation/devicetree/bindings/clock/sunxi.txt | 7 +
+ .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
+ .../devicetree/bindings/vendor-prefixes.txt | 1 +
+ arch/arm/boot/dts/sun8i-h3.dtsi | 18 +-
+ arch/arm/mach-sunxi/Kconfig | 7 +
+ arch/arm64/Kconfig.platforms | 6 +
+ arch/arm64/boot/dts/Makefile | 1 +
+ arch/arm64/boot/dts/allwinner/Makefile | 5 +
+ .../dts/allwinner/sun50i-a64-pine64-common.dtsi | 80 +++
+ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 59 ++
+ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 58 ++
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 624 +++++++++++++++++++++
+ drivers/clk/sunxi/Makefile | 1 +
+ drivers/clk/sunxi/clk-factors.c | 3 +-
+ drivers/clk/sunxi/clk-factors.h | 1 +
+ drivers/clk/sunxi/clk-multi-gates.c | 105 ++++
+ drivers/clk/sunxi/clk-sunxi.c | 4 +-
+ drivers/crypto/Kconfig | 2 +-
+ drivers/pinctrl/sunxi/Kconfig | 4 +
+ drivers/pinctrl/sunxi/Makefile | 1 +
+ drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 602 ++++++++++++++++++++
+ drivers/rtc/Kconfig | 7 +-
+ 23 files changed, 1582 insertions(+), 16 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-common.dtsi
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+ create mode 100644 drivers/clk/sunxi/clk-multi-gates.c
+ create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
+
+diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
+index bb9b0faa..8b39d2b 100644
+--- a/Documentation/devicetree/bindings/arm/sunxi.txt
++++ b/Documentation/devicetree/bindings/arm/sunxi.txt
+@@ -13,3 +13,4 @@ using one of the following compatible strings:
+ allwinner,sun8i-a33
+ allwinner,sun8i-h3
+ allwinner,sun9i-a80
++ allwinner,sun50i-a64
+diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
+index e59f57b..8af12b5 100644
+--- a/Documentation/devicetree/bindings/clock/sunxi.txt
++++ b/Documentation/devicetree/bindings/clock/sunxi.txt
+@@ -77,6 +77,8 @@ Required properties:
+ "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
+ "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
+ "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
++ "allwinner,sunxi-multi-bus-gates-clk" - for the multi-parent bus gates
++ "allwinner,sun50i-a64-bus-gates-clk" - for the bus gates on A64
+
+ Required properties for all clocks:
+ - reg : shall be the control register address for the clock.
+@@ -117,6 +119,11 @@ For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
+ is the normal PLL6 output, or "pll6". The second output is rate doubled
+ PLL6, or "pll6x2".
+
++The "allwinner,sunxi-multi-bus-gates-clk" holds the actual clocks in
++child nodes, where each one specifies the parent clock that the particular
++gates are depending from. The child nodes each follow the common clock
++binding as described in this document.
++
+ The "allwinner,*-mmc-clk" clocks have three different outputs: the
+ main clock, with the ID 0, and the output and sample clocks, with the
+ IDs 1 and 2, respectively.
+diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+index 9213b27..08b2361 100644
+--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+@@ -21,6 +21,7 @@ Required properties:
+ "allwinner,sun9i-a80-r-pinctrl"
+ "allwinner,sun8i-a83t-pinctrl"
+ "allwinner,sun8i-h3-pinctrl"
++ "allwinner,sun50i-a64-pinctrl"
+
+ - reg: Should contain the register physical address and length for the
+ pin controller.
+diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
+index 72e2c5a..0c22fa9 100644
+--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
++++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
+@@ -175,6 +175,7 @@ parade Parade Technologies Inc.
+ pericom Pericom Technology Inc.
+ phytec PHYTEC Messtechnik GmbH
+ picochip Picochip Ltd
++pine64 Pine64
+ plathome Plat'Home Co., Ltd.
+ plda PLDA
+ pixcir PIXCIR MICROELECTRONICS Co., Ltd
+diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
+index 1524130e..7c50fa0 100644
+--- a/arch/arm/boot/dts/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/sun8i-h3.dtsi
+@@ -137,12 +137,12 @@
+ clock-output-names = "pll6d2";
+ };
+
+- /* dummy clock until pll6 can be reused */
+- pll8: pll8_clk {
+- #clock-cells = <0>;
+- compatible = "fixed-clock";
+- clock-frequency = <1>;
+- clock-output-names = "pll8";
++ pll8: clk@c01c20044 {
++ #clock-cells = <1>;
++ compatible = "allwinner,sun6i-a31-pll6-clk";
++ reg = <0x01c20044 0x4>;
++ clocks = <&osc24M>;
++ clock-output-names = "pll8", "pll8x2";
+ };
+
+ cpu: cpu_clk@01c20050 {
+@@ -243,7 +243,7 @@
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+- clocks = <&osc24M>, <&pll6 0>, <&pll8>;
++ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+@@ -253,7 +253,7 @@
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+- clocks = <&osc24M>, <&pll6 0>, <&pll8>;
++ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+@@ -263,7 +263,7 @@
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+- clocks = <&osc24M>, <&pll6 0>, <&pll8>;
++ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
+index c124d65..b305f5b 100644
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -46,4 +46,11 @@ config MACH_SUN9I
+ default ARCH_SUNXI
+ select ARM_GIC
+
++config MACH_SUN50I
++ bool "Allwinner A64 (sun50i) SoCs support"
++ default ARCH_SUNXI
++ select ARM_GIC
++ select HAVE_ARM_ARCH_TIMER
++ select PINCTRL_SUN50I_A64
++
+ endif
+diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
+index 21074f6..63a690d 100644
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -72,6 +72,12 @@ config ARCH_SEATTLE
+ config ARCH_SHMOBILE
+ bool
+
++config ARCH_SUNXI
++ bool "Allwinner sunxi 64-bit SoC Family"
++ select PINCTRL_SUN50I_A64
++ help
++ This enables support for Allwinner sunxi based SoCs like the A64.
++
+ config ARCH_RENESAS
+ bool "Renesas SoC Platforms"
+ select ARCH_SHMOBILE
+diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
+index f832b8a..3b7428a 100644
+--- a/arch/arm64/boot/dts/Makefile
++++ b/arch/arm64/boot/dts/Makefile
+@@ -1,3 +1,4 @@
++dts-dirs += allwinner
+ dts-dirs += altera
+ dts-dirs += amd
+ dts-dirs += apm
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+new file mode 100644
+index 0000000..1e29a5a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -0,0 +1,5 @@
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
++
++always := $(dtb-y)
++subdir-y := $(dts-dirs)
++clean-files := *.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-common.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-common.dtsi
+new file mode 100644
+index 0000000..d5a7249
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-common.dtsi
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (c) 2016 ARM Ltd.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "sun50i-a64.dtsi"
++
++/ {
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ soc {
++ reg_vcc3v3: vcc3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++ };
++};
++
++&mmc0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
++ vmmc-supply = <&reg_vcc3v3>;
++ cd-gpios = <&pio 5 6 0>;
++ cd-inverted;
++ status = "okay";
++};
++
++&uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0_pins_a>;
++ status = "okay";
++};
++
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pins>;
++ status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+new file mode 100644
+index 0000000..549dc15
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+@@ -0,0 +1,59 @@
++/*
++ * Copyright (c) 2016 ARM Ltd.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-pine64-common.dtsi"
++
++/ {
++ model = "Pine64+";
++ compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ /* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
++ memory {
++ reg = <0x40000000 0x40000000>;
++ };
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+new file mode 100644
+index 0000000..ebe029e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -0,0 +1,58 @@
++/*
++ * Copyright (c) 2016 ARM Ltd.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-pine64-common.dtsi"
++
++/ {
++ model = "Pine64";
++ compatible = "pine64,pine64", "allwinner,sun50i-a64";
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory {
++ reg = <0x40000000 0x20000000>;
++ };
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+new file mode 100644
+index 0000000..1bd436f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -0,0 +1,624 @@
++/*
++ * Copyright (C) 2016 ARM Ltd.
++ * based on the Allwinner H3 dtsi:
++ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
++
++/ {
++ interrupt-parent = <&gic>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ compatible = "arm,cortex-a53", "arm,armv8";
++ device_type = "cpu";
++ reg = <0>;
++ enable-method = "psci";
++ };
++
++ cpu@1 {
++ compatible = "arm,cortex-a53", "arm,armv8";
++ device_type = "cpu";
++ reg = <1>;
++ enable-method = "psci";
++ };
++
++ cpu@2 {
++ compatible = "arm,cortex-a53", "arm,armv8";
++ device_type = "cpu";
++ reg = <2>;
++ enable-method = "psci";
++ };
++
++ cpu@3 {
++ compatible = "arm,cortex-a53", "arm,armv8";
++ device_type = "cpu";
++ reg = <3>;
++ enable-method = "psci";
++ };
++ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
++
++ memory {
++ device_type = "memory";
++ reg = <0x40000000 0>;
++ };
++
++ gic: interrupt-controller@1c81000 {
++ compatible = "arm,gic-400";
++ interrupt-controller;
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++
++ reg = <0x01c81000 0x1000>,
++ <0x01c82000 0x2000>,
++ <0x01c84000 0x2000>,
++ <0x01c86000 0x2000>;
++ interrupts = <GIC_PPI 9
++ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13
++ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
++ <GIC_PPI 14
++ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
++ <GIC_PPI 11
++ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
++ <GIC_PPI 10
++ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++ };
++
++ clocks {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ osc24M: osc24M_clk {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <24000000>;
++ clock-output-names = "osc24M";
++ };
++
++ osc32k: osc32k_clk {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <32768>;
++ clock-output-names = "osc32k";
++ };
++
++ pll1: pll1_clk@1c20000 {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun8i-a23-pll1-clk";
++ reg = <0x01c20000 0x4>;
++ clocks = <&osc24M>;
++ clock-output-names = "pll1";
++ };
++
++ pll6: pll6_clk@1c20028 {
++ #clock-cells = <1>;
++ compatible = "allwinner,sun6i-a31-pll6-clk";
++ reg = <0x01c20028 0x4>;
++ clocks = <&osc24M>;
++ clock-output-names = "pll6", "pll6x2";
++ };
++
++ pll6d2: pll6d2_clk {
++ #clock-cells = <0>;
++ compatible = "fixed-factor-clock";
++ clock-div = <2>;
++ clock-mult = <1>;
++ clocks = <&pll6 0>;
++ clock-output-names = "pll6d2";
++ };
++
++ pll7: pll7_clk@1c2002c {
++ #clock-cells = <1>;
++ compatible = "allwinner,sun6i-a31-pll6-clk";
++ reg = <0x01c2002c 0x4>;
++ clocks = <&osc24M>;
++ clock-output-names = "pll7", "pll7x2";
++ };
++
++ cpu: cpu_clk@1c20050 {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun4i-a10-cpu-clk";
++ reg = <0x01c20050 0x4>;
++ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
++ clock-output-names = "cpu";
++ critical-clocks = <0>;
++ };
++
++ axi: axi_clk@1c20050 {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun4i-a10-axi-clk";
++ reg = <0x01c20050 0x4>;
++ clocks = <&cpu>;
++ clock-output-names = "axi";
++ };
++
++ ahb1: ahb1_clk@1c20054 {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun6i-a31-ahb1-clk";
++ reg = <0x01c20054 0x4>;
++ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
++ clock-output-names = "ahb1";
++ };
++
++ ahb2: ahb2_clk@1c2005c {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun8i-h3-ahb2-clk";
++ reg = <0x01c2005c 0x4>;
++ clocks = <&ahb1>, <&pll6d2>;
++ clock-output-names = "ahb2";
++ };
++
++ apb1: apb1_clk@1c20054 {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun4i-a10-apb0-clk";
++ reg = <0x01c20054 0x4>;
++ clocks = <&ahb1>;
++ clock-output-names = "apb1";
++ };
++
++ apb2: apb2_clk@1c20058 {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun4i-a10-apb1-clk";
++ reg = <0x01c20058 0x4>;
++ clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
++ clock-output-names = "apb2";
++ };
++
++ bus_gates: bus_gates_clk@1c20060 {
++ #clock-cells = <1>;
++ compatible = "allwinner,sun50i-a64-bus-gates-clk",
++ "allwinner,sunxi-multi-bus-gates-clk";
++ reg = <0x01c20060 0x14>;
++ ahb1_parent {
++ clocks = <&ahb1>;
++ clock-indices = <1>, <5>,
++ <6>, <8>,
++ <9>, <10>,
++ <13>, <14>,
++ <18>, <19>,
++ <20>, <21>,
++ <23>, <24>,
++ <25>, <28>,
++ <32>, <35>,
++ <36>, <37>,
++ <40>, <43>,
++ <44>, <52>,
++ <53>, <54>,
++ <135>;
++ clock-output-names = "bus_mipidsi", "bus_ce",
++ "bus_dma", "bus_mmc0",
++ "bus_mmc1", "bus_mmc2",
++ "bus_nand", "bus_sdram",
++ "bus_ts", "bus_hstimer",
++ "bus_spi0", "bus_spi1",
++ "bus_otg", "bus_otg_ehci0",
++ "bus_ehci0", "bus_otg_ohci0",
++ "bus_ve", "bus_lcd0",
++ "bus_lcd1", "bus_deint",
++ "bus_csi", "bus_hdmi",
++ "bus_de", "bus_gpu",
++ "bus_msgbox", "bus_spinlock",
++ "bus_dbg";
++ };
++ ahb2_parent {
++ clocks = <&ahb2>;
++ clock-indices = <17>, <29>;
++ clock-output-names = "bus_gmac", "bus_ohci0";
++ };
++ apb1_parent {
++ clocks = <&apb1>;
++ clock-indices = <64>, <65>,
++ <69>, <72>,
++ <76>, <77>,
++ <78>;
++ clock-output-names = "bus_codec", "bus_spdif",
++ "bus_pio", "bus_ths",
++ "bus_i2s0", "bus_i2s1",
++ "bus_i2s2";
++ };
++ abp2_parent {
++ clocks = <&apb2>;
++ clock-indices = <96>, <97>,
++ <98>, <101>,
++ <112>, <113>,
++ <114>, <115>,
++ <116>;
++ clock-output-names = "bus_i2c0", "bus_i2c1",
++ "bus_i2c2", "bus_scr",
++ "bus_uart0", "bus_uart1",
++ "bus_uart2", "bus_uart3",
++ "bus_uart4";
++ };
++ };
++
++ mmc0_clk: mmc0_clk@1c20088 {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun4i-a10-mod0-clk";
++ reg = <0x01c20088 0x4>;
++ clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
++ clock-output-names = "mmc0";
++ };
++
++ mmc1_clk: mmc1_clk@1c2008c {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun4i-a10-mod0-clk";
++ reg = <0x01c2008c 0x4>;
++ clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
++ clock-output-names = "mmc1";
++ };
++
++ mmc2_clk: mmc2_clk@1c20090 {
++ #clock-cells = <0>;
++ compatible = "allwinner,sun4i-a10-mod0-clk";
++ reg = <0x01c20090 0x4>;
++ clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
++ clock-output-names = "mmc2";
++ };
++ };
++
++ soc {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ mmc0: mmc@1c0f000 {
++ compatible = "allwinner,sun50i-a64-mmc",
++ "allwinner,sun5i-a13-mmc";
++ reg = <0x01c0f000 0x1000>;
++ clocks = <&bus_gates 8>, <&mmc0_clk>,
++ <&mmc0_clk>, <&mmc0_clk>;
++ clock-names = "ahb", "mmc",
++ "output", "sample";
++ resets = <&ahb_rst 8>;
++ reset-names = "ahb";
++ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ mmc1: mmc@1c10000 {
++ compatible = "allwinner,sun50i-a64-mmc",
++ "allwinner,sun5i-a13-mmc";
++ reg = <0x01c10000 0x1000>;
++ clocks = <&bus_gates 9>, <&mmc1_clk>,
++ <&mmc1_clk>, <&mmc1_clk>;
++ clock-names = "ahb", "mmc",
++ "output", "sample";
++ resets = <&ahb_rst 9>;
++ reset-names = "ahb";
++ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ mmc2: mmc@1c11000 {
++ compatible = "allwinner,sun50i-a64-mmc",
++ "allwinner,sun5i-a13-mmc";
++ reg = <0x01c11000 0x1000>;
++ clocks = <&bus_gates 10>, <&mmc2_clk>,
++ <&mmc2_clk>, <&mmc2_clk>;
++ clock-names = "ahb", "mmc",
++ "output", "sample";
++ resets = <&ahb_rst 10>;
++ reset-names = "ahb";
++ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pio: pinctrl@1c20800 {
++ compatible = "allwinner,sun50i-a64-pinctrl";
++ reg = <0x01c20800 0x400>;
++ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&bus_gates 69>;
++ gpio-controller;
++ #gpio-cells = <3>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++
++ uart0_pins_a: uart0@0 {
++ allwinner,pins = "PB8", "PB9";
++ allwinner,function = "uart0";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart0_pins_b: uart0@1 {
++ allwinner,pins = "PF2", "PF3";
++ allwinner,function = "uart0";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart1_2pins: uart1_2@0 {
++ allwinner,pins = "PG6", "PG7";
++ allwinner,function = "uart1";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart1_4pins: uart1_4@0 {
++ allwinner,pins = "PG6", "PG7", "PG8", "PG9";
++ allwinner,function = "uart1";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart2_2pins: uart2_2@0 {
++ allwinner,pins = "PB0", "PB1";
++ allwinner,function = "uart2";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart2_4pins: uart2_4@0 {
++ allwinner,pins = "PB0", "PB1", "PB2", "PB3";
++ allwinner,function = "uart2";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart3_pins_a: uart3@0 {
++ allwinner,pins = "PD0", "PD1";
++ allwinner,function = "uart3";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart3_2pins_b: uart3_2@1 {
++ allwinner,pins = "PH4", "PH5";
++ allwinner,function = "uart3";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart3_4pins_b: uart3_4@1 {
++ allwinner,pins = "PH4", "PH5", "PH6", "PH7";
++ allwinner,function = "uart3";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart4_2pins: uart4_2@0 {
++ allwinner,pins = "PD2", "PD3";
++ allwinner,function = "uart4";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ uart4_4pins: uart4_4@0 {
++ allwinner,pins = "PD2", "PD3", "PD4", "PD5";
++ allwinner,function = "uart4";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ mmc0_pins: mmc0@0 {
++ allwinner,pins = "PF0", "PF1", "PF2", "PF3",
++ "PF4", "PF5";
++ allwinner,function = "mmc0";
++ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ mmc0_default_cd_pin: mmc0_cd_pin@0 {
++ allwinner,pins = "PF6";
++ allwinner,function = "gpio_in";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
++ };
++
++ mmc1_pins: mmc1@0 {
++ allwinner,pins = "PG0", "PG1", "PG2", "PG3",
++ "PG4", "PG5";
++ allwinner,function = "mmc1";
++ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ mmc2_pins: mmc2@0 {
++ allwinner,pins = "PC1", "PC5", "PC6", "PC8",
++ "PC9", "PC10";
++ allwinner,function = "mmc2";
++ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ i2c0_pins: i2c0_pins {
++ allwinner,pins = "PH0", "PH1";
++ allwinner,function = "i2c0";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ i2c1_pins: i2c1_pins {
++ allwinner,pins = "PH2", "PH3";
++ allwinner,function = "i2c1";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++
++ i2c2_pins: i2c2_pins {
++ allwinner,pins = "PE14", "PE15";
++ allwinner,function = "i2c2";
++ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++ };
++ };
++
++ ahb_rst: reset@1c202c0 {
++ #reset-cells = <1>;
++ compatible = "allwinner,sun6i-a31-clock-reset";
++ reg = <0x01c202c0 0xc>;
++ };
++
++ apb1_rst: reset@1c202d0 {
++ #reset-cells = <1>;
++ compatible = "allwinner,sun6i-a31-clock-reset";
++ reg = <0x01c202d0 0x4>;
++ };
++
++ apb2_rst: reset@1c202d8 {
++ #reset-cells = <1>;
++ compatible = "allwinner,sun6i-a31-clock-reset";
++ reg = <0x01c202d8 0x4>;
++ };
++
++ uart0: serial@1c28000 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x01c28000 0x400>;
++ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&bus_gates 112>;
++ resets = <&apb2_rst 16>;
++ status = "disabled";
++ };
++
++ uart1: serial@1c28400 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x01c28400 0x400>;
++ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&bus_gates 113>;
++ resets = <&apb2_rst 17>;
++ status = "disabled";
++ };
++
++ uart2: serial@1c28800 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x01c28800 0x400>;
++ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&bus_gates 114>;
++ resets = <&apb2_rst 18>;
++ status = "disabled";
++ };
++
++ uart3: serial@1c28c00 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x01c28c00 0x400>;
++ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&bus_gates 115>;
++ resets = <&apb2_rst 19>;
++ status = "disabled";
++ };
++
++ uart4: serial@1c29000 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x01c29000 0x400>;
++ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&bus_gates 116>;
++ resets = <&apb2_rst 20>;
++ status = "disabled";
++ };
++
++ rtc: rtc@1f00000 {
++ compatible = "allwinner,sun6i-a31-rtc";
++ reg = <0x01f00000 0x54>;
++ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ i2c0: i2c@1c2ac00 {
++ compatible = "allwinner,sun6i-a31-i2c";
++ reg = <0x01c2ac00 0x400>;
++ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&bus_gates 96>;
++ resets = <&apb2_rst 0>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ i2c1: i2c@1c2b000 {
++ compatible = "allwinner,sun6i-a31-i2c";
++ reg = <0x01c2b000 0x400>;
++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&bus_gates 97>;
++ resets = <&apb2_rst 1>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ i2c2: i2c@1c2b400 {
++ compatible = "allwinner,sun6i-a31-i2c";
++ reg = <0x01c2b400 0x400>;
++ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&bus_gates 98>;
++ resets = <&apb2_rst 2>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++};
+diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
+index 3fd7901..3a9dc31 100644
+--- a/drivers/clk/sunxi/Makefile
++++ b/drivers/clk/sunxi/Makefile
+@@ -11,6 +11,7 @@ obj-y += clk-a10-ve.o
+ obj-y += clk-a20-gmac.o
+ obj-y += clk-mod0.o
+ obj-y += clk-simple-gates.o
++obj-y += clk-multi-gates.o
+ obj-y += clk-sun8i-bus-gates.o
+ obj-y += clk-sun8i-mbus.o
+ obj-y += clk-sun9i-core.o
+diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
+index 59428db..607ba53 100644
+--- a/drivers/clk/sunxi/clk-factors.c
++++ b/drivers/clk/sunxi/clk-factors.c
+@@ -184,7 +184,8 @@ struct clk *sunxi_factors_register(struct device_node *node,
+ if (data->name)
+ clk_name = data->name;
+ else
+- of_property_read_string(node, "clock-output-names", &clk_name);
++ of_property_read_string_index(node, "clock-output-names",
++ data->name_idx, &clk_name);
+
+ factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
+ if (!factors)
+diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
+index 171085a..cc89d1f 100644
+--- a/drivers/clk/sunxi/clk-factors.h
++++ b/drivers/clk/sunxi/clk-factors.h
+@@ -26,6 +26,7 @@ struct factors_data {
+ struct clk_factors_config *table;
+ void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
+ const char *name;
++ int name_idx;
+ };
+
+ struct clk_factors {
+diff --git a/drivers/clk/sunxi/clk-multi-gates.c b/drivers/clk/sunxi/clk-multi-gates.c
+new file mode 100644
+index 0000000..76e715a
+--- /dev/null
++++ b/drivers/clk/sunxi/clk-multi-gates.c
+@@ -0,0 +1,105 @@
++/*
++ * Copyright (C) 2016 ARM Ltd.
++ *
++ * Based on clk-sun8i-bus-gates.c, which is:
++ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
++ * Based on clk-simple-gates.c, which is:
++ * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++static DEFINE_SPINLOCK(gates_lock);
++
++static void __init sunxi_parse_parent(struct device_node *node,
++ struct clk_onecell_data *clk_data,
++ void __iomem *reg)
++{
++ const char *parent = of_clk_get_parent_name(node, 0);
++ const char *clk_name;
++ struct property *prop;
++ struct clk *clk;
++ const __be32 *p;
++ int index, i = 0;
++
++ of_property_for_each_u32(node, "clock-indices", prop, p, index) {
++ of_property_read_string_index(node, "clock-output-names",
++ i, &clk_name);
++
++ clk = clk_register_gate(NULL, clk_name, parent, 0,
++ reg + 4 * (index / 32), index % 32,
++ 0, &gates_lock);
++ i++;
++ if (IS_ERR(clk)) {
++ pr_warn("could not register gate clock \"%s\"\n",
++ clk_name);
++ continue;
++ }
++ if (clk_data->clks[index])
++ pr_warn("bus-gate clock %s: index #%d already registered as %s\n",
++ clk_name, index, "?");
++ else
++ clk_data->clks[index] = clk;
++ }
++}
++
++static void __init sunxi_multi_bus_gates_init(struct device_node *node)
++{
++ struct clk_onecell_data *clk_data;
++ struct device_node *child;
++ struct property *prop;
++ struct resource res;
++ void __iomem *reg;
++ const __be32 *p;
++ int number = 0;
++ int index;
++
++ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
++ if (IS_ERR(reg))
++ return;
++
++ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
++ if (!clk_data)
++ goto err_unmap;
++
++ for_each_child_of_node(node, child)
++ of_property_for_each_u32(child, "clock-indices", prop, p, index)
++ number = max(number, index);
++
++ clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
++ if (!clk_data->clks)
++ goto err_free_data;
++
++ for_each_child_of_node(node, child)
++ sunxi_parse_parent(child, clk_data, reg);
++
++ clk_data->clk_num = number + 1;
++ if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data))
++ pr_err("registering bus-gate clock %s failed\n", node->name);
++
++ return;
++
++err_free_data:
++ kfree(clk_data);
++err_unmap:
++ iounmap(reg);
++ of_address_to_resource(node, 0, &res);
++ release_mem_region(res.start, resource_size(&res));
++}
++
++CLK_OF_DECLARE(sunxi_multi_bus_gates, "allwinner,sunxi-multi-bus-gates-clk",
++ sunxi_multi_bus_gates_init);
+diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
+index 5ba2188..ca59458 100644
+--- a/drivers/clk/sunxi/clk-sunxi.c
++++ b/drivers/clk/sunxi/clk-sunxi.c
+@@ -711,14 +711,14 @@ static const struct factors_data sun4i_pll6_data __initconst = {
+ .enable = 31,
+ .table = &sun4i_pll5_config,
+ .getter = sun4i_get_pll5_factors,
+- .name = "pll6",
++ .name_idx = 2,
+ };
+
+ static const struct factors_data sun6i_a31_pll6_data __initconst = {
+ .enable = 31,
+ .table = &sun6i_a31_pll6_config,
+ .getter = sun6i_a31_get_pll6_factors,
+- .name = "pll6x2",
++ .name_idx = 1,
+ };
+
+ static const struct factors_data sun5i_a13_ahb_data __initconst = {
+diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
+index 07d4942..737200f 100644
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -487,7 +487,7 @@ config CRYPTO_DEV_IMGTEC_HASH
+
+ config CRYPTO_DEV_SUN4I_SS
+ tristate "Support for Allwinner Security System cryptographic accelerator"
+- depends on ARCH_SUNXI
++ depends on ARCH_SUNXI && !64BIT
+ select CRYPTO_MD5
+ select CRYPTO_SHA1
+ select CRYPTO_AES
+diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
+index f8dbc8b..c1f970f 100644
+--- a/drivers/pinctrl/sunxi/Kconfig
++++ b/drivers/pinctrl/sunxi/Kconfig
+@@ -64,4 +64,8 @@ config PINCTRL_SUN9I_A80_R
+ depends on RESET_CONTROLLER
+ select PINCTRL_SUNXI_COMMON
+
++config PINCTRL_SUN50I_A64
++ bool
++ select PINCTRL_SUNXI_COMMON
++
+ endif
+diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
+index ef82f22..0ca7681 100644
+--- a/drivers/pinctrl/sunxi/Makefile
++++ b/drivers/pinctrl/sunxi/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
+ obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
+ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
+ obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
++obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
+ obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
+ obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
+ obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
+new file mode 100644
+index 0000000..a53cc23
+--- /dev/null
++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
+@@ -0,0 +1,602 @@
++/*
++ * Allwinner A64 SoCs pinctrl driver.
++ *
++ * Copyright (C) 2016 - ARM Ltd.
++ * Author: Andre Przywara <andre.przywara@arm.com>
++ *
++ * Based on pinctrl-sun7i-a20.c, which is:
++ * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/pinctrl.h>
++
++#include "pinctrl-sunxi.h"
++
++static const struct sunxi_desc_pin a64_pins[] = {
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
++ SUNXI_FUNCTION(0x4, "jtag"), /* MS0 */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* EINT0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
++ SUNXI_FUNCTION(0x4, "jtag"), /* CK0 */
++ SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* EINT1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
++ SUNXI_FUNCTION(0x4, "jtag"), /* DO0 */
++ SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* EINT2 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
++ SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
++ SUNXI_FUNCTION(0x4, "jtag"), /* DI0 */
++ SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* EINT3 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "aif2"), /* SYNC */
++ SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
++ SUNXI_FUNCTION(0x5, "sim"), /* CLK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* EINT4 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "aif2"), /* BCLK */
++ SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
++ SUNXI_FUNCTION(0x5, "sim"), /* DATA */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* EINT5 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "aif2"), /* DOUT */
++ SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
++ SUNXI_FUNCTION(0x5, "sim"), /* RST */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* EINT6 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "aif2"), /* DIN */
++ SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
++ SUNXI_FUNCTION(0x5, "sim"), /* DET */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* EINT7 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x4, "uart0"), /* TX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* EINT8 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x4, "uart0"), /* RX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* EINT9 */
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
++ SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
++ SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
++ SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
++ SUNXI_FUNCTION(0x4, "spi0")), /* SCK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
++ SUNXI_FUNCTION(0x4, "spi0")), /* CS */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0")), /* NRB1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
++ SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
++ SUNXI_FUNCTION(0x3, "uart3"), /* TX */
++ SUNXI_FUNCTION(0x4, "spi1"), /* CS */
++ SUNXI_FUNCTION(0x5, "ccir")), /* CLK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
++ SUNXI_FUNCTION(0x3, "uart3"), /* RX */
++ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
++ SUNXI_FUNCTION(0x5, "ccir")), /* DE */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
++ SUNXI_FUNCTION(0x3, "uart4"), /* TX */
++ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
++ SUNXI_FUNCTION(0x5, "ccir")), /* HSYNC */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
++ SUNXI_FUNCTION(0x3, "uart4"), /* RX */
++ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
++ SUNXI_FUNCTION(0x5, "ccir")), /* VSYNC */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
++ SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
++ SUNXI_FUNCTION(0x5, "ccir")), /* D0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
++ SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
++ SUNXI_FUNCTION(0x5, "ccir")), /* D1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
++ SUNXI_FUNCTION(0x5, "ccir")), /* D2 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
++ SUNXI_FUNCTION(0x5, "ccir")), /* D3 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
++ SUNXI_FUNCTION(0x4, "emac"), /* ERXD3 */
++ SUNXI_FUNCTION(0x5, "ccir")), /* D4 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
++ SUNXI_FUNCTION(0x4, "emac"), /* ERXD2 */
++ SUNXI_FUNCTION(0x5, "ccir")), /* D5 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
++ SUNXI_FUNCTION(0x4, "emac")), /* ERXD1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
++ SUNXI_FUNCTION(0x4, "emac")), /* ERXD0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
++ SUNXI_FUNCTION(0x4, "emac")), /* ERXCK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
++ SUNXI_FUNCTION(0x4, "emac")), /* ERXCTL */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
++ SUNXI_FUNCTION(0x4, "emac")), /* ENULL */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
++ SUNXI_FUNCTION(0x4, "emac"), /* ETXD3 */
++ SUNXI_FUNCTION(0x5, "ccir")), /* D6 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
++ SUNXI_FUNCTION(0x4, "emac"), /* ETXD2 */
++ SUNXI_FUNCTION(0x5, "ccir")), /* D7 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
++ SUNXI_FUNCTION(0x4, "emac")), /* ETXD1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */
++ SUNXI_FUNCTION(0x4, "emac")), /* ETXD0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */
++ SUNXI_FUNCTION(0x4, "emac")), /* ETXCK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */
++ SUNXI_FUNCTION(0x4, "emac")), /* ETXCTL */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
++ SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */
++ SUNXI_FUNCTION(0x4, "emac")), /* ECLKIN */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
++ SUNXI_FUNCTION(0x4, "emac")), /* EMDC */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x4, "emac")), /* EMDIO */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out")),
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* PCK */
++ SUNXI_FUNCTION(0x4, "ts0")), /* CLK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* CK */
++ SUNXI_FUNCTION(0x4, "ts0")), /* ERR */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* HSYNC */
++ SUNXI_FUNCTION(0x4, "ts0")), /* SYNC */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* VSYNC */
++ SUNXI_FUNCTION(0x4, "ts0")), /* DVLD */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* D0 */
++ SUNXI_FUNCTION(0x4, "ts0")), /* D0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* D1 */
++ SUNXI_FUNCTION(0x4, "ts0")), /* D1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* D2 */
++ SUNXI_FUNCTION(0x4, "ts0")), /* D2 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* D3 */
++ SUNXI_FUNCTION(0x4, "ts0")), /* D3 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* D4 */
++ SUNXI_FUNCTION(0x4, "ts0")), /* D4 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* D5 */
++ SUNXI_FUNCTION(0x4, "ts0")), /* D5 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* D6 */
++ SUNXI_FUNCTION(0x4, "ts0")), /* D6 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0"), /* D7 */
++ SUNXI_FUNCTION(0x4, "ts0")), /* D7 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0")), /* SCK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi0")), /* SDA */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "pll"), /* LOCK_DBG */
++ SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out")),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out")),
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
++ SUNXI_FUNCTION(0x3, "jtag")), /* MSI */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
++ SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
++ SUNXI_FUNCTION(0x3, "uart0")), /* TX */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
++ SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
++ SUNXI_FUNCTION(0x4, "uart0")), /* RX */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
++ SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out")),
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* EINT0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* EINT1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* EINT2 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* EINT3 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* EINT4 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* EINT5 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart1"), /* TX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* EINT6 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart1"), /* RX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* EINT7 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* EINT8 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* EINT9 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "aif3"), /* SYNC */
++ SUNXI_FUNCTION(0x3, "i2s1"), /* SYNC */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* EINT10 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "aif3"), /* BCLK */
++ SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* EINT11 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "aif3"), /* DOUT */
++ SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* EINT12 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "aif3"), /* DIN */
++ SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* EINT13 */
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* EINT0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* EINT1 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* EINT2 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* EINT3 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart3"), /* TX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* EINT4 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart3"), /* RX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* EINT5 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* EINT6 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* EINT7 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* EINT8 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* EINT9 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mic"), /* CLK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* EINT10 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mic"), /* DATA */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* EINT11 */
++};
++
++static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
++ .pins = a64_pins,
++ .npins = ARRAY_SIZE(a64_pins),
++ .irq_banks = 3,
++};
++
++static int a64_pinctrl_probe(struct platform_device *pdev)
++{
++ return sunxi_pinctrl_init(pdev,
++ &a64_pinctrl_data);
++}
++
++static const struct of_device_id a64_pinctrl_match[] = {
++ { .compatible = "allwinner,sun50i-a64-pinctrl", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, a64_pinctrl_match);
++
++static struct platform_driver a64_pinctrl_driver = {
++ .probe = a64_pinctrl_probe,
++ .driver = {
++ .name = "sun50i-a64-pinctrl",
++ .of_match_table = a64_pinctrl_match,
++ },
++};
++builtin_platform_driver(a64_pinctrl_driver);
+diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
+index 376322f..526eaf4 100644
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -1360,10 +1360,11 @@ config RTC_DRV_SUN4V
+
+ config RTC_DRV_SUN6I
+ tristate "Allwinner A31 RTC"
+- depends on MACH_SUN6I || MACH_SUN8I
++ default MACH_SUN6I || MACH_SUN8I
++ depends on ARCH_SUNXI
+ help
+- If you say Y here you will get support for the RTC found on
+- Allwinner A31.
++ If you say Y here you will get support for the RTC found in
++ some Allwinner SoCs like the A31 or the A64.
+
+ config RTC_DRV_SUNXI
+ tristate "Allwinner sun4i/sun7i RTC"
+--
+2.5.0
+
diff --git a/config-arm-generic b/config-arm-generic
index 987695636..8215a36a8 100644
--- a/config-arm-generic
+++ b/config-arm-generic
@@ -79,6 +79,11 @@ CONFIG_CRYPTO_SHA1_ARM_NEON=y
CONFIG_CRYPTO_SHA512_ARM_NEON=y
CONFIG_CRYPTO_SHA512_ARM=y
+# EDAC
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=m
+CONFIG_EDAC_LEGACY_SYSFS=y
+
# ARM VExpress
CONFIG_ARCH_VEXPRESS=y
CONFIG_MFD_VEXPRESS_SYSREG=y
@@ -128,8 +133,41 @@ CONFIG_CRYPTO_DEV_ROCKCHIP=m
CONFIG_ROCKCHIP_EFUSE=m
# Tegra
-# CONFIG_TEGRA_AHB is not set
-#
+CONFIG_ARM_TEGRA_CPUFREQ=y
+CONFIG_TEGRA_MC=y
+CONFIG_TEGRA124_EMC=y
+CONFIG_TEGRA_IOMMU_SMMU=y
+CONFIG_TEGRA_AHB=y
+CONFIG_TEGRA20_APB_DMA=y
+CONFIG_TRUSTED_FOUNDATIONS=y
+CONFIG_SERIAL_TEGRA=y
+CONFIG_PCI_TEGRA=y
+CONFIG_AHCI_TEGRA=m
+CONFIG_MMC_SDHCI_TEGRA=m
+CONFIG_TEGRA_WATCHDOG=m
+CONFIG_I2C_TEGRA=m
+CONFIG_SPI_TEGRA114=m
+CONFIG_PWM_TEGRA=m
+CONFIG_KEYBOARD_TEGRA=m
+CONFIG_USB_EHCI_TEGRA=m
+CONFIG_RTC_DRV_TEGRA=m
+CONFIG_ARM_TEGRA_DEVFREQ=m
+CONFIG_ARM_TEGRA124_CPUFREQ=m
+CONFIG_TEGRA_SOCTHERM=m
+
+CONFIG_TEGRA_HOST1X=m
+CONFIG_TEGRA_HOST1X_FIREWALL=y
+CONFIG_DRM_TEGRA=m
+CONFIG_DRM_TEGRA_FBDEV=y
+# CONFIG_DRM_TEGRA_DEBUG is not set
+CONFIG_DRM_TEGRA_STAGING=y
+CONFIG_NOUVEAU_PLATFORM_DRIVER=y
+CONFIG_SND_HDA_TEGRA=m
+
+# CONFIG_ARM_TEGRA20_CPUFREQ is not set
+# CONFIG_MFD_NVEC is not set
+# CONFIG_TEGRA20_APB_DMA is not set
+
# Virt
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_TIME_ACCOUNTING=y
@@ -248,6 +286,18 @@ CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_MMC_SPI=m
CONFIG_MMC_SDHCI_OF_ARASAN=m
+# LCD Panels
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_LD9040=m
+CONFIG_DRM_PANEL_LG_LG4573=m
+CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
+CONFIG_DRM_PANEL_S6E8AA0=m
+CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
+CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
+CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
+
# Designware (used by numerous devices)
CONFIG_MMC_DW=m
CONFIG_MMC_DW_PLTFM=m
@@ -367,11 +417,6 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
-# EDAC
-CONFIG_EDAC=y
-CONFIG_EDAC_MM_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-
# VFIO
CONFIG_VFIO_PLATFORM=m
CONFIG_VFIO_AMBA=m
diff --git a/config-arm64 b/config-arm64
index 1ef481a75..773a35ee5 100644
--- a/config-arm64
+++ b/config-arm64
@@ -9,6 +9,8 @@ CONFIG_SCHED_SMT=y
# arm64 only SoCs
CONFIG_ARCH_HISI=y
CONFIG_ARCH_SEATTLE=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_XGENE=y
# CONFIG_ARCH_BCM_IPROC is not set
# CONFIG_ARCH_BERLIN is not set
@@ -20,7 +22,6 @@ CONFIG_ARCH_XGENE=y
# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_STRATIX10 is not set
-# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_ZYNQMP is not set
# CONFIG_ARCH_UNIPHIER is not set
@@ -142,6 +143,31 @@ CONFIG_STUB_CLK_HI6220=y
CONFIG_PHY_HI6220_USB=m
CONFIG_COMMON_RESET_HI6220=m
+# Tegra
+CONFIG_ARCH_TEGRA_132_SOC=y
+CONFIG_ARCH_TEGRA_210_SOC=y
+
+# AllWinner
+CONFIG_MACH_SUN50I=y
+CONFIG_SUNXI_RSB=m
+CONFIG_AHCI_SUNXI=m
+CONFIG_NET_VENDOR_ALLWINNER=y
+# CONFIG_SUN4I_EMAC is not set
+# CONFIG_MDIO_SUN4I is not set
+# CONFIG_KEYBOARD_SUN4I_LRADC is not set
+# CONFIG_TOUCHSCREEN_SUN4I is not set
+# CONFIG_SERIO_SUN4I_PS2 is not set
+CONFIG_I2C_MV64XXX=m
+CONFIG_SUNXI_WATCHDOG=m
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_IR_SUNXI=m
+CONFIG_MMC_SUNXI=m
+CONFIG_RTC_DRV_SUN6I=m
+CONFIG_PWM_SUN4I=m
+# CONFIG_PHY_SUN4I_USB is not set
+# CONFIG_PHY_SUN9I_USB is not set
+CONFIG_NVMEM_SUNXI_SID=m
+
# ThunderX
# CONFIG_MDIO_OCTEON is not set
diff --git a/config-armv7 b/config-armv7
index bf1742e09..0cce9bc04 100644
--- a/config-armv7
+++ b/config-armv7
@@ -3,6 +3,7 @@
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_KEYSTONE is not set
CONFIG_ARCH_MXC=y
+CONFIG_ARCH_MMP=y
CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y
CONFIG_ARCH_QCOM=y
@@ -510,6 +511,24 @@ CONFIG_REGULATOR_DA9055=m
# picoxcell
# CONFIG_CRYPTO_DEV_PICOXCELL is not set
+# MMP XO 1.75
+# CONFIG_MACH_BROWNSTONE is not set
+# CONFIG_MACH_FLINT is not set
+# CONFIG_MACH_MARVELL_JASPER is not set
+CONFIG_MACH_MMP2_DT=y
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_KEYBOARD_PXA27x=y
+CONFIG_I2C_PXA=m
+# CONFIG_I2C_PXA_SLAVE is not set
+CONFIG_SND_MMP_SOC=y
+CONFIG_SND_PXA910_SOC=m
+CONFIG_MMC_SDHCI_PXAV2=m
+CONFIG_MMP_PDMA=y
+CONFIG_MMP_TDMA=y
+CONFIG_PXA_DMA=y
+CONFIG_SERIO_OLPC_APSP=m
+
# Exynos 4
CONFIG_ARCH_EXYNOS4=y
CONFIG_SOC_EXYNOS4212=y
@@ -591,9 +610,6 @@ CONFIG_MFD_TPS6586X=y
CONFIG_GPIO_TPS6586X=y
CONFIG_RTC_DRV_TPS6586X=m
-# OLPC XO
-CONFIG_SERIO_OLPC_APSP=m
-
# Zynq-7xxx
CONFIG_SERIAL_UARTLITE=y
CONFIG_SERIAL_UARTLITE_CONSOLE=y
@@ -626,9 +642,9 @@ CONFIG_USB_GADGET_XILINX=m
CONFIG_PCIE_XILINX=y
CONFIG_CADENCE_WATCHDOG=m
CONFIG_REGULATOR_ISL9305=m
-CONFIG_EDAC_SYNOPSYS=m
CONFIG_PINCTRL_ZYNQ=y
CONFIG_AXI_DMAC=m
+CONFIG_EDAC_SYNOPSYS=m
# Multi function devices
CONFIG_MFD_88PM800=m
diff --git a/config-armv7-generic b/config-armv7-generic
index d845e63c0..e4322ac8e 100644
--- a/config-armv7-generic
+++ b/config-armv7-generic
@@ -49,6 +49,7 @@ CONFIG_CPU_SW_DOMAIN_PAN=y
# CONFIG_ARM_VIRT_EXT is not set
# Platforms enabled/disabled globally on ARMv7
+CONFIG_ARCH_BCM2835=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_SUNXI=y
@@ -170,8 +171,6 @@ CONFIG_RTC_DRV_PL030=y
CONFIG_AMBA_PL08X=y
CONFIG_SND_ARMAACI=m
-CONFIG_EDAC=y
-
# highbank
CONFIG_EDAC_HIGHBANK_MC=m
CONFIG_EDAC_HIGHBANK_L2=m
@@ -188,6 +187,7 @@ CONFIG_MACH_SUN6I=y
CONFIG_MACH_SUN7I=y
CONFIG_MACH_SUN8I=y
# CONFIG_MACH_SUN9I is not set
+# CONFIG_MACH_SUN50I is not set
CONFIG_SUNXI_SRAM=y
CONFIG_DMA_SUN4I=m
CONFIG_DMA_SUN6I=m
@@ -229,6 +229,22 @@ CONFIG_SND_SUN4I_CODEC=m
CONFIG_SUNXI_RSB=m
CONFIG_NVMEM_SUNXI_SID=m
+# BCM 283x
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_DMA_BCM2835=m
+CONFIG_MMC_SDHCI_BCM2835=m
+CONFIG_BCM2835_MBOX=m
+CONFIG_PWM_BCM2835=m
+CONFIG_HW_RANDOM_BCM2835=m
+CONFIG_I2C_BCM2835=m
+CONFIG_SPI_BCM2835=m
+CONFIG_SPI_BCM2835AUX=m
+CONFIG_BCM2835_WDT=m
+CONFIG_SND_BCM2835_SOC_I2S=m
+CONFIG_DRM_VC4=m
+CONFIG_RASPBERRYPI_FIRMWARE=m
+
# Exynos
CONFIG_ARCH_EXYNOS3=y
# CONFIG_ARCH_EXYNOS4 is not set
@@ -344,52 +360,15 @@ CONFIG_EXTCON_MAX8997=m
# Tegra
CONFIG_ARCH_TEGRA_114_SOC=y
CONFIG_ARCH_TEGRA_124_SOC=y
-CONFIG_ARM_TEGRA_CPUFREQ=y
-CONFIG_TRUSTED_FOUNDATIONS=y
-CONFIG_SERIAL_TEGRA=y
-CONFIG_PCI_TEGRA=y
-CONFIG_AHCI_TEGRA=m
-CONFIG_TEGRA_IOMMU_SMMU=y
-CONFIG_MMC_SDHCI_TEGRA=m
-CONFIG_TEGRA_WATCHDOG=m
-CONFIG_I2C_TEGRA=m
-CONFIG_TEGRA_AHB=y
-CONFIG_TEGRA20_APB_DMA=y
-CONFIG_SPI_TEGRA114=m
-CONFIG_PWM_TEGRA=m
-CONFIG_KEYBOARD_TEGRA=m
-CONFIG_USB_EHCI_TEGRA=m
-CONFIG_RTC_DRV_TEGRA=m
CONFIG_SND_SOC_TEGRA=m
-CONFIG_SND_SOC_TEGRA_MAX98090=m
-CONFIG_SND_SOC_TEGRA_RT5640=m
CONFIG_SND_SOC_TEGRA30_AHUB=m
CONFIG_SND_SOC_TEGRA30_I2S=m
+CONFIG_SND_SOC_TEGRA_MAX98090=m
+CONFIG_SND_SOC_TEGRA_RT5640=m
CONFIG_SND_SOC_TEGRA_RT5677=m
-CONFIG_SND_HDA_TEGRA=m
-CONFIG_TEGRA_HOST1X=m
-CONFIG_TEGRA_HOST1X_FIREWALL=y
-CONFIG_DRM_TEGRA=m
-CONFIG_DRM_TEGRA_FBDEV=y
-# CONFIG_DRM_TEGRA_DEBUG is not set
-CONFIG_DRM_TEGRA_STAGING=y
-CONFIG_NOUVEAU_PLATFORM_DRIVER=y
CONFIG_AD525X_DPOT=m
CONFIG_AD525X_DPOT_I2C=m
CONFIG_AD525X_DPOT_SPI=m
-CONFIG_TEGRA_SOCTHERM=m
-CONFIG_TEGRA_MC=y
-CONFIG_TEGRA124_EMC=y
-CONFIG_ARM_TEGRA_DEVFREQ=m
-# CONFIG_ARM_TEGRA20_CPUFREQ is not set
-CONFIG_ARM_TEGRA124_CPUFREQ=m
-
-# Jetson TK1
-CONFIG_PINCTRL_AS3722=y
-CONFIG_POWER_RESET_AS3722=y
-CONFIG_MFD_AS3722=y
-CONFIG_REGULATOR_AS3722=m
-CONFIG_RTC_DRV_AS3722=y
# TI Generic
CONFIG_TI_SOC_THERMAL=m
@@ -853,18 +832,18 @@ CONFIG_R8188EU=m
# CONFIG_SND_SOC_APQ8016_SBC is not set
# CONFIG_SND_SOC_TAS571X is not set
+# CONFIG_VFIO_PLATFORM_AMDXGBE_RESET is not set
+
+# Altera?
+# CONFIG_PCIE_ALTERA is not set
+
# Debug options. We need to deal with them at some point like x86
# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_LL is not set
-# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_DMADEVICES_VDEBUG is not set
# CONFIG_DMADEVICES_DEBUG is not set
+# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
# CONFIG_OMAP2_DSS_DEBUG is not set
# CONFIG_CRYPTO_DEV_UX500_DEBUG is not set
# CONFIG_AB8500_DEBUG is not set
# CONFIG_ARM_KERNMEM_PERMS is not set
-
-# CONFIG_VFIO_PLATFORM_AMDXGBE_RESET is not set
-
-# Altera?
-# CONFIG_PCIE_ALTERA is not set
+# CONFIG_DEBUG_LL is not set
diff --git a/kernel.spec b/kernel.spec
index 4c5c5aa37..6783bb396 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -506,6 +506,17 @@ Patch456: arm64-acpi-drop-expert-patch.patch
# http://patchwork.ozlabs.org/patch/587554/
Patch457: ARM-tegra-usb-no-reset.patch
+Patch458: ARM-mvebu-change-order-of-ethernet-DT-nodes-on-Armada-38x.patch
+
+# http://www.spinics.net/lists/arm-kernel/msg480703.html
+Patch459: Geekbox-device-tree-support.patch
+
+# http://www.spinics.net/lists/arm-kernel/msg483898.html
+Patch460: Initial-AllWinner-A64-and-PINE64-support.patch
+
+# http://www.spinics.net/lists/linux-tegra/msg25152.html
+Patch461: Fix-tegra-to-use-stdout-path-for-serial-console.patch
+
Patch463: arm-i.MX6-Utilite-device-dtb.patch
Patch466: input-kill-stupid-messages.patch
@@ -2127,6 +2138,12 @@ fi
#
#
%changelog
+* Sat Mar 5 2016 Peter Robinson <pbrobinson@fedoraproject.org>
+- Updates and new SoCs for aarch64 and ARMv7
+- Add aarch64 support for PINE64 and Geekbox devices
+- Fix ethernet naming on Armada 38x devices
+- Serial console fixes for Tegra
+
* Fri Mar 04 2016 Justin M. Forbes <jforbes@fedoraproject.org> - 4.5.0-0.rc6.git3.1
- Linux v4.5-rc6-41-ge3c2ef4