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-rw-r--r--arm64-96boards-Rock960-CE-board-support.patch1798
-rw-r--r--arm64-ZynqMP-firmware-clock-drivers-core.patch5481
-rw-r--r--arm64-rockchip-add-initial-Rockpro64.patch862
-rw-r--r--configs/fedora/generic/CONFIG_ADXL372_I2C1
-rw-r--r--configs/fedora/generic/CONFIG_ADXL372_SPI1
-rw-r--r--configs/fedora/generic/CONFIG_LTC16601
-rw-r--r--configs/fedora/generic/CONFIG_MCP39111
-rw-r--r--configs/fedora/generic/CONFIG_VL53L0X_I2C1
-rw-r--r--configs/fedora/generic/arm/CONFIG_MESON_CANVAS1
-rw-r--r--configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_ADSP1
-rw-r--r--configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_MSS1
-rw-r--r--configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_PAS1
-rw-r--r--configs/fedora/generic/arm/CONFIG_QCOM_SPMI_ADC51
-rw-r--r--configs/fedora/generic/arm/CONFIG_RESET_QCOM_PDC1
-rw-r--r--configs/fedora/generic/arm/CONFIG_VIDEO_IMX_PXP1
-rw-r--r--configs/fedora/generic/arm/armv7/CONFIG_IMX_SCU1
-rw-r--r--gitrev2
-rw-r--r--kernel-aarch64-debug.config12
-rw-r--r--kernel-aarch64.config12
-rw-r--r--kernel-armv7hl-debug.config13
-rw-r--r--kernel-armv7hl-lpae-debug.config13
-rw-r--r--kernel-armv7hl-lpae.config13
-rw-r--r--kernel-armv7hl.config13
-rw-r--r--kernel-i686-debug.config5
-rw-r--r--kernel-i686.config5
-rw-r--r--kernel-ppc64le-debug.config5
-rw-r--r--kernel-ppc64le.config5
-rw-r--r--kernel-s390x-debug.config5
-rw-r--r--kernel-s390x.config5
-rw-r--r--kernel-x86_64-debug.config5
-rw-r--r--kernel-x86_64.config5
-rw-r--r--kernel.spec11
-rw-r--r--sources2
33 files changed, 135 insertions, 8150 deletions
diff --git a/arm64-96boards-Rock960-CE-board-support.patch b/arm64-96boards-Rock960-CE-board-support.patch
deleted file mode 100644
index 1d08debaa..000000000
--- a/arm64-96boards-Rock960-CE-board-support.patch
+++ /dev/null
@@ -1,1798 +0,0 @@
-From patchwork Mon Sep 10 15:13:53 2018
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-From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-To: heiko@sntech.de,
- robh+dt@kernel.org
-Subject: [PATCH 1/4] arm64: dts: rockchip: Split out common nodes for Rock960
- based boards
-Date: Mon, 10 Sep 2018 20:43:53 +0530
-Message-Id: <20180910151356.25946-2-manivannan.sadhasivam@linaro.org>
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-
-Since the same family members of Rock960 boards (Rock960 and Ficus)
-share the same configuration, split out the common nodes into a common
-dtsi file for reducing code duplication. The board specific nodes for
-Ficus boards are then placed in corresponding board DTS file.
-
-Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
----
- arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 429 +----------------
- .../boot/dts/rockchip/rk3399-rock960.dtsi | 439 ++++++++++++++++++
- 2 files changed, 440 insertions(+), 428 deletions(-)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
-index 8978d924eb83..7f6ec37d5a69 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
-@@ -7,8 +7,7 @@
- */
-
- /dts-v1/;
--#include "rk3399.dtsi"
--#include "rk3399-opp.dtsi"
-+#include "rk3399-rock960.dtsi"
-
- / {
- model = "96boards RK3399 Ficus";
-@@ -25,31 +24,6 @@
- #clock-cells = <0>;
- };
-
-- vcc1v8_s0: vcc1v8-s0 {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc1v8_s0";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- regulator-always-on;
-- };
--
-- vcc_sys: vcc-sys {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc_sys";
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- regulator-always-on;
-- };
--
-- vcc3v3_sys: vcc3v3-sys {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc3v3_sys";
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- regulator-always-on;
-- vin-supply = <&vcc_sys>;
-- };
--
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
-@@ -75,46 +49,6 @@
- regulator-always-on;
- vin-supply = <&vcc_sys>;
- };
--
-- vdd_log: vdd-log {
-- compatible = "pwm-regulator";
-- pwms = <&pwm2 0 25000 0>;
-- regulator-name = "vdd_log";
-- regulator-min-microvolt = <800000>;
-- regulator-max-microvolt = <1400000>;
-- regulator-always-on;
-- regulator-boot-on;
-- vin-supply = <&vcc_sys>;
-- };
--
--};
--
--&cpu_l0 {
-- cpu-supply = <&vdd_cpu_l>;
--};
--
--&cpu_l1 {
-- cpu-supply = <&vdd_cpu_l>;
--};
--
--&cpu_l2 {
-- cpu-supply = <&vdd_cpu_l>;
--};
--
--&cpu_l3 {
-- cpu-supply = <&vdd_cpu_l>;
--};
--
--&cpu_b0 {
-- cpu-supply = <&vdd_cpu_b>;
--};
--
--&cpu_b1 {
-- cpu-supply = <&vdd_cpu_b>;
--};
--
--&emmc_phy {
-- status = "okay";
- };
-
- &gmac {
-@@ -133,263 +67,6 @@
- status = "okay";
- };
-
--&hdmi {
-- ddc-i2c-bus = <&i2c3>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&hdmi_cec>;
-- status = "okay";
--};
--
--&i2c0 {
-- clock-frequency = <400000>;
-- i2c-scl-rising-time-ns = <168>;
-- i2c-scl-falling-time-ns = <4>;
-- status = "okay";
--
-- vdd_cpu_b: regulator@40 {
-- compatible = "silergy,syr827";
-- reg = <0x40>;
-- fcs,suspend-voltage-selector = <1>;
-- regulator-name = "vdd_cpu_b";
-- regulator-min-microvolt = <712500>;
-- regulator-max-microvolt = <1500000>;
-- regulator-ramp-delay = <1000>;
-- regulator-always-on;
-- regulator-boot-on;
-- vin-supply = <&vcc_sys>;
-- status = "okay";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_gpu: regulator@41 {
-- compatible = "silergy,syr828";
-- reg = <0x41>;
-- fcs,suspend-voltage-selector = <1>;
-- regulator-name = "vdd_gpu";
-- regulator-min-microvolt = <712500>;
-- regulator-max-microvolt = <1500000>;
-- regulator-ramp-delay = <1000>;
-- regulator-always-on;
-- regulator-boot-on;
-- vin-supply = <&vcc_sys>;
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- rk808: pmic@1b {
-- compatible = "rockchip,rk808";
-- reg = <0x1b>;
-- interrupt-parent = <&gpio1>;
-- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pmic_int_l>;
-- rockchip,system-power-controller;
-- wakeup-source;
-- #clock-cells = <1>;
-- clock-output-names = "xin32k", "rk808-clkout2";
--
-- vcc1-supply = <&vcc_sys>;
-- vcc2-supply = <&vcc_sys>;
-- vcc3-supply = <&vcc_sys>;
-- vcc4-supply = <&vcc_sys>;
-- vcc6-supply = <&vcc_sys>;
-- vcc7-supply = <&vcc_sys>;
-- vcc8-supply = <&vcc3v3_sys>;
-- vcc9-supply = <&vcc_sys>;
-- vcc10-supply = <&vcc_sys>;
-- vcc11-supply = <&vcc_sys>;
-- vcc12-supply = <&vcc3v3_sys>;
-- vddio-supply = <&vcc_1v8>;
--
-- regulators {
-- vdd_center: DCDC_REG1 {
-- regulator-name = "vdd_center";
-- regulator-min-microvolt = <750000>;
-- regulator-max-microvolt = <1350000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_cpu_l: DCDC_REG2 {
-- regulator-name = "vdd_cpu_l";
-- regulator-min-microvolt = <750000>;
-- regulator-max-microvolt = <1350000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_ddr: DCDC_REG3 {
-- regulator-name = "vcc_ddr";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- };
-- };
--
-- vcc_1v8: DCDC_REG4 {
-- regulator-name = "vcc_1v8";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <1800000>;
-- };
-- };
--
-- vcc1v8_dvp: LDO_REG1 {
-- regulator-name = "vcc1v8_dvp";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <1800000>;
-- };
-- };
--
-- vcca1v8_hdmi: LDO_REG2 {
-- regulator-name = "vcca1v8_hdmi";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <1800000>;
-- };
-- };
--
-- vcca_1v8: LDO_REG3 {
-- regulator-name = "vcca_1v8";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <1800000>;
-- };
-- };
--
-- vcc_sd: LDO_REG4 {
-- regulator-name = "vcc_sd";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <3300000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <3300000>;
-- };
-- };
--
-- vcc3v0_sd: LDO_REG5 {
-- regulator-name = "vcc3v0_sd";
-- regulator-min-microvolt = <3000000>;
-- regulator-max-microvolt = <3000000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <3000000>;
-- };
-- };
--
-- vcc_1v5: LDO_REG6 {
-- regulator-name = "vcc_1v5";
-- regulator-min-microvolt = <1500000>;
-- regulator-max-microvolt = <1500000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <1500000>;
-- };
-- };
--
-- vcca0v9_hdmi: LDO_REG7 {
-- regulator-name = "vcca0v9_hdmi";
-- regulator-min-microvolt = <900000>;
-- regulator-max-microvolt = <900000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <900000>;
-- };
-- };
--
-- vcc_3v0: LDO_REG8 {
-- regulator-name = "vcc_3v0";
-- regulator-min-microvolt = <3000000>;
-- regulator-max-microvolt = <3000000>;
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <3000000>;
-- };
-- };
--
-- vcc3v3_s3: SWITCH_REG1 {
-- regulator-name = "vcc3v3_s3";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- };
-- };
--
-- vcc3v3_s0: SWITCH_REG2 {
-- regulator-name = "vcc3v3_s0";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- };
-- };
-- };
-- };
--};
--
--&i2c1 {
-- status = "okay";
--};
--
--&i2c2 {
-- status = "okay";
--};
--
--&i2c3 {
-- status = "okay";
--};
--
--&i2c4 {
-- status = "okay";
--};
--
--&io_domains {
-- bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
-- audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
-- sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
-- gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
-- status = "okay";
--};
--
- &pcie_phy {
- status = "okay";
- };
-@@ -403,11 +80,6 @@
- status = "okay";
- };
-
--&pmu_io_domains {
-- pmu1830-supply = <&vcc_1v8>;
-- status = "okay";
--};
--
- &pinctrl {
- gmac {
- rgmii_sleep_pins: rgmii-sleep-pins {
-@@ -416,31 +88,6 @@
- };
- };
-
-- sdmmc {
-- sdmmc_bus1: sdmmc-bus1 {
-- rockchip,pins =
-- <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
-- };
--
-- sdmmc_bus4: sdmmc-bus4 {
-- rockchip,pins =
-- <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
-- <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
-- <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
-- <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
-- };
--
-- sdmmc_clk: sdmmc-clk {
-- rockchip,pins =
-- <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
-- };
--
-- sdmmc_cmd: sdmmc-cmd {
-- rockchip,pins =
-- <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
-- };
-- };
--
- pcie {
- pcie_drv: pcie-drv {
- rockchip,pins =
-@@ -448,23 +95,6 @@
- };
- };
-
-- pmic {
-- pmic_int_l: pmic-int-l {
-- rockchip,pins =
-- <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
-- };
--
-- vsel1_gpio: vsel1-gpio {
-- rockchip,pins =
-- <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
-- };
--
-- vsel2_gpio: vsel2-gpio {
-- rockchip,pins =
-- <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
-- };
-- };
--
- usb2 {
- host_vbus_drv: host-vbus-drv {
- rockchip,pins =
-@@ -473,37 +103,6 @@
- };
- };
-
--&pwm2 {
-- status = "okay";
--};
--
--&pwm3 {
-- status = "okay";
--};
--
--&sdhci {
-- bus-width = <8>;
-- mmc-hs400-1_8v;
-- mmc-hs400-enhanced-strobe;
-- non-removable;
-- status = "okay";
--};
--
--&sdmmc {
-- bus-width = <4>;
-- cap-mmc-highspeed;
-- cap-sd-highspeed;
-- clock-frequency = <100000000>;
-- clock-freq-min-max = <100000 100000000>;
-- disable-wp;
-- sd-uhs-sdr104;
-- vqmmc-supply = <&vcc_sd>;
-- card-detect-delay = <800>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
-- status = "okay";
--};
--
- &tcphy0 {
- status = "okay";
- };
-@@ -538,16 +137,6 @@
- status = "okay";
- };
-
--&uart0 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&uart0_xfer &uart0_cts>;
-- status = "okay";
--};
--
--&uart2 {
-- status = "okay";
--};
--
- &usb_host0_ehci {
- status = "okay";
- };
-@@ -581,19 +170,3 @@
- status = "okay";
- dr_mode = "host";
- };
--
--&vopb {
-- status = "okay";
--};
--
--&vopb_mmu {
-- status = "okay";
--};
--
--&vopl {
-- status = "okay";
--};
--
--&vopl_mmu {
-- status = "okay";
--};
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-new file mode 100644
-index 000000000000..5a5d8e28ef55
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-@@ -0,0 +1,439 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2018 Collabora Ltd.
-+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
-+ * Copyright (c) 2018 Linaro Ltd.
-+ */
-+
-+#include "rk3399.dtsi"
-+#include "rk3399-opp.dtsi"
-+
-+/ {
-+ vcc1v8_s0: vcc1v8-s0 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc1v8_s0";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ };
-+
-+ vcc_sys: vcc-sys {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_sys";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-always-on;
-+ };
-+
-+ vcc3v3_sys: vcc3v3-sys {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ vin-supply = <&vcc_sys>;
-+ };
-+
-+ vdd_log: vdd-log {
-+ compatible = "pwm-regulator";
-+ pwms = <&pwm2 0 25000 0>;
-+ regulator-name = "vdd_log";
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1400000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ vin-supply = <&vcc_sys>;
-+ };
-+
-+};
-+
-+&cpu_l0 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l1 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l2 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l3 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_b0 {
-+ cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&cpu_b1 {
-+ cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&emmc_phy {
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ ddc-i2c-bus = <&i2c3>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hdmi_cec>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ clock-frequency = <400000>;
-+ i2c-scl-rising-time-ns = <168>;
-+ i2c-scl-falling-time-ns = <4>;
-+ status = "okay";
-+
-+ vdd_cpu_b: regulator@40 {
-+ compatible = "silergy,syr827";
-+ reg = <0x40>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu_b";
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-ramp-delay = <1000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ vin-supply = <&vcc_sys>;
-+ status = "okay";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: regulator@41 {
-+ compatible = "silergy,syr828";
-+ reg = <0x41>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_gpu";
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-ramp-delay = <1000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ vin-supply = <&vcc_sys>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk808: pmic@1b {
-+ compatible = "rockchip,rk808";
-+ reg = <0x1b>;
-+ interrupt-parent = <&gpio1>;
-+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int_l>;
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+ #clock-cells = <1>;
-+ clock-output-names = "xin32k", "rk808-clkout2";
-+
-+ vcc1-supply = <&vcc_sys>;
-+ vcc2-supply = <&vcc_sys>;
-+ vcc3-supply = <&vcc_sys>;
-+ vcc4-supply = <&vcc_sys>;
-+ vcc6-supply = <&vcc_sys>;
-+ vcc7-supply = <&vcc_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc_sys>;
-+ vcc10-supply = <&vcc_sys>;
-+ vcc11-supply = <&vcc_sys>;
-+ vcc12-supply = <&vcc3v3_sys>;
-+ vddio-supply = <&vcc_1v8>;
-+
-+ regulators {
-+ vdd_center: DCDC_REG1 {
-+ regulator-name = "vdd_center";
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_cpu_l: DCDC_REG2 {
-+ regulator-name = "vdd_cpu_l";
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG4 {
-+ regulator-name = "vcc_1v8";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcc1v8_dvp: LDO_REG1 {
-+ regulator-name = "vcc1v8_dvp";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca1v8_hdmi: LDO_REG2 {
-+ regulator-name = "vcca1v8_hdmi";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca_1v8: LDO_REG3 {
-+ regulator-name = "vcca_1v8";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcc_sd: LDO_REG4 {
-+ regulator-name = "vcc_sd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcc3v0_sd: LDO_REG5 {
-+ regulator-name = "vcc3v0_sd";
-+ regulator-min-microvolt = <3000000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3000000>;
-+ };
-+ };
-+
-+ vcc_1v5: LDO_REG6 {
-+ regulator-name = "vcc_1v5";
-+ regulator-min-microvolt = <1500000>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1500000>;
-+ };
-+ };
-+
-+ vcca0v9_hdmi: LDO_REG7 {
-+ regulator-name = "vcca0v9_hdmi";
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vcc_3v0: LDO_REG8 {
-+ regulator-name = "vcc_3v0";
-+ regulator-min-microvolt = <3000000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3000000>;
-+ };
-+ };
-+
-+ vcc3v3_s3: SWITCH_REG1 {
-+ regulator-name = "vcc3v3_s3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_s0: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&i2c1 {
-+ status = "okay";
-+};
-+
-+&i2c2 {
-+ status = "okay";
-+};
-+
-+&i2c3 {
-+ status = "okay";
-+};
-+
-+&i2c4 {
-+ status = "okay";
-+};
-+
-+&io_domains {
-+ bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
-+ audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
-+ sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
-+ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
-+ status = "okay";
-+};
-+
-+&pmu_io_domains {
-+ pmu1830-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ sdmmc {
-+ sdmmc_bus1: sdmmc-bus1 {
-+ rockchip,pins =
-+ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
-+ };
-+
-+ sdmmc_bus4: sdmmc-bus4 {
-+ rockchip,pins =
-+ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
-+ <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
-+ <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
-+ <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
-+ };
-+
-+ sdmmc_clk: sdmmc-clk {
-+ rockchip,pins =
-+ <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
-+ };
-+
-+ sdmmc_cmd: sdmmc-cmd {
-+ rockchip,pins =
-+ <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins =
-+ <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+
-+ vsel1_gpio: vsel1-gpio {
-+ rockchip,pins =
-+ <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+
-+ vsel2_gpio: vsel2-gpio {
-+ rockchip,pins =
-+ <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+ };
-+};
-+
-+&pwm2 {
-+ status = "okay";
-+};
-+
-+&pwm3 {
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ mmc-hs400-1_8v;
-+ mmc-hs400-enhanced-strobe;
-+ non-removable;
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ clock-frequency = <100000000>;
-+ clock-freq-min-max = <100000 100000000>;
-+ disable-wp;
-+ sd-uhs-sdr104;
-+ vqmmc-supply = <&vcc_sd>;
-+ card-detect-delay = <800>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&vopb {
-+ status = "okay";
-+};
-+
-+&vopb_mmu {
-+ status = "okay";
-+};
-+
-+&vopl {
-+ status = "okay";
-+};
-+
-+&vopl_mmu {
-+ status = "okay";
-+};
-
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-From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-To: heiko@sntech.de,
- robh+dt@kernel.org
-Subject: [PATCH 2/4] dt-bindings: arm: rockchip: Add binding for Rock960 board
-Date: Mon, 10 Sep 2018 20:43:54 +0530
-Message-Id: <20180910151356.25946-3-manivannan.sadhasivam@linaro.org>
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-Add devicetree binding for Rock960 board from Vamrs Limited.
-
-Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
----
- Documentation/devicetree/bindings/arm/rockchip.txt | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
-index acfd3c773dd0..aaad9e2ff9a3 100644
---- a/Documentation/devicetree/bindings/arm/rockchip.txt
-+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
-@@ -5,6 +5,10 @@ Rockchip platforms device tree bindings
- Required root node properties:
- - compatible = "vamrs,ficus", "rockchip,rk3399";
-
-+- 96boards RK3399 Rock960 (ROCK960 Consumer Edition)
-+ Required root node properties:
-+ - compatible = "vamrs,rk3399-rock960", "rockchip,rk3399";
-+
- - Amarula Vyasa RK3288 board
- Required root node properties:
- - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
-
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-From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-To: heiko@sntech.de,
- robh+dt@kernel.org
-Subject: [PATCH 3/4] arm64: boot: dts: rockchip: Add support for Rock960 board
-Date: Mon, 10 Sep 2018 20:43:55 +0530
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-
-Add devicetree support for Rock960 board, one of the Consumer Edition
-boards of the 96Boards family. This board support utilizes the common
-Rock960 family board support that includes Ficus 96Board.
-
-Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3399-rock960.dts | 139 ++++++++++++++++++
- 2 files changed, 140 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
-
-diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
-index b0092d95b574..57c0d76458e6 100644
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -14,5 +14,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
-new file mode 100644
-index 000000000000..281f3d79b38e
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
-@@ -0,0 +1,139 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2018 Linaro Ltd.
-+ */
-+
-+/dts-v1/;
-+#include "rk3399-rock960.dtsi"
-+
-+/ {
-+ model = "96boards Rock960";
-+ compatible = "vamrs,rk3399-rock960", "rockchip,rk3399";
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ vcc3v3_pcie: vcc3v3-pcie-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_drv>;
-+ regulator-boot-on;
-+ regulator-name = "vcc3v3_pcie";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ vcc5v0_host: vcc5v0-host-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&host_vbus_drv>;
-+ regulator-name = "vcc5v0_host";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-always-on;
-+ vin-supply = <&vcc_sys>;
-+ };
-+};
-+
-+&pinctrl {
-+ pcie {
-+ pcie_drv: pcie-drv {
-+ rockchip,pins =
-+ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb2 {
-+ host_vbus_drv: host-vbus-drv {
-+ rockchip,pins =
-+ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pcie_phy {
-+ status = "okay";
-+};
-+
-+&pcie0 {
-+ ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
-+ num-lanes = <4>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_clkreqn_cpm>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&tcphy0 {
-+ status = "okay";
-+};
-+
-+&tcphy1 {
-+ status = "okay";
-+};
-+
-+&u2phy0 {
-+ status = "okay";
-+};
-+
-+&u2phy1 {
-+ status = "okay";
-+};
-+
-+&u2phy0_host {
-+ phy-supply = <&vcc5v0_host>;
-+ status = "okay";
-+};
-+
-+&u2phy1_host {
-+ phy-supply = <&vcc5v0_host>;
-+ status = "okay";
-+};
-+
-+&u2phy0_otg {
-+ status = "okay";
-+};
-+
-+&u2phy1_otg {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usbdrd3_0 {
-+ status = "okay";
-+};
-+
-+&usbdrd_dwc3_0 {
-+ status = "okay";
-+ dr_mode = "otg";
-+};
-+
-+&usbdrd3_1 {
-+ status = "okay";
-+};
-+
-+&usbdrd_dwc3_1 {
-+ status = "okay";
-+ dr_mode = "host";
-+};
-
-From patchwork Mon Sep 10 15:13:56 2018
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- Mon, 10 Sep 2018 08:14:50 -0700 (PDT)
-From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-To: heiko@sntech.de,
- robh+dt@kernel.org
-Subject: [PATCH 4/4] arm64: dts: rockchip: Enable SD card detection for
- Rock960 boards
-Date: Mon, 10 Sep 2018 20:43:56 +0530
-Message-Id: <20180910151356.25946-5-manivannan.sadhasivam@linaro.org>
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-Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
- tom@vamrs.com, amit.kucheria@linaro.org, shawn.lin@rock-chips.com,
- linux-kernel@vger.kernel.org, vicencb@gmail.com, dev@vamrs.com,
- linux-rockchip@lists.infradead.org, pbrobinson@gmail.com,
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
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-
-For proper working of SD cards, let's add the Card Detect GPIO property
-to the common devicetree for Rock960 family boards.
-
-Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
----
- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-index 5a5d8e28ef55..f68254831ad9 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-@@ -403,6 +403,7 @@
- cap-sd-highspeed;
- clock-frequency = <100000000>;
- clock-freq-min-max = <100000 100000000>;
-+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
- disable-wp;
- sd-uhs-sdr104;
- vqmmc-supply = <&vcc_sd>;
-From patchwork Tue Oct 16 14:00:20 2018
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-X-Patchwork-Submitter: Daniel Lezcano <daniel.lezcano@linaro.org>
-X-Patchwork-Id: 1000432
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- Tue, 16 Oct 2018 07:01:19 -0700 (PDT)
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-To: heiko@sntech.de
-Cc: linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
- Mark Rutland <mark.rutland@arm.com>,
- Vicente Bergas <vicencb@gmail.com>,
- Shawn Lin <shawn.lin@rock-chips.com>,
- Ezequiel Garcia <ezequiel@collabora.com>,
- Enric Balletbo i Serra <enric.balletbo@collabora.com>,
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
- devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
- DEVICE TREE BINDINGS),
- linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC
- support),
- linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC
- support)
-Subject: [PATCH] DT: rockchip: Fix stability issues with the 'performance'
- governor on rock960
-Date: Tue, 16 Oct 2018 16:00:20 +0200
-Message-Id: <1539698431-12616-1-git-send-email-daniel.lezcano@linaro.org>
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-
-When the performance governor is set as default, the rock960 hangs
-around one minute after booting, whatever the activity is (idle, key
-pressed, loaded, ...).
-
-Based on the commit log found at https://patchwork.kernel.org/patch/10092377/
-
-"vdd_log has no consumer and therefore will not be set to a specific
-voltage. Still the PWM output pin gets configured and thence the vdd_log
-output voltage will changed from it's default. Depending on the idle
-state of the PWM this will slightly over or undervoltage the logic supply
-of the RK3399 and cause instability with GbE (undervoltage) and PCIe
-(overvoltage). Since the default value set by a voltage divider is the
-correct supply voltage and we don't need to change it during runtime we
-remove the rail from the devicetree completely so the PWM pin will not
-be configured."
-
-After removing the vdd-log from the rock960's specific DT, the board
-does no longer hang and shows a stable behavior.
-
-Apply the same change for the rock960 by removing the vdd-log from the
-DT.
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
----
- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 12 ------------
- 1 file changed, 12 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-index 6c8c4ab..56abbb0 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
-@@ -57,18 +57,6 @@
- regulator-always-on;
- vin-supply = <&vcc_sys>;
- };
--
-- vdd_log: vdd-log {
-- compatible = "pwm-regulator";
-- pwms = <&pwm2 0 25000 0>;
-- regulator-name = "vdd_log";
-- regulator-min-microvolt = <800000>;
-- regulator-max-microvolt = <1400000>;
-- regulator-always-on;
-- regulator-boot-on;
-- vin-supply = <&vcc_sys>;
-- };
--
- };
-
- &cpu_l0 {
diff --git a/arm64-ZynqMP-firmware-clock-drivers-core.patch b/arm64-ZynqMP-firmware-clock-drivers-core.patch
deleted file mode 100644
index f8824e505..000000000
--- a/arm64-ZynqMP-firmware-clock-drivers-core.patch
+++ /dev/null
@@ -1,5481 +0,0 @@
-From patchwork Fri Aug 3 17:53:18 2018
-Content-Type: text/plain; charset="utf-8"
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-Subject: [PATCH v11 01/11] dt-bindings: firmware: Add bindings for ZynqMP
- firmware
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-From: Rajan Vaja <rajanv@xilinx.com>
-
-Add documentation to describe Xilinx ZynqMP firmware driver
-bindings. Firmware driver provides an interface to firmware
-APIs. Interface APIs can be used by any driver to communicate
-to PMUFW (Platform Management Unit).
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
----
- .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 29 ++++++++++++++++++++++
- 1 file changed, 29 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
-
-diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
-new file mode 100644
-index 0000000..1b431d9
---- /dev/null
-+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
-@@ -0,0 +1,29 @@
-+-----------------------------------------------------------------
-+Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
-+-----------------------------------------------------------------
-+
-+The zynqmp-firmware node describes the interface to platform firmware.
-+ZynqMP has an interface to communicate with secure firmware. Firmware
-+driver provides an interface to firmware APIs. Interface APIs can be
-+used by any driver to communicate to PMUFW(Platform Management Unit).
-+These requests include clock management, pin control, device control,
-+power management service, FPGA service and other platform management
-+services.
-+
-+Required properties:
-+ - compatible: Must contain: "xlnx,zynqmp-firmware"
-+ - method: The method of calling the PM-API firmware layer.
-+ Permitted values are:
-+ - "smc" : SMC #0, following the SMCCC
-+ - "hvc" : HVC #0, following the SMCCC
-+
-+-------
-+Example
-+-------
-+
-+firmware {
-+ zynqmp_firmware: zynqmp-firmware {
-+ compatible = "xlnx,zynqmp-firmware";
-+ method = "smc";
-+ };
-+};
-
-From patchwork Fri Aug 3 17:53:19 2018
-Content-Type: text/plain; charset="utf-8"
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-X-Patchwork-Submitter: Jolly Shah <jolly.shah@xilinx.com>
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-Subject: [PATCH v11 02/11] firmware: xilinx: Add Zynqmp firmware driver
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-Cc: devicetree@vger.kernel.org, rajanv@xilinx.com,
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-From: Rajan Vaja <rajanv@xilinx.com>
-
-This patch is adding communication layer with firmware.
-Firmware driver provides an interface to firmware APIs.
-Interface APIs can be used by any driver to communicate to
-PMUFW(Platform Management Unit). All requests go through ATF.
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
----
- arch/arm64/Kconfig.platforms | 1 +
- drivers/firmware/Kconfig | 1 +
- drivers/firmware/Makefile | 1 +
- drivers/firmware/xilinx/Kconfig | 16 ++
- drivers/firmware/xilinx/Makefile | 4 +
- drivers/firmware/xilinx/zynqmp.c | 337 +++++++++++++++++++++++++++++++++++
- include/linux/firmware/xlnx-zynqmp.h | 63 +++++++
- 7 files changed, 423 insertions(+)
- create mode 100644 drivers/firmware/xilinx/Kconfig
- create mode 100644 drivers/firmware/xilinx/Makefile
- create mode 100644 drivers/firmware/xilinx/zynqmp.c
- create mode 100644 include/linux/firmware/xlnx-zynqmp.h
-
-diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
-index fbedbd8..6454458 100644
---- a/arch/arm64/Kconfig.platforms
-+++ b/arch/arm64/Kconfig.platforms
-@@ -274,6 +274,7 @@ config ARCH_ZX
-
- config ARCH_ZYNQMP
- bool "Xilinx ZynqMP Family"
-+ select ZYNQMP_FIRMWARE
- help
- This enables support for Xilinx ZynqMP Family
-
-diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
-index b7c7482..f41eb0d 100644
---- a/drivers/firmware/Kconfig
-+++ b/drivers/firmware/Kconfig
-@@ -257,5 +257,6 @@ source "drivers/firmware/google/Kconfig"
- source "drivers/firmware/efi/Kconfig"
- source "drivers/firmware/meson/Kconfig"
- source "drivers/firmware/tegra/Kconfig"
-+source "drivers/firmware/xilinx/Kconfig"
-
- endmenu
-diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
-index b248238..f90363e 100644
---- a/drivers/firmware/Makefile
-+++ b/drivers/firmware/Makefile
-@@ -31,3 +31,4 @@ obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
- obj-$(CONFIG_EFI) += efi/
- obj-$(CONFIG_UEFI_CPER) += efi/
- obj-y += tegra/
-+obj-y += xilinx/
-diff --git a/drivers/firmware/xilinx/Kconfig b/drivers/firmware/xilinx/Kconfig
-new file mode 100644
-index 0000000..64d976e
---- /dev/null
-+++ b/drivers/firmware/xilinx/Kconfig
-@@ -0,0 +1,16 @@
-+# SPDX-License-Identifier: GPL-2.0
-+# Kconfig for Xilinx firmwares
-+
-+menu "Zynq MPSoC Firmware Drivers"
-+ depends on ARCH_ZYNQMP
-+
-+config ZYNQMP_FIRMWARE
-+ bool "Enable Xilinx Zynq MPSoC firmware interface"
-+ help
-+ Firmware interface driver is used by different
-+ drivers to communicate with the firmware for
-+ various platform management services.
-+ Say yes to enable ZynqMP firmware interface driver.
-+ If in doubt, say N.
-+
-+endmenu
-diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile
-new file mode 100644
-index 0000000..29f7bf2
---- /dev/null
-+++ b/drivers/firmware/xilinx/Makefile
-@@ -0,0 +1,4 @@
-+# SPDX-License-Identifier: GPL-2.0
-+# Makefile for Xilinx firmwares
-+
-+obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o
-diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
-new file mode 100644
-index 0000000..edbb84e
---- /dev/null
-+++ b/drivers/firmware/xilinx/zynqmp.c
-@@ -0,0 +1,337 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Xilinx Zynq MPSoC Firmware layer
-+ *
-+ * Copyright (C) 2014-2018 Xilinx, Inc.
-+ *
-+ * Michal Simek <michal.simek@xilinx.com>
-+ * Davorin Mista <davorin.mista@aggios.com>
-+ * Jolly Shah <jollys@xilinx.com>
-+ * Rajan Vaja <rajanv@xilinx.com>
-+ */
-+
-+#include <linux/arm-smccc.h>
-+#include <linux/compiler.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/slab.h>
-+#include <linux/uaccess.h>
-+
-+#include <linux/firmware/xlnx-zynqmp.h>
-+
-+/**
-+ * zynqmp_pm_ret_code() - Convert PMU-FW error codes to Linux error codes
-+ * @ret_status: PMUFW return code
-+ *
-+ * Return: corresponding Linux error code
-+ */
-+static int zynqmp_pm_ret_code(u32 ret_status)
-+{
-+ switch (ret_status) {
-+ case XST_PM_SUCCESS:
-+ case XST_PM_DOUBLE_REQ:
-+ return 0;
-+ case XST_PM_NO_ACCESS:
-+ return -EACCES;
-+ case XST_PM_ABORT_SUSPEND:
-+ return -ECANCELED;
-+ case XST_PM_INTERNAL:
-+ case XST_PM_CONFLICT:
-+ case XST_PM_INVALID_NODE:
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static noinline int do_fw_call_fail(u64 arg0, u64 arg1, u64 arg2,
-+ u32 *ret_payload)
-+{
-+ return -ENODEV;
-+}
-+
-+/*
-+ * PM function call wrapper
-+ * Invoke do_fw_call_smc or do_fw_call_hvc, depending on the configuration
-+ */
-+static int (*do_fw_call)(u64, u64, u64, u32 *ret_payload) = do_fw_call_fail;
-+
-+/**
-+ * do_fw_call_smc() - Call system-level platform management layer (SMC)
-+ * @arg0: Argument 0 to SMC call
-+ * @arg1: Argument 1 to SMC call
-+ * @arg2: Argument 2 to SMC call
-+ * @ret_payload: Returned value array
-+ *
-+ * Invoke platform management function via SMC call (no hypervisor present).
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static noinline int do_fw_call_smc(u64 arg0, u64 arg1, u64 arg2,
-+ u32 *ret_payload)
-+{
-+ struct arm_smccc_res res;
-+
-+ arm_smccc_smc(arg0, arg1, arg2, 0, 0, 0, 0, 0, &res);
-+
-+ if (ret_payload) {
-+ ret_payload[0] = lower_32_bits(res.a0);
-+ ret_payload[1] = upper_32_bits(res.a0);
-+ ret_payload[2] = lower_32_bits(res.a1);
-+ ret_payload[3] = upper_32_bits(res.a1);
-+ }
-+
-+ return zynqmp_pm_ret_code((enum pm_ret_status)res.a0);
-+}
-+
-+/**
-+ * do_fw_call_hvc() - Call system-level platform management layer (HVC)
-+ * @arg0: Argument 0 to HVC call
-+ * @arg1: Argument 1 to HVC call
-+ * @arg2: Argument 2 to HVC call
-+ * @ret_payload: Returned value array
-+ *
-+ * Invoke platform management function via HVC
-+ * HVC-based for communication through hypervisor
-+ * (no direct communication with ATF).
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static noinline int do_fw_call_hvc(u64 arg0, u64 arg1, u64 arg2,
-+ u32 *ret_payload)
-+{
-+ struct arm_smccc_res res;
-+
-+ arm_smccc_hvc(arg0, arg1, arg2, 0, 0, 0, 0, 0, &res);
-+
-+ if (ret_payload) {
-+ ret_payload[0] = lower_32_bits(res.a0);
-+ ret_payload[1] = upper_32_bits(res.a0);
-+ ret_payload[2] = lower_32_bits(res.a1);
-+ ret_payload[3] = upper_32_bits(res.a1);
-+ }
-+
-+ return zynqmp_pm_ret_code((enum pm_ret_status)res.a0);
-+}
-+
-+/**
-+ * zynqmp_pm_invoke_fn() - Invoke the system-level platform management layer
-+ * caller function depending on the configuration
-+ * @pm_api_id: Requested PM-API call
-+ * @arg0: Argument 0 to requested PM-API call
-+ * @arg1: Argument 1 to requested PM-API call
-+ * @arg2: Argument 2 to requested PM-API call
-+ * @arg3: Argument 3 to requested PM-API call
-+ * @ret_payload: Returned value array
-+ *
-+ * Invoke platform management function for SMC or HVC call, depending on
-+ * configuration.
-+ * Following SMC Calling Convention (SMCCC) for SMC64:
-+ * Pm Function Identifier,
-+ * PM_SIP_SVC + PM_API_ID =
-+ * ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT)
-+ * ((SMC_64) << FUNCID_CC_SHIFT)
-+ * ((SIP_START) << FUNCID_OEN_SHIFT)
-+ * ((PM_API_ID) & FUNCID_NUM_MASK))
-+ *
-+ * PM_SIP_SVC - Registered ZynqMP SIP Service Call.
-+ * PM_API_ID - Platform Management API ID.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
-+ u32 arg2, u32 arg3, u32 *ret_payload)
-+{
-+ /*
-+ * Added SIP service call Function Identifier
-+ * Make sure to stay in x0 register
-+ */
-+ u64 smc_arg[4];
-+
-+ smc_arg[0] = PM_SIP_SVC | pm_api_id;
-+ smc_arg[1] = ((u64)arg1 << 32) | arg0;
-+ smc_arg[2] = ((u64)arg3 << 32) | arg2;
-+
-+ return do_fw_call(smc_arg[0], smc_arg[1], smc_arg[2], ret_payload);
-+}
-+
-+static u32 pm_api_version;
-+static u32 pm_tz_version;
-+
-+/**
-+ * zynqmp_pm_get_api_version() - Get version number of PMU PM firmware
-+ * @version: Returned version value
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_get_api_version(u32 *version)
-+{
-+ u32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ if (!version)
-+ return -EINVAL;
-+
-+ /* Check is PM API version already verified */
-+ if (pm_api_version > 0) {
-+ *version = pm_api_version;
-+ return 0;
-+ }
-+ ret = zynqmp_pm_invoke_fn(PM_GET_API_VERSION, 0, 0, 0, 0, ret_payload);
-+ *version = ret_payload[1];
-+
-+ return ret;
-+}
-+
-+/**
-+ * zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version
-+ * @version: Returned version value
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_get_trustzone_version(u32 *version)
-+{
-+ u32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ if (!version)
-+ return -EINVAL;
-+
-+ /* Check is PM trustzone version already verified */
-+ if (pm_tz_version > 0) {
-+ *version = pm_tz_version;
-+ return 0;
-+ }
-+ ret = zynqmp_pm_invoke_fn(PM_GET_TRUSTZONE_VERSION, 0, 0,
-+ 0, 0, ret_payload);
-+ *version = ret_payload[1];
-+
-+ return ret;
-+}
-+
-+/**
-+ * get_set_conduit_method() - Choose SMC or HVC based communication
-+ * @np: Pointer to the device_node structure
-+ *
-+ * Use SMC or HVC-based functions to communicate with EL2/EL3.
-+ *
-+ * Return: Returns 0 on success or error code
-+ */
-+static int get_set_conduit_method(struct device_node *np)
-+{
-+ const char *method;
-+
-+ if (of_property_read_string(np, "method", &method)) {
-+ pr_warn("%s missing \"method\" property\n", __func__);
-+ return -ENXIO;
-+ }
-+
-+ if (!strcmp("hvc", method)) {
-+ do_fw_call = do_fw_call_hvc;
-+ } else if (!strcmp("smc", method)) {
-+ do_fw_call = do_fw_call_smc;
-+ } else {
-+ pr_warn("%s Invalid \"method\" property: %s\n",
-+ __func__, method);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct zynqmp_eemi_ops eemi_ops = {
-+ .get_api_version = zynqmp_pm_get_api_version,
-+};
-+
-+/**
-+ * zynqmp_pm_get_eemi_ops - Get eemi ops functions
-+ *
-+ * Return: Pointer of eemi_ops structure
-+ */
-+const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
-+{
-+ return &eemi_ops;
-+}
-+EXPORT_SYMBOL_GPL(zynqmp_pm_get_eemi_ops);
-+
-+static int zynqmp_firmware_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+
-+ return of_platform_populate(dev->of_node, NULL, NULL, dev);
-+}
-+
-+static const struct of_device_id zynqmp_firmware_of_match[] = {
-+ {.compatible = "xlnx,zynqmp-firmware"},
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, zynqmp_firmware_of_match);
-+
-+static struct platform_driver zynqmp_firmware_driver = {
-+ .driver = {
-+ .name = "zynqmp_firmware",
-+ .of_match_table = zynqmp_firmware_of_match,
-+ },
-+ .probe = zynqmp_firmware_probe,
-+};
-+module_platform_driver(zynqmp_firmware_driver);
-+
-+static int __init zynqmp_plat_init(void)
-+{
-+ int ret;
-+ struct device_node *np;
-+
-+ np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp");
-+ if (!np)
-+ return 0;
-+ of_node_put(np);
-+
-+ /*
-+ * We're running on a ZynqMP machine,
-+ * the zynqmp-firmware node is mandatory.
-+ */
-+ np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp-firmware");
-+ if (!np) {
-+ pr_warn("%s: zynqmp-firmware node not found\n", __func__);
-+ return -ENXIO;
-+ }
-+
-+ ret = get_set_conduit_method(np);
-+ if (ret) {
-+ of_node_put(np);
-+ return ret;
-+ }
-+
-+ /* Check PM API version number */
-+ zynqmp_pm_get_api_version(&pm_api_version);
-+ if (pm_api_version < ZYNQMP_PM_VERSION) {
-+ panic("%s Platform Management API version error. Expected: v%d.%d - Found: v%d.%d\n",
-+ __func__,
-+ ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR,
-+ pm_api_version >> 16, pm_api_version & 0xFFFF);
-+ }
-+
-+ pr_info("%s Platform Management API v%d.%d\n", __func__,
-+ pm_api_version >> 16, pm_api_version & 0xFFFF);
-+
-+ /* Check trustzone version number */
-+ ret = zynqmp_pm_get_trustzone_version(&pm_tz_version);
-+ if (ret)
-+ panic("Legacy trustzone found without version support\n");
-+
-+ if (pm_tz_version < ZYNQMP_TZ_VERSION)
-+ panic("%s Trustzone version error. Expected: v%d.%d - Found: v%d.%d\n",
-+ __func__,
-+ ZYNQMP_TZ_VERSION_MAJOR, ZYNQMP_TZ_VERSION_MINOR,
-+ pm_tz_version >> 16, pm_tz_version & 0xFFFF);
-+
-+ pr_info("%s Trustzone version v%d.%d\n", __func__,
-+ pm_tz_version >> 16, pm_tz_version & 0xFFFF);
-+
-+ of_node_put(np);
-+
-+ return ret;
-+}
-+early_initcall(zynqmp_plat_init);
-diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
-new file mode 100644
-index 0000000..cb63bed
---- /dev/null
-+++ b/include/linux/firmware/xlnx-zynqmp.h
-@@ -0,0 +1,63 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Xilinx Zynq MPSoC Firmware layer
-+ *
-+ * Copyright (C) 2014-2018 Xilinx
-+ *
-+ * Michal Simek <michal.simek@xilinx.com>
-+ * Davorin Mista <davorin.mista@aggios.com>
-+ * Jolly Shah <jollys@xilinx.com>
-+ * Rajan Vaja <rajanv@xilinx.com>
-+ */
-+
-+#ifndef __FIRMWARE_ZYNQMP_H__
-+#define __FIRMWARE_ZYNQMP_H__
-+
-+#define ZYNQMP_PM_VERSION_MAJOR 1
-+#define ZYNQMP_PM_VERSION_MINOR 0
-+
-+#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
-+ ZYNQMP_PM_VERSION_MINOR)
-+
-+#define ZYNQMP_TZ_VERSION_MAJOR 1
-+#define ZYNQMP_TZ_VERSION_MINOR 0
-+
-+#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
-+ ZYNQMP_TZ_VERSION_MINOR)
-+
-+/* SMC SIP service Call Function Identifier Prefix */
-+#define PM_SIP_SVC 0xC2000000
-+#define PM_GET_TRUSTZONE_VERSION 0xa03
-+
-+/* Number of 32bits values in payload */
-+#define PAYLOAD_ARG_CNT 4U
-+
-+enum pm_api_id {
-+ PM_GET_API_VERSION = 1,
-+};
-+
-+/* PMU-FW return status codes */
-+enum pm_ret_status {
-+ XST_PM_SUCCESS = 0,
-+ XST_PM_INTERNAL = 2000,
-+ XST_PM_CONFLICT,
-+ XST_PM_NO_ACCESS,
-+ XST_PM_INVALID_NODE,
-+ XST_PM_DOUBLE_REQ,
-+ XST_PM_ABORT_SUSPEND,
-+};
-+
-+struct zynqmp_eemi_ops {
-+ int (*get_api_version)(u32 *version);
-+};
-+
-+#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
-+const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
-+#else
-+static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
-+{
-+ return NULL;
-+}
-+#endif
-+
-+#endif /* __FIRMWARE_ZYNQMP_H__ */
-
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-Subject: [PATCH v11 03/11] firmware: xilinx: Add zynqmp IOCTL API for device
- control
-Date: Fri, 3 Aug 2018 10:53:20 -0700
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-Cc: devicetree@vger.kernel.org, rajanv@xilinx.com,
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-From: Rajan Vaja <rajanv@xilinx.com>
-
-Add ZynqMP firmware IOCTL API to control and configure
-devices like PLLs, SD, Gem, etc.
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
----
- drivers/firmware/xilinx/zynqmp.c | 20 ++++++++++++++++++++
- include/linux/firmware/xlnx-zynqmp.h | 2 ++
- 2 files changed, 22 insertions(+)
-
-diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
-index edbb84e..24cfd9e 100644
---- a/drivers/firmware/xilinx/zynqmp.c
-+++ b/drivers/firmware/xilinx/zynqmp.c
-@@ -241,8 +241,28 @@ static int get_set_conduit_method(struct device_node *np)
- return 0;
- }
-
-+/**
-+ * zynqmp_pm_ioctl() - PM IOCTL API for device control and configs
-+ * @node_id: Node ID of the device
-+ * @ioctl_id: ID of the requested IOCTL
-+ * @arg1: Argument 1 to requested IOCTL call
-+ * @arg2: Argument 2 to requested IOCTL call
-+ * @out: Returned output value
-+ *
-+ * This function calls IOCTL to firmware for device control and configuration.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2,
-+ u32 *out)
-+{
-+ return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, ioctl_id,
-+ arg1, arg2, out);
-+}
-+
- static const struct zynqmp_eemi_ops eemi_ops = {
- .get_api_version = zynqmp_pm_get_api_version,
-+ .ioctl = zynqmp_pm_ioctl,
- };
-
- /**
-diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
-index cb63bed..2eec6e7 100644
---- a/include/linux/firmware/xlnx-zynqmp.h
-+++ b/include/linux/firmware/xlnx-zynqmp.h
-@@ -34,6 +34,7 @@
-
- enum pm_api_id {
- PM_GET_API_VERSION = 1,
-+ PM_IOCTL = 34,
- };
-
- /* PMU-FW return status codes */
-@@ -49,6 +50,7 @@ enum pm_ret_status {
-
- struct zynqmp_eemi_ops {
- int (*get_api_version)(u32 *version);
-+ int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
- };
-
- #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
-
-From patchwork Fri Aug 3 17:53:21 2018
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-Subject: [PATCH v11 04/11] firmware: xilinx: Add query data API
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-From: Rajan Vaja <rajanv@xilinx.com>
-
-Add ZynqMP firmware query data API to query platform
-specific information(clocks, pins) from firmware.
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
----
- drivers/firmware/xilinx/zynqmp.c | 14 ++++++++++++++
- include/linux/firmware/xlnx-zynqmp.h | 20 ++++++++++++++++++++
- 2 files changed, 34 insertions(+)
-
-diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
-index 24cfd9e..8ec5682 100644
---- a/drivers/firmware/xilinx/zynqmp.c
-+++ b/drivers/firmware/xilinx/zynqmp.c
-@@ -260,9 +260,23 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2,
- arg1, arg2, out);
- }
-
-+/**
-+ * zynqmp_pm_query_data() - Get query data from firmware
-+ * @qdata: Variable to the zynqmp_pm_query_data structure
-+ * @out: Returned output value
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out)
-+{
-+ return zynqmp_pm_invoke_fn(PM_QUERY_DATA, qdata.qid, qdata.arg1,
-+ qdata.arg2, qdata.arg3, out);
-+}
-+
- static const struct zynqmp_eemi_ops eemi_ops = {
- .get_api_version = zynqmp_pm_get_api_version,
- .ioctl = zynqmp_pm_ioctl,
-+ .query_data = zynqmp_pm_query_data,
- };
-
- /**
-diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
-index 2eec6e7..55ed2ba 100644
---- a/include/linux/firmware/xlnx-zynqmp.h
-+++ b/include/linux/firmware/xlnx-zynqmp.h
-@@ -35,6 +35,7 @@
- enum pm_api_id {
- PM_GET_API_VERSION = 1,
- PM_IOCTL = 34,
-+ PM_QUERY_DATA,
- };
-
- /* PMU-FW return status codes */
-@@ -48,9 +49,28 @@ enum pm_ret_status {
- XST_PM_ABORT_SUSPEND,
- };
-
-+enum pm_query_id {
-+ PM_QID_INVALID,
-+};
-+
-+/**
-+ * struct zynqmp_pm_query_data - PM query data
-+ * @qid: query ID
-+ * @arg1: Argument 1 of query data
-+ * @arg2: Argument 2 of query data
-+ * @arg3: Argument 3 of query data
-+ */
-+struct zynqmp_pm_query_data {
-+ u32 qid;
-+ u32 arg1;
-+ u32 arg2;
-+ u32 arg3;
-+};
-+
- struct zynqmp_eemi_ops {
- int (*get_api_version)(u32 *version);
- int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
-+ int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
- };
-
- #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
-
-From patchwork Fri Aug 3 17:53:22 2018
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-From: Rajan Vaja <rajanv@xilinx.com>
-
-Add clock APIs to control clocks through firmware
-interface.
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
----
- drivers/firmware/xilinx/zynqmp.c | 186 ++++++++++++++++++++++++++++++++++-
- include/linux/firmware/xlnx-zynqmp.h | 30 ++++++
- 2 files changed, 214 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
-index 8ec5682..41ed800 100644
---- a/drivers/firmware/xilinx/zynqmp.c
-+++ b/drivers/firmware/xilinx/zynqmp.c
-@@ -269,14 +269,196 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2,
- */
- static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out)
- {
-- return zynqmp_pm_invoke_fn(PM_QUERY_DATA, qdata.qid, qdata.arg1,
-- qdata.arg2, qdata.arg3, out);
-+ int ret;
-+
-+ ret = zynqmp_pm_invoke_fn(PM_QUERY_DATA, qdata.qid, qdata.arg1,
-+ qdata.arg2, qdata.arg3, out);
-+
-+ /*
-+ * For clock name query, all bytes in SMC response are clock name
-+ * characters and return code is always success. For invalid clocks,
-+ * clock name bytes would be zeros.
-+ */
-+ return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : ret;
-+}
-+
-+/**
-+ * zynqmp_pm_clock_enable() - Enable the clock for given id
-+ * @clock_id: ID of the clock to be enabled
-+ *
-+ * This function is used by master to enable the clock
-+ * including peripherals and PLL clocks.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_clock_enable(u32 clock_id)
-+{
-+ return zynqmp_pm_invoke_fn(PM_CLOCK_ENABLE, clock_id, 0, 0, 0, NULL);
-+}
-+
-+/**
-+ * zynqmp_pm_clock_disable() - Disable the clock for given id
-+ * @clock_id: ID of the clock to be disable
-+ *
-+ * This function is used by master to disable the clock
-+ * including peripherals and PLL clocks.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_clock_disable(u32 clock_id)
-+{
-+ return zynqmp_pm_invoke_fn(PM_CLOCK_DISABLE, clock_id, 0, 0, 0, NULL);
-+}
-+
-+/**
-+ * zynqmp_pm_clock_getstate() - Get the clock state for given id
-+ * @clock_id: ID of the clock to be queried
-+ * @state: 1/0 (Enabled/Disabled)
-+ *
-+ * This function is used by master to get the state of clock
-+ * including peripherals and PLL clocks.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
-+{
-+ u32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETSTATE, clock_id, 0,
-+ 0, 0, ret_payload);
-+ *state = ret_payload[1];
-+
-+ return ret;
-+}
-+
-+/**
-+ * zynqmp_pm_clock_setdivider() - Set the clock divider for given id
-+ * @clock_id: ID of the clock
-+ * @divider: divider value
-+ *
-+ * This function is used by master to set divider for any clock
-+ * to achieve desired rate.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
-+{
-+ return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, clock_id, divider,
-+ 0, 0, NULL);
-+}
-+
-+/**
-+ * zynqmp_pm_clock_getdivider() - Get the clock divider for given id
-+ * @clock_id: ID of the clock
-+ * @divider: divider value
-+ *
-+ * This function is used by master to get divider values
-+ * for any clock.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
-+{
-+ u32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETDIVIDER, clock_id, 0,
-+ 0, 0, ret_payload);
-+ *divider = ret_payload[1];
-+
-+ return ret;
-+}
-+
-+/**
-+ * zynqmp_pm_clock_setrate() - Set the clock rate for given id
-+ * @clock_id: ID of the clock
-+ * @rate: rate value in hz
-+ *
-+ * This function is used by master to set rate for any clock.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
-+{
-+ return zynqmp_pm_invoke_fn(PM_CLOCK_SETRATE, clock_id,
-+ lower_32_bits(rate),
-+ upper_32_bits(rate),
-+ 0, NULL);
-+}
-+
-+/**
-+ * zynqmp_pm_clock_getrate() - Get the clock rate for given id
-+ * @clock_id: ID of the clock
-+ * @rate: rate value in hz
-+ *
-+ * This function is used by master to get rate
-+ * for any clock.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
-+{
-+ u32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETRATE, clock_id, 0,
-+ 0, 0, ret_payload);
-+ *rate = ((u64)ret_payload[2] << 32) | ret_payload[1];
-+
-+ return ret;
-+}
-+
-+/**
-+ * zynqmp_pm_clock_setparent() - Set the clock parent for given id
-+ * @clock_id: ID of the clock
-+ * @parent_id: parent id
-+ *
-+ * This function is used by master to set parent for any clock.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
-+{
-+ return zynqmp_pm_invoke_fn(PM_CLOCK_SETPARENT, clock_id,
-+ parent_id, 0, 0, NULL);
-+}
-+
-+/**
-+ * zynqmp_pm_clock_getparent() - Get the clock parent for given id
-+ * @clock_id: ID of the clock
-+ * @parent_id: parent id
-+ *
-+ * This function is used by master to get parent index
-+ * for any clock.
-+ *
-+ * Return: Returns status, either success or error+reason
-+ */
-+static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
-+{
-+ u32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETPARENT, clock_id, 0,
-+ 0, 0, ret_payload);
-+ *parent_id = ret_payload[1];
-+
-+ return ret;
- }
-
- static const struct zynqmp_eemi_ops eemi_ops = {
- .get_api_version = zynqmp_pm_get_api_version,
- .ioctl = zynqmp_pm_ioctl,
- .query_data = zynqmp_pm_query_data,
-+ .clock_enable = zynqmp_pm_clock_enable,
-+ .clock_disable = zynqmp_pm_clock_disable,
-+ .clock_getstate = zynqmp_pm_clock_getstate,
-+ .clock_setdivider = zynqmp_pm_clock_setdivider,
-+ .clock_getdivider = zynqmp_pm_clock_getdivider,
-+ .clock_setrate = zynqmp_pm_clock_setrate,
-+ .clock_getrate = zynqmp_pm_clock_getrate,
-+ .clock_setparent = zynqmp_pm_clock_setparent,
-+ .clock_getparent = zynqmp_pm_clock_getparent,
- };
-
- /**
-diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
-index 55ed2ba..58a7478 100644
---- a/include/linux/firmware/xlnx-zynqmp.h
-+++ b/include/linux/firmware/xlnx-zynqmp.h
-@@ -36,6 +36,15 @@ enum pm_api_id {
- PM_GET_API_VERSION = 1,
- PM_IOCTL = 34,
- PM_QUERY_DATA,
-+ PM_CLOCK_ENABLE,
-+ PM_CLOCK_DISABLE,
-+ PM_CLOCK_GETSTATE,
-+ PM_CLOCK_SETDIVIDER,
-+ PM_CLOCK_GETDIVIDER,
-+ PM_CLOCK_SETRATE,
-+ PM_CLOCK_GETRATE,
-+ PM_CLOCK_SETPARENT,
-+ PM_CLOCK_GETPARENT,
- };
-
- /* PMU-FW return status codes */
-@@ -49,8 +58,20 @@ enum pm_ret_status {
- XST_PM_ABORT_SUSPEND,
- };
-
-+enum pm_ioctl_id {
-+ IOCTL_SET_PLL_FRAC_MODE = 8,
-+ IOCTL_GET_PLL_FRAC_MODE,
-+ IOCTL_SET_PLL_FRAC_DATA,
-+ IOCTL_GET_PLL_FRAC_DATA,
-+};
-+
- enum pm_query_id {
- PM_QID_INVALID,
-+ PM_QID_CLOCK_GET_NAME,
-+ PM_QID_CLOCK_GET_TOPOLOGY,
-+ PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
-+ PM_QID_CLOCK_GET_PARENTS,
-+ PM_QID_CLOCK_GET_ATTRIBUTES,
- };
-
- /**
-@@ -71,6 +92,15 @@ struct zynqmp_eemi_ops {
- int (*get_api_version)(u32 *version);
- int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
- int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
-+ int (*clock_enable)(u32 clock_id);
-+ int (*clock_disable)(u32 clock_id);
-+ int (*clock_getstate)(u32 clock_id, u32 *state);
-+ int (*clock_setdivider)(u32 clock_id, u32 divider);
-+ int (*clock_getdivider)(u32 clock_id, u32 *divider);
-+ int (*clock_setrate)(u32 clock_id, u64 rate);
-+ int (*clock_getrate)(u32 clock_id, u64 *rate);
-+ int (*clock_setparent)(u32 clock_id, u32 parent_id);
-+ int (*clock_getparent)(u32 clock_id, u32 *parent_id);
- };
-
- #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
-
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-Subject: [PATCH v11 06/11] firmware: xilinx: Add debugfs interface
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-Cc: devicetree@vger.kernel.org, rajanv@xilinx.com,
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-From: Rajan Vaja <rajanv@xilinx.com>
-
-Firmware-debug provides debugfs interface to all APIs.
-Debugfs can be used to call firmware APIs with required
-parameters.
-
-Usage:
-* Calling firmware API through debugfs:
- # echo "<api-name> <arg1> .. <argn>" > /sys/.../zynqmp-firmware/pm
-
-* Read output of last called firmware API:
- # cat /sys/.../zynqmp-firmware/pm
-
-Refer ug1200 for more information on these APIs:
- * https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf
-
-Add basic debugfs file to get API version.
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
----
- drivers/firmware/xilinx/Kconfig | 7 ++
- drivers/firmware/xilinx/Makefile | 1 +
- drivers/firmware/xilinx/zynqmp-debug.c | 212 +++++++++++++++++++++++++++++++++
- drivers/firmware/xilinx/zynqmp-debug.h | 22 ++++
- drivers/firmware/xilinx/zynqmp.c | 9 ++
- 5 files changed, 251 insertions(+)
- create mode 100644 drivers/firmware/xilinx/zynqmp-debug.c
- create mode 100644 drivers/firmware/xilinx/zynqmp-debug.h
-
-diff --git a/drivers/firmware/xilinx/Kconfig b/drivers/firmware/xilinx/Kconfig
-index 64d976e..8f44b9c 100644
---- a/drivers/firmware/xilinx/Kconfig
-+++ b/drivers/firmware/xilinx/Kconfig
-@@ -13,4 +13,11 @@ config ZYNQMP_FIRMWARE
- Say yes to enable ZynqMP firmware interface driver.
- If in doubt, say N.
-
-+config ZYNQMP_FIRMWARE_DEBUG
-+ bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
-+ depends on ZYNQMP_FIRMWARE && DEBUG_FS
-+ help
-+ Say yes to enable ZynqMP firmware interface debug APIs.
-+ If in doubt, say N.
-+
- endmenu
-diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile
-index 29f7bf2..875a537 100644
---- a/drivers/firmware/xilinx/Makefile
-+++ b/drivers/firmware/xilinx/Makefile
-@@ -2,3 +2,4 @@
- # Makefile for Xilinx firmwares
-
- obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o
-+obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) += zynqmp-debug.o
-diff --git a/drivers/firmware/xilinx/zynqmp-debug.c b/drivers/firmware/xilinx/zynqmp-debug.c
-new file mode 100644
-index 0000000..fcbdd6e
---- /dev/null
-+++ b/drivers/firmware/xilinx/zynqmp-debug.c
-@@ -0,0 +1,212 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Xilinx Zynq MPSoC Firmware layer for debugfs APIs
-+ *
-+ * Copyright (C) 2014-2018 Xilinx, Inc.
-+ *
-+ * Michal Simek <michal.simek@xilinx.com>
-+ * Davorin Mista <davorin.mista@aggios.com>
-+ * Jolly Shah <jollys@xilinx.com>
-+ * Rajan Vaja <rajanv@xilinx.com>
-+ */
-+
-+#include <linux/compiler.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/debugfs.h>
-+#include <linux/uaccess.h>
-+
-+#include <linux/firmware/xlnx-zynqmp.h>
-+#include "zynqmp-debug.h"
-+
-+#define PM_API_NAME_LEN 50
-+
-+struct pm_api_info {
-+ u32 api_id;
-+ char api_name[PM_API_NAME_LEN];
-+ char api_name_len;
-+};
-+
-+static char debugfs_buf[PAGE_SIZE];
-+
-+#define PM_API(id) {id, #id, strlen(#id)}
-+static struct pm_api_info pm_api_list[] = {
-+ PM_API(PM_GET_API_VERSION),
-+};
-+
-+/**
-+ * zynqmp_pm_argument_value() - Extract argument value from a PM-API request
-+ * @arg: Entered PM-API argument in string format
-+ *
-+ * Return: Argument value in unsigned integer format on success
-+ * 0 otherwise
-+ */
-+static u64 zynqmp_pm_argument_value(char *arg)
-+{
-+ u64 value;
-+
-+ if (!arg)
-+ return 0;
-+
-+ if (!kstrtou64(arg, 0, &value))
-+ return value;
-+
-+ return 0;
-+}
-+
-+/**
-+ * get_pm_api_id() - Extract API-ID from a PM-API request
-+ * @pm_api_req: Entered PM-API argument in string format
-+ * @pm_id: API-ID
-+ *
-+ * Return: 0 on success else error code
-+ */
-+static int get_pm_api_id(char *pm_api_req, u32 *pm_id)
-+{
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(pm_api_list) ; i++) {
-+ if (!strncasecmp(pm_api_req, pm_api_list[i].api_name,
-+ pm_api_list[i].api_name_len)) {
-+ *pm_id = pm_api_list[i].api_id;
-+ break;
-+ }
-+ }
-+
-+ /* If no name was entered look for PM-API ID instead */
-+ if (i == ARRAY_SIZE(pm_api_list) && kstrtouint(pm_api_req, 10, pm_id))
-+ return -EINVAL;
-+
-+ return 0;
-+}
-+
-+static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret)
-+{
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+ u32 pm_api_version;
-+ int ret;
-+
-+ if (!eemi_ops)
-+ return -ENXIO;
-+
-+ switch (pm_id) {
-+ case PM_GET_API_VERSION:
-+ ret = eemi_ops->get_api_version(&pm_api_version);
-+ sprintf(debugfs_buf, "PM-API Version = %d.%d\n",
-+ pm_api_version >> 16, pm_api_version & 0xffff);
-+ break;
-+ default:
-+ sprintf(debugfs_buf, "Unsupported PM-API request\n");
-+ ret = -EINVAL;
-+ }
-+
-+ return ret;
-+}
-+
-+/**
-+ * zynqmp_pm_debugfs_api_write() - debugfs write function
-+ * @file: User file
-+ * @ptr: User entered PM-API string
-+ * @len: Length of the userspace buffer
-+ * @off: Offset within the file
-+ *
-+ * Used for triggering pm api functions by writing
-+ * echo <pm_api_id> > /sys/kernel/debug/zynqmp_pm/power or
-+ * echo <pm_api_name> > /sys/kernel/debug/zynqmp_pm/power
-+ *
-+ * Return: Number of bytes copied if PM-API request succeeds,
-+ * the corresponding error code otherwise
-+ */
-+static ssize_t zynqmp_pm_debugfs_api_write(struct file *file,
-+ const char __user *ptr, size_t len,
-+ loff_t *off)
-+{
-+ char *kern_buff, *tmp_buff;
-+ char *pm_api_req;
-+ u32 pm_id = 0;
-+ u64 pm_api_arg[4] = {0, 0, 0, 0};
-+ /* Return values from PM APIs calls */
-+ u32 pm_api_ret[4] = {0, 0, 0, 0};
-+
-+ int ret;
-+ int i = 0;
-+
-+ strcpy(debugfs_buf, "");
-+
-+ if (*off != 0 || len == 0)
-+ return -EINVAL;
-+
-+ kern_buff = kzalloc(len, GFP_KERNEL);
-+ if (!kern_buff)
-+ return -ENOMEM;
-+
-+ tmp_buff = kern_buff;
-+
-+ ret = strncpy_from_user(kern_buff, ptr, len);
-+ if (ret < 0) {
-+ ret = -EFAULT;
-+ goto err;
-+ }
-+
-+ /* Read the API name from a user request */
-+ pm_api_req = strsep(&kern_buff, " ");
-+
-+ ret = get_pm_api_id(pm_api_req, &pm_id);
-+ if (ret < 0)
-+ goto err;
-+
-+ /* Read node_id and arguments from the PM-API request */
-+ pm_api_req = strsep(&kern_buff, " ");
-+ while ((i < ARRAY_SIZE(pm_api_arg)) && pm_api_req) {
-+ pm_api_arg[i++] = zynqmp_pm_argument_value(pm_api_req);
-+ pm_api_req = strsep(&kern_buff, " ");
-+ }
-+
-+ ret = process_api_request(pm_id, pm_api_arg, pm_api_ret);
-+
-+err:
-+ kfree(tmp_buff);
-+ if (ret)
-+ return ret;
-+
-+ return len;
-+}
-+
-+/**
-+ * zynqmp_pm_debugfs_api_read() - debugfs read function
-+ * @file: User file
-+ * @ptr: Requested pm_api_version string
-+ * @len: Length of the userspace buffer
-+ * @off: Offset within the file
-+ *
-+ * Return: Length of the version string on success
-+ * else error code
-+ */
-+static ssize_t zynqmp_pm_debugfs_api_read(struct file *file, char __user *ptr,
-+ size_t len, loff_t *off)
-+{
-+ return simple_read_from_buffer(ptr, len, off, debugfs_buf,
-+ strlen(debugfs_buf));
-+}
-+
-+/* Setup debugfs fops */
-+static const struct file_operations fops_zynqmp_pm_dbgfs = {
-+ .owner = THIS_MODULE,
-+ .write = zynqmp_pm_debugfs_api_write,
-+ .read = zynqmp_pm_debugfs_api_read,
-+};
-+
-+/**
-+ * zynqmp_pm_api_debugfs_init - Initialize debugfs interface
-+ *
-+ * Return: None
-+ */
-+void zynqmp_pm_api_debugfs_init(void)
-+{
-+ struct dentry *root_dir;
-+
-+ /* Initialize debugfs interface */
-+ root_dir = debugfs_create_dir("zynqmp-firmware", NULL);
-+ debugfs_create_file("pm", 0660, root_dir, NULL,
-+ &fops_zynqmp_pm_dbgfs);
-+}
-diff --git a/drivers/firmware/xilinx/zynqmp-debug.h b/drivers/firmware/xilinx/zynqmp-debug.h
-new file mode 100644
-index 0000000..3303b37
---- /dev/null
-+++ b/drivers/firmware/xilinx/zynqmp-debug.h
-@@ -0,0 +1,22 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Xilinx Zynq MPSoC Firmware layer
-+ *
-+ * Copyright (C) 2014-2018 Xilinx
-+ *
-+ * Michal Simek <michal.simek@xilinx.com>
-+ * Davorin Mista <davorin.mista@aggios.com>
-+ * Jolly Shah <jollys@xilinx.com>
-+ * Rajan Vaja <rajanv@xilinx.com>
-+ */
-+
-+#ifndef __FIRMWARE_ZYNQMP_DEBUG_H__
-+#define __FIRMWARE_ZYNQMP_DEBUG_H__
-+
-+#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE_DEBUG)
-+void zynqmp_pm_api_debugfs_init(void);
-+#else
-+static inline void zynqmp_pm_api_debugfs_init(void) { }
-+#endif
-+
-+#endif /* __FIRMWARE_ZYNQMP_DEBUG_H__ */
-diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
-index 41ed800..7ccedf0 100644
---- a/drivers/firmware/xilinx/zynqmp.c
-+++ b/drivers/firmware/xilinx/zynqmp.c
-@@ -21,6 +21,7 @@
- #include <linux/uaccess.h>
-
- #include <linux/firmware/xlnx-zynqmp.h>
-+#include "zynqmp-debug.h"
-
- /**
- * zynqmp_pm_ret_code() - Convert PMU-FW error codes to Linux error codes
-@@ -551,3 +552,11 @@ static int __init zynqmp_plat_init(void)
- return ret;
- }
- early_initcall(zynqmp_plat_init);
-+
-+static int zynqmp_firmware_init(void)
-+{
-+ zynqmp_pm_api_debugfs_init();
-+
-+ return 0;
-+}
-+device_initcall(zynqmp_firmware_init);
-
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-Subject: [PATCH v11 07/11] firmware: xilinx: Add debugfs for IOCTL API
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-From: Rajan Vaja <rajanv@xilinx.com>
-
-Add debugfs file to set/get IOCTL using debugfs interface.
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
----
- drivers/firmware/xilinx/zynqmp-debug.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/firmware/xilinx/zynqmp-debug.c b/drivers/firmware/xilinx/zynqmp-debug.c
-index fcbdd6e..fc11db9 100644
---- a/drivers/firmware/xilinx/zynqmp-debug.c
-+++ b/drivers/firmware/xilinx/zynqmp-debug.c
-@@ -32,6 +32,7 @@ static char debugfs_buf[PAGE_SIZE];
- #define PM_API(id) {id, #id, strlen(#id)}
- static struct pm_api_info pm_api_list[] = {
- PM_API(PM_GET_API_VERSION),
-+ PM_API(PM_IOCTL),
- };
-
- /**
-@@ -95,6 +96,15 @@ static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret)
- sprintf(debugfs_buf, "PM-API Version = %d.%d\n",
- pm_api_version >> 16, pm_api_version & 0xffff);
- break;
-+ case PM_IOCTL:
-+ ret = eemi_ops->ioctl(pm_api_arg[0], pm_api_arg[1],
-+ pm_api_arg[2], pm_api_arg[3],
-+ &pm_api_ret[0]);
-+ if (!ret && (pm_api_arg[1] == IOCTL_GET_PLL_FRAC_MODE ||
-+ pm_api_arg[1] == IOCTL_GET_PLL_FRAC_DATA))
-+ sprintf(debugfs_buf, "IOCTL return value: %u\n",
-+ pm_api_ret[1]);
-+ break;
- default:
- sprintf(debugfs_buf, "Unsupported PM-API request\n");
- ret = -EINVAL;
-
-From patchwork Fri Aug 3 17:53:25 2018
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-To: <ard.biesheuvel@linaro.org>, <mingo@kernel.org>,
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-Subject: [PATCH v11 08/11] firmware: xilinx: Add debugfs for query data API
-Date: Fri, 3 Aug 2018 10:53:25 -0700
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-Cc: devicetree@vger.kernel.org, rajanv@xilinx.com,
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-From: Rajan Vaja <rajanv@xilinx.com>
-
-Add debugfs file to query platform specific data from firmware
-using debugfs interface.
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
----
- drivers/firmware/xilinx/zynqmp-debug.c | 27 +++++++++++++++++++++++++++
- 1 file changed, 27 insertions(+)
-
-diff --git a/drivers/firmware/xilinx/zynqmp-debug.c b/drivers/firmware/xilinx/zynqmp-debug.c
-index fc11db9..4532bd0 100644
---- a/drivers/firmware/xilinx/zynqmp-debug.c
-+++ b/drivers/firmware/xilinx/zynqmp-debug.c
-@@ -33,6 +33,7 @@ static char debugfs_buf[PAGE_SIZE];
- static struct pm_api_info pm_api_list[] = {
- PM_API(PM_GET_API_VERSION),
- PM_API(PM_IOCTL),
-+ PM_API(PM_QUERY_DATA),
- };
-
- /**
-@@ -105,6 +106,32 @@ static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret)
- sprintf(debugfs_buf, "IOCTL return value: %u\n",
- pm_api_ret[1]);
- break;
-+ case PM_QUERY_DATA:
-+ {
-+ struct zynqmp_pm_query_data qdata = {0};
-+
-+ qdata.qid = pm_api_arg[0];
-+ qdata.arg1 = pm_api_arg[1];
-+ qdata.arg2 = pm_api_arg[2];
-+ qdata.arg3 = pm_api_arg[3];
-+
-+ ret = eemi_ops->query_data(qdata, pm_api_ret);
-+ if (ret)
-+ break;
-+
-+ if (qdata.qid == PM_QID_CLOCK_GET_NAME)
-+ sprintf(debugfs_buf, "Clock name = %s\n",
-+ (char *)pm_api_ret);
-+ else if (qdata.qid == PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS)
-+ sprintf(debugfs_buf, "Multiplier = %d, Divider = %d\n",
-+ pm_api_ret[1], pm_api_ret[2]);
-+ else
-+ sprintf(debugfs_buf,
-+ "data[0] = 0x%08x\ndata[1] = 0x%08x\n data[2] = 0x%08x\ndata[3] = 0x%08x\n",
-+ pm_api_ret[0], pm_api_ret[1],
-+ pm_api_ret[2], pm_api_ret[3]);
-+ break;
-+ }
- default:
- sprintf(debugfs_buf, "Unsupported PM-API request\n");
- ret = -EINVAL;
-
-From patchwork Fri Aug 3 17:53:26 2018
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-From: Jolly Shah <jolly.shah@xilinx.com>
-To: <ard.biesheuvel@linaro.org>, <mingo@kernel.org>,
- <gregkh@linuxfoundation.org>, <matt@codeblueprint.co.uk>,
- <sudeep.holla@arm.com>, <hkallweit1@gmail.com>, <keescook@chromium.org>,
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-Subject: [PATCH v11 09/11] dt-bindings: clock: Add bindings for ZynqMP clock
- driver
-Date: Fri, 3 Aug 2018 10:53:26 -0700
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-Cc: devicetree@vger.kernel.org, rajanv@xilinx.com,
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-From: Rajan Vaja <rajanv@xilinx.com>
-
-Add documentation to describe Xilinx ZynqMP clock driver
-bindings.
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
----
- .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 53 ++++++++++
- include/dt-bindings/clock/xlnx,zynqmp-clk.h | 116 +++++++++++++++++++++
- 2 files changed, 169 insertions(+)
- create mode 100644 include/dt-bindings/clock/xlnx,zynqmp-clk.h
-
-diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
-index 1b431d9..d215d15 100644
---- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
-+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
-@@ -17,6 +17,53 @@ Required properties:
- - "smc" : SMC #0, following the SMCCC
- - "hvc" : HVC #0, following the SMCCC
-
-+--------------------------------------------------------------------------
-+Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
-+Zynq MPSoC firmware interface
-+--------------------------------------------------------------------------
-+The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
-+tree. It reads required input clock frequencies from the devicetree and acts
-+as clock provider for all clock consumers of PS clocks.
-+
-+See clock_bindings.txt for more information on the generic clock bindings.
-+
-+Required properties:
-+ - #clock-cells: Must be 1
-+ - compatible: Must contain: "xlnx,zynqmp-clk"
-+ - clocks: List of clock specifiers which are external input
-+ clocks to the given clock controller. Please refer
-+ the next section to find the input clocks for a
-+ given controller.
-+ - clock-names: List of clock names which are exteral input clocks
-+ to the given clock controller. Please refer to the
-+ clock bindings for more details.
-+
-+Input clocks for zynqmp Ultrascale+ clock controller:
-+
-+The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
-+inputs. These required clock inputs are:
-+ - pss_ref_clk (PS reference clock)
-+ - video_clk (reference clock for video system )
-+ - pss_alt_ref_clk (alternative PS reference clock)
-+ - aux_ref_clk
-+ - gt_crx_ref_clk (transceiver reference clock)
-+
-+The following strings are optional parameters to the 'clock-names' property in
-+order to provide an optional (E)MIO clock source:
-+ - swdt0_ext_clk
-+ - swdt1_ext_clk
-+ - gem0_emio_clk
-+ - gem1_emio_clk
-+ - gem2_emio_clk
-+ - gem3_emio_clk
-+ - mio_clk_XX # with XX = 00..77
-+ - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
-+
-+
-+Output clocks are registered based on clock information received
-+from firmware. Output clocks indexes are mentioned in
-+include/dt-bindings/clock/xlnx,zynqmp-clk.h.
-+
- -------
- Example
- -------
-@@ -25,5 +72,11 @@ firmware {
- zynqmp_firmware: zynqmp-firmware {
- compatible = "xlnx,zynqmp-firmware";
- method = "smc";
-+ zynqmp_clk : clock-controller {
-+ #clock-cells = <1>;
-+ compatible = "xlnx,zynqmp-clk";
-+ clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
-+ clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
-+ };
- };
- };
-diff --git a/include/dt-bindings/clock/xlnx,zynqmp-clk.h b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
-new file mode 100644
-index 0000000..4aebe6e
---- /dev/null
-+++ b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
-@@ -0,0 +1,116 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Xilinx Zynq MPSoC Firmware layer
-+ *
-+ * Copyright (C) 2014-2018 Xilinx, Inc.
-+ *
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
-+#define _DT_BINDINGS_CLK_ZYNQMP_H
-+
-+#define IOPLL 0
-+#define RPLL 1
-+#define APLL 2
-+#define DPLL 3
-+#define VPLL 4
-+#define IOPLL_TO_FPD 5
-+#define RPLL_TO_FPD 6
-+#define APLL_TO_LPD 7
-+#define DPLL_TO_LPD 8
-+#define VPLL_TO_LPD 9
-+#define ACPU 10
-+#define ACPU_HALF 11
-+#define DBF_FPD 12
-+#define DBF_LPD 13
-+#define DBG_TRACE 14
-+#define DBG_TSTMP 15
-+#define DP_VIDEO_REF 16
-+#define DP_AUDIO_REF 17
-+#define DP_STC_REF 18
-+#define GDMA_REF 19
-+#define DPDMA_REF 20
-+#define DDR_REF 21
-+#define SATA_REF 22
-+#define PCIE_REF 23
-+#define GPU_REF 24
-+#define GPU_PP0_REF 25
-+#define GPU_PP1_REF 26
-+#define TOPSW_MAIN 27
-+#define TOPSW_LSBUS 28
-+#define GTGREF0_REF 29
-+#define LPD_SWITCH 30
-+#define LPD_LSBUS 31
-+#define USB0_BUS_REF 32
-+#define USB1_BUS_REF 33
-+#define USB3_DUAL_REF 34
-+#define USB0 35
-+#define USB1 36
-+#define CPU_R5 37
-+#define CPU_R5_CORE 38
-+#define CSU_SPB 39
-+#define CSU_PLL 40
-+#define PCAP 41
-+#define IOU_SWITCH 42
-+#define GEM_TSU_REF 43
-+#define GEM_TSU 44
-+#define GEM0_REF 45
-+#define GEM1_REF 46
-+#define GEM2_REF 47
-+#define GEM3_REF 48
-+#define GEM0_TX 49
-+#define GEM1_TX 50
-+#define GEM2_TX 51
-+#define GEM3_TX 52
-+#define QSPI_REF 53
-+#define SDIO0_REF 54
-+#define SDIO1_REF 55
-+#define UART0_REF 56
-+#define UART1_REF 57
-+#define SPI0_REF 58
-+#define SPI1_REF 59
-+#define NAND_REF 60
-+#define I2C0_REF 61
-+#define I2C1_REF 62
-+#define CAN0_REF 63
-+#define CAN1_REF 64
-+#define CAN0 65
-+#define CAN1 66
-+#define DLL_REF 67
-+#define ADMA_REF 68
-+#define TIMESTAMP_REF 69
-+#define AMS_REF 70
-+#define PL0_REF 71
-+#define PL1_REF 72
-+#define PL2_REF 73
-+#define PL3_REF 74
-+#define WDT 75
-+#define IOPLL_INT 76
-+#define IOPLL_PRE_SRC 77
-+#define IOPLL_HALF 78
-+#define IOPLL_INT_MUX 79
-+#define IOPLL_POST_SRC 80
-+#define RPLL_INT 81
-+#define RPLL_PRE_SRC 82
-+#define RPLL_HALF 83
-+#define RPLL_INT_MUX 84
-+#define RPLL_POST_SRC 85
-+#define APLL_INT 86
-+#define APLL_PRE_SRC 87
-+#define APLL_HALF 88
-+#define APLL_INT_MUX 89
-+#define APLL_POST_SRC 90
-+#define DPLL_INT 91
-+#define DPLL_PRE_SRC 92
-+#define DPLL_HALF 93
-+#define DPLL_INT_MUX 94
-+#define DPLL_POST_SRC 95
-+#define VPLL_INT 96
-+#define VPLL_PRE_SRC 97
-+#define VPLL_HALF 98
-+#define VPLL_INT_MUX 99
-+#define VPLL_POST_SRC 100
-+#define CAN0_MIO 101
-+#define CAN1_MIO 102
-+
-+#endif
-
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-Subject: [PATCH v11 10/11] drivers: clk: Add ZynqMP clock driver
-Date: Fri, 3 Aug 2018 10:53:27 -0700
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-Cc: devicetree@vger.kernel.org, Tejas Patel <tejasp@xilinx.com>,
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-From: Jolly Shah <jolly.shah@xilinx.com>
-
-This patch adds CCF compliant clock driver for ZynqMP.
-Clock driver queries supported clock information from
-firmware and regiters pll and output clocks with CCF.
-
-Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
-Signed-off-by: Tejas Patel <tejasp@xilinx.com>
-Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
----
- drivers/clk/Kconfig | 1 +
- drivers/clk/Makefile | 1 +
- drivers/clk/zynqmp/Kconfig | 10 +
- drivers/clk/zynqmp/Makefile | 4 +
- drivers/clk/zynqmp/clk-gate-zynqmp.c | 144 +++++++
- drivers/clk/zynqmp/clk-mux-zynqmp.c | 141 +++++++
- drivers/clk/zynqmp/clk-zynqmp.h | 68 ++++
- drivers/clk/zynqmp/clkc.c | 716 +++++++++++++++++++++++++++++++++++
- drivers/clk/zynqmp/divider.c | 217 +++++++++++
- drivers/clk/zynqmp/pll.c | 335 ++++++++++++++++
- include/linux/firmware/xlnx-zynqmp.h | 1 +
- 11 files changed, 1638 insertions(+)
- create mode 100644 drivers/clk/zynqmp/Kconfig
- create mode 100644 drivers/clk/zynqmp/Makefile
- create mode 100644 drivers/clk/zynqmp/clk-gate-zynqmp.c
- create mode 100644 drivers/clk/zynqmp/clk-mux-zynqmp.c
- create mode 100644 drivers/clk/zynqmp/clk-zynqmp.h
- create mode 100644 drivers/clk/zynqmp/clkc.c
- create mode 100644 drivers/clk/zynqmp/divider.c
- create mode 100644 drivers/clk/zynqmp/pll.c
-
-diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
-index 98ce9fc..ab2ea76 100644
---- a/drivers/clk/Kconfig
-+++ b/drivers/clk/Kconfig
-@@ -253,5 +253,6 @@ source "drivers/clk/sunxi-ng/Kconfig"
- source "drivers/clk/tegra/Kconfig"
- source "drivers/clk/ti/Kconfig"
- source "drivers/clk/uniphier/Kconfig"
-+source "drivers/clk/zynqmp/Kconfig"
-
- endmenu
-diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
-index 71ec41e..b6ac0d2 100644
---- a/drivers/clk/Makefile
-+++ b/drivers/clk/Makefile
-@@ -100,3 +100,4 @@ obj-$(CONFIG_X86) += x86/
- endif
- obj-$(CONFIG_ARCH_ZX) += zte/
- obj-$(CONFIG_ARCH_ZYNQ) += zynq/
-+obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
-diff --git a/drivers/clk/zynqmp/Kconfig b/drivers/clk/zynqmp/Kconfig
-new file mode 100644
-index 0000000..1708605
---- /dev/null
-+++ b/drivers/clk/zynqmp/Kconfig
-@@ -0,0 +1,10 @@
-+# SPDX-License-Identifier: GPL-2.0
-+
-+config COMMON_CLK_ZYNQMP
-+ bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
-+ depends on ARCH_ZYNQMP || COMPILE_TEST
-+ depends on ZYNQMP_FIRMWARE
-+ help
-+ Support for the Zynqmp Ultrascale clock controller.
-+ It has a dependency on the PMU firmware.
-+ Say Y if you want to include clock support.
-diff --git a/drivers/clk/zynqmp/Makefile b/drivers/clk/zynqmp/Makefile
-new file mode 100644
-index 0000000..0ec24bf
---- /dev/null
-+++ b/drivers/clk/zynqmp/Makefile
-@@ -0,0 +1,4 @@
-+# SPDX-License-Identifier: GPL-2.0
-+# Zynq Ultrascale+ MPSoC clock specific Makefile
-+
-+obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o
-diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c
-new file mode 100644
-index 0000000..83b236f
---- /dev/null
-+++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c
-@@ -0,0 +1,144 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Zynq UltraScale+ MPSoC clock controller
-+ *
-+ * Copyright (C) 2016-2018 Xilinx
-+ *
-+ * Gated clock implementation
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/slab.h>
-+#include "clk-zynqmp.h"
-+
-+/**
-+ * struct clk_gate - gating clock
-+ * @hw: handle between common and hardware-specific interfaces
-+ * @flags: hardware-specific flags
-+ * @clk_id: Id of clock
-+ */
-+struct zynqmp_clk_gate {
-+ struct clk_hw hw;
-+ u8 flags;
-+ u32 clk_id;
-+};
-+
-+#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw)
-+
-+/**
-+ * zynqmp_clk_gate_enable() - Enable clock
-+ * @hw: handle between common and hardware-specific interfaces
-+ *
-+ * Return: 0 on success else error code
-+ */
-+static int zynqmp_clk_gate_enable(struct clk_hw *hw)
-+{
-+ struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = gate->clk_id;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ ret = eemi_ops->clock_enable(clk_id);
-+
-+ if (ret)
-+ pr_warn_once("%s() clock enabled failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ return ret;
-+}
-+
-+/*
-+ * zynqmp_clk_gate_disable() - Disable clock
-+ * @hw: handle between common and hardware-specific interfaces
-+ */
-+static void zynqmp_clk_gate_disable(struct clk_hw *hw)
-+{
-+ struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = gate->clk_id;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ ret = eemi_ops->clock_disable(clk_id);
-+
-+ if (ret)
-+ pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+}
-+
-+/**
-+ * zynqmp_clk_gate_is_enable() - Check clock state
-+ * @hw: handle between common and hardware-specific interfaces
-+ *
-+ * Return: 1 if enabled, 0 if disabled else error code
-+ */
-+static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
-+{
-+ struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = gate->clk_id;
-+ int state, ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ ret = eemi_ops->clock_getstate(clk_id, &state);
-+ if (ret) {
-+ pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+ return -EIO;
-+ }
-+
-+ return state ? 1 : 0;
-+}
-+
-+static const struct clk_ops zynqmp_clk_gate_ops = {
-+ .enable = zynqmp_clk_gate_enable,
-+ .disable = zynqmp_clk_gate_disable,
-+ .is_enabled = zynqmp_clk_gate_is_enabled,
-+};
-+
-+/**
-+ * zynqmp_clk_register_gate() - Register a gate clock with the clock framework
-+ * @name: Name of this clock
-+ * @clk_id: Id of this clock
-+ * @parents: Name of this clock's parents
-+ * @num_parents: Number of parents
-+ * @nodes: Clock topology node
-+ *
-+ * Return: clock hardware of the registered clock gate
-+ */
-+struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes)
-+{
-+ struct zynqmp_clk_gate *gate;
-+ struct clk_hw *hw;
-+ int ret;
-+ struct clk_init_data init;
-+
-+ /* allocate the gate */
-+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
-+ if (!gate)
-+ return ERR_PTR(-ENOMEM);
-+
-+ init.name = name;
-+ init.ops = &zynqmp_clk_gate_ops;
-+ init.flags = nodes->flag;
-+ init.parent_names = parents;
-+ init.num_parents = 1;
-+
-+ /* struct clk_gate assignments */
-+ gate->flags = nodes->type_flag;
-+ gate->hw.init = &init;
-+ gate->clk_id = clk_id;
-+
-+ hw = &gate->hw;
-+ ret = clk_hw_register(NULL, hw);
-+ if (ret) {
-+ kfree(gate);
-+ hw = ERR_PTR(ret);
-+ }
-+
-+ return hw;
-+}
-diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
-new file mode 100644
-index 0000000..4143f56
---- /dev/null
-+++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
-@@ -0,0 +1,141 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Zynq UltraScale+ MPSoC mux
-+ *
-+ * Copyright (C) 2016-2018 Xilinx
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/slab.h>
-+#include "clk-zynqmp.h"
-+
-+/*
-+ * DOC: basic adjustable multiplexer clock that cannot gate
-+ *
-+ * Traits of this clock:
-+ * prepare - clk_prepare only ensures that parents are prepared
-+ * enable - clk_enable only ensures that parents are enabled
-+ * rate - rate is only affected by parent switching. No clk_set_rate support
-+ * parent - parent is adjustable through clk_set_parent
-+ */
-+
-+/**
-+ * struct zynqmp_clk_mux - multiplexer clock
-+ *
-+ * @hw: handle between common and hardware-specific interfaces
-+ * @flags: hardware-specific flags
-+ * @clk_id: Id of clock
-+ */
-+struct zynqmp_clk_mux {
-+ struct clk_hw hw;
-+ u8 flags;
-+ u32 clk_id;
-+};
-+
-+#define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw)
-+
-+/**
-+ * zynqmp_clk_mux_get_parent() - Get parent of clock
-+ * @hw: handle between common and hardware-specific interfaces
-+ *
-+ * Return: Parent index
-+ */
-+static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw)
-+{
-+ struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = mux->clk_id;
-+ u32 val;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ ret = eemi_ops->clock_getparent(clk_id, &val);
-+
-+ if (ret)
-+ pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ return val;
-+}
-+
-+/**
-+ * zynqmp_clk_mux_set_parent() - Set parent of clock
-+ * @hw: handle between common and hardware-specific interfaces
-+ * @index: Parent index
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
-+{
-+ struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = mux->clk_id;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ ret = eemi_ops->clock_setparent(clk_id, index);
-+
-+ if (ret)
-+ pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ return ret;
-+}
-+
-+static const struct clk_ops zynqmp_clk_mux_ops = {
-+ .get_parent = zynqmp_clk_mux_get_parent,
-+ .set_parent = zynqmp_clk_mux_set_parent,
-+ .determine_rate = __clk_mux_determine_rate,
-+};
-+
-+static const struct clk_ops zynqmp_clk_mux_ro_ops = {
-+ .get_parent = zynqmp_clk_mux_get_parent,
-+};
-+
-+/**
-+ * zynqmp_clk_register_mux() - Register a mux table with the clock
-+ * framework
-+ * @name: Name of this clock
-+ * @clk_id: Id of this clock
-+ * @parents: Name of this clock's parents
-+ * @num_parents: Number of parents
-+ * @nodes: Clock topology node
-+ *
-+ * Return: clock hardware of the registered clock mux
-+ */
-+struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes)
-+{
-+ struct zynqmp_clk_mux *mux;
-+ struct clk_hw *hw;
-+ struct clk_init_data init;
-+ int ret;
-+
-+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
-+ if (!mux)
-+ return ERR_PTR(-ENOMEM);
-+
-+ init.name = name;
-+ if (nodes->type_flag & CLK_MUX_READ_ONLY)
-+ init.ops = &zynqmp_clk_mux_ro_ops;
-+ else
-+ init.ops = &zynqmp_clk_mux_ops;
-+ init.flags = nodes->flag;
-+ init.parent_names = parents;
-+ init.num_parents = num_parents;
-+ mux->flags = nodes->type_flag;
-+ mux->hw.init = &init;
-+ mux->clk_id = clk_id;
-+
-+ hw = &mux->hw;
-+ ret = clk_hw_register(NULL, hw);
-+ if (ret) {
-+ kfree(hw);
-+ hw = ERR_PTR(ret);
-+ }
-+
-+ return hw;
-+}
-+EXPORT_SYMBOL_GPL(zynqmp_clk_register_mux);
-diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
-new file mode 100644
-index 0000000..7ab163b
---- /dev/null
-+++ b/drivers/clk/zynqmp/clk-zynqmp.h
-@@ -0,0 +1,68 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2016-2018 Xilinx
-+ */
-+
-+#ifndef __LINUX_CLK_ZYNQMP_H_
-+#define __LINUX_CLK_ZYNQMP_H_
-+
-+#include <linux/spinlock.h>
-+
-+#include <linux/firmware/xlnx-zynqmp.h>
-+
-+/* Clock APIs payload parameters */
-+#define CLK_GET_NAME_RESP_LEN 16
-+#define CLK_GET_TOPOLOGY_RESP_WORDS 3
-+#define CLK_GET_PARENTS_RESP_WORDS 3
-+#define CLK_GET_ATTR_RESP_WORDS 1
-+
-+enum topology_type {
-+ TYPE_INVALID,
-+ TYPE_MUX,
-+ TYPE_PLL,
-+ TYPE_FIXEDFACTOR,
-+ TYPE_DIV1,
-+ TYPE_DIV2,
-+ TYPE_GATE,
-+};
-+
-+/**
-+ * struct clock_topology - Clock topology
-+ * @type: Type of topology
-+ * @flag: Topology flags
-+ * @type_flag: Topology type specific flag
-+ */
-+struct clock_topology {
-+ u32 type;
-+ u32 flag;
-+ u32 type_flag;
-+};
-+
-+struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes);
-+
-+struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes);
-+
-+struct clk_hw *zynqmp_clk_register_divider(const char *name,
-+ u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes);
-+
-+struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes);
-+
-+struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
-+ u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes);
-+
-+#endif
-diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
-new file mode 100644
-index 0000000..1b07d77
---- /dev/null
-+++ b/drivers/clk/zynqmp/clkc.c
-@@ -0,0 +1,716 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Zynq UltraScale+ MPSoC clock controller
-+ *
-+ * Copyright (C) 2016-2018 Xilinx
-+ *
-+ * Based on drivers/clk/zynq/clkc.c
-+ */
-+
-+#include <linux/bitfield.h>
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/slab.h>
-+#include <linux/string.h>
-+
-+#include "clk-zynqmp.h"
-+
-+#define MAX_PARENT 100
-+#define MAX_NODES 6
-+#define MAX_NAME_LEN 50
-+
-+#define CLK_TYPE_SHIFT 2
-+
-+#define PM_API_PAYLOAD_LEN 3
-+
-+#define NA_PARENT 0xFFFFFFFF
-+#define DUMMY_PARENT 0xFFFFFFFE
-+
-+#define CLK_TYPE_FIELD_LEN 4
-+#define CLK_TOPOLOGY_NODE_OFFSET 16
-+#define NODES_PER_RESP 3
-+
-+#define CLK_TYPE_FIELD_MASK 0xF
-+#define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
-+#define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
-+
-+#define CLK_PARENTS_ID_LEN 16
-+#define CLK_PARENTS_ID_MASK 0xFFFF
-+
-+/* Flags for parents */
-+#define PARENT_CLK_SELF 0
-+#define PARENT_CLK_NODE1 1
-+#define PARENT_CLK_NODE2 2
-+#define PARENT_CLK_NODE3 3
-+#define PARENT_CLK_NODE4 4
-+#define PARENT_CLK_EXTERNAL 5
-+
-+#define END_OF_CLK_NAME "END_OF_CLK"
-+#define END_OF_TOPOLOGY_NODE 1
-+#define END_OF_PARENTS 1
-+#define RESERVED_CLK_NAME ""
-+
-+#define CLK_VALID_MASK 0x1
-+
-+enum clk_type {
-+ CLK_TYPE_OUTPUT,
-+ CLK_TYPE_EXTERNAL,
-+};
-+
-+/**
-+ * struct clock_parent - Clock parent
-+ * @name: Parent name
-+ * @id: Parent clock ID
-+ * @flag: Parent flags
-+ */
-+struct clock_parent {
-+ char name[MAX_NAME_LEN];
-+ int id;
-+ u32 flag;
-+};
-+
-+/**
-+ * struct zynqmp_clock - Clock
-+ * @clk_name: Clock name
-+ * @valid: Validity flag of clock
-+ * @type: Clock type (Output/External)
-+ * @node: Clock topology nodes
-+ * @num_nodes: Number of nodes present in topology
-+ * @parent: Parent of clock
-+ * @num_parents: Number of parents of clock
-+ */
-+struct zynqmp_clock {
-+ char clk_name[MAX_NAME_LEN];
-+ u32 valid;
-+ enum clk_type type;
-+ struct clock_topology node[MAX_NODES];
-+ u32 num_nodes;
-+ struct clock_parent parent[MAX_PARENT];
-+ u32 num_parents;
-+};
-+
-+static const char clk_type_postfix[][10] = {
-+ [TYPE_INVALID] = "",
-+ [TYPE_MUX] = "_mux",
-+ [TYPE_GATE] = "",
-+ [TYPE_DIV1] = "_div1",
-+ [TYPE_DIV2] = "_div2",
-+ [TYPE_FIXEDFACTOR] = "_ff",
-+ [TYPE_PLL] = ""
-+};
-+
-+static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes)
-+ = {
-+ [TYPE_INVALID] = NULL,
-+ [TYPE_MUX] = zynqmp_clk_register_mux,
-+ [TYPE_PLL] = zynqmp_clk_register_pll,
-+ [TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor,
-+ [TYPE_DIV1] = zynqmp_clk_register_divider,
-+ [TYPE_DIV2] = zynqmp_clk_register_divider,
-+ [TYPE_GATE] = zynqmp_clk_register_gate
-+};
-+
-+static struct zynqmp_clock *clock;
-+static struct clk_hw_onecell_data *zynqmp_data;
-+static unsigned int clock_max_idx;
-+static const struct zynqmp_eemi_ops *eemi_ops;
-+
-+/**
-+ * zynqmp_is_valid_clock() - Check whether clock is valid or not
-+ * @clk_id: Clock index
-+ *
-+ * Return: 1 if clock is valid, 0 if clock is invalid else error code
-+ */
-+static inline int zynqmp_is_valid_clock(u32 clk_id)
-+{
-+ if (clk_id > clock_max_idx)
-+ return -ENODEV;
-+
-+ return clock[clk_id].valid;
-+}
-+
-+/**
-+ * zynqmp_get_clock_name() - Get name of clock from Clock index
-+ * @clk_id: Clock index
-+ * @clk_name: Name of clock
-+ *
-+ * Return: 0 on success else error code
-+ */
-+static int zynqmp_get_clock_name(u32 clk_id, char *clk_name)
-+{
-+ int ret;
-+
-+ ret = zynqmp_is_valid_clock(clk_id);
-+ if (ret == 1) {
-+ strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
-+ return 0;
-+ }
-+
-+ return ret == 0 ? -EINVAL : ret;
-+}
-+
-+/**
-+ * zynqmp_get_clock_type() - Get type of clock
-+ * @clk_id: Clock index
-+ * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL
-+ *
-+ * Return: 0 on success else error code
-+ */
-+static int zynqmp_get_clock_type(u32 clk_id, u32 *type)
-+{
-+ int ret;
-+
-+ ret = zynqmp_is_valid_clock(clk_id);
-+ if (ret == 1) {
-+ *type = clock[clk_id].type;
-+ return 0;
-+ }
-+
-+ return ret == 0 ? -EINVAL : ret;
-+}
-+
-+/**
-+ * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
-+ * @nclocks: Number of clocks in system/board.
-+ *
-+ * Call firmware API to get number of clocks.
-+ *
-+ * Return: 0 on success else error code.
-+ */
-+static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks)
-+{
-+ struct zynqmp_pm_query_data qdata = {0};
-+ __le32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
-+
-+ ret = eemi_ops->query_data(qdata, ret_payload);
-+ *nclocks = ret_payload[1];
-+
-+ return ret;
-+}
-+
-+/**
-+ * zynqmp_pm_clock_get_name() - Get the name of clock for given id
-+ * @clock_id: ID of the clock to be queried
-+ * @name: Name of given clock
-+ *
-+ * This function is used to get name of clock specified by given
-+ * clock ID.
-+ *
-+ * Return: Returns 0, in case of error name would be 0
-+ */
-+static int zynqmp_pm_clock_get_name(u32 clock_id, char *name)
-+{
-+ struct zynqmp_pm_query_data qdata = {0};
-+ __le32 ret_payload[PAYLOAD_ARG_CNT];
-+
-+ qdata.qid = PM_QID_CLOCK_GET_NAME;
-+ qdata.arg1 = clock_id;
-+
-+ eemi_ops->query_data(qdata, ret_payload);
-+ memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
-+
-+ return 0;
-+}
-+
-+/**
-+ * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
-+ * @clock_id: ID of the clock to be queried
-+ * @index: Node index of clock topology
-+ * @topology: Buffer to store nodes in topology and flags
-+ *
-+ * This function is used to get topology information for the clock
-+ * specified by given clock ID.
-+ *
-+ * This API will return 3 node of topology with a single response. To get
-+ * other nodes, master should call same API in loop with new
-+ * index till error is returned. E.g First call should have
-+ * index 0 which will return nodes 0,1 and 2. Next call, index
-+ * should be 3 which will return nodes 3,4 and 5 and so on.
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
-+{
-+ struct zynqmp_pm_query_data qdata = {0};
-+ __le32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
-+ qdata.arg1 = clock_id;
-+ qdata.arg2 = index;
-+
-+ ret = eemi_ops->query_data(qdata, ret_payload);
-+ memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
-+
-+ return ret;
-+}
-+
-+/**
-+ * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
-+ * clock framework
-+ * @name: Name of this clock
-+ * @clk_id: Clock ID
-+ * @parents: Name of this clock's parents
-+ * @num_parents: Number of parents
-+ * @nodes: Clock topology node
-+ *
-+ * Return: clock hardware to the registered clock
-+ */
-+struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes)
-+{
-+ u32 mult, div;
-+ struct clk_hw *hw;
-+ struct zynqmp_pm_query_data qdata = {0};
-+ __le32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
-+ qdata.arg1 = clk_id;
-+
-+ ret = eemi_ops->query_data(qdata, ret_payload);
-+ mult = ret_payload[1];
-+ div = ret_payload[2];
-+
-+ hw = clk_hw_register_fixed_factor(NULL, name,
-+ parents[0],
-+ nodes->flag, mult,
-+ div);
-+
-+ return hw;
-+}
-+
-+/**
-+ * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
-+ * @clock_id: Clock ID
-+ * @index: Parent index
-+ * @parents: 3 parents of the given clock
-+ *
-+ * This function is used to get 3 parents for the clock specified by
-+ * given clock ID.
-+ *
-+ * This API will return 3 parents with a single response. To get
-+ * other parents, master should call same API in loop with new
-+ * parent index till error is returned. E.g First call should have
-+ * index 0 which will return parents 0,1 and 2. Next call, index
-+ * should be 3 which will return parent 3,4 and 5 and so on.
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
-+{
-+ struct zynqmp_pm_query_data qdata = {0};
-+ __le32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ qdata.qid = PM_QID_CLOCK_GET_PARENTS;
-+ qdata.arg1 = clock_id;
-+ qdata.arg2 = index;
-+
-+ ret = eemi_ops->query_data(qdata, ret_payload);
-+ memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
-+
-+ return ret;
-+}
-+
-+/**
-+ * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
-+ * @clock_id: Clock ID
-+ * @attr: Clock attributes
-+ *
-+ * This function is used to get clock's attributes(e.g. valid, clock type, etc).
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int zynqmp_pm_clock_get_attributes(u32 clock_id, u32 *attr)
-+{
-+ struct zynqmp_pm_query_data qdata = {0};
-+ __le32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+
-+ qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
-+ qdata.arg1 = clock_id;
-+
-+ ret = eemi_ops->query_data(qdata, ret_payload);
-+ memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
-+
-+ return ret;
-+}
-+
-+/**
-+ * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
-+ * response data
-+ * @topology: Clock topology
-+ * @data: Clock topology data received from firmware
-+ * @nnodes: Number of nodes
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int __zynqmp_clock_get_topology(struct clock_topology *topology,
-+ u32 *data, u32 *nnodes)
-+{
-+ int i;
-+
-+ for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
-+ if (!(data[i] & CLK_TYPE_FIELD_MASK))
-+ return END_OF_TOPOLOGY_NODE;
-+ topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
-+ topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
-+ data[i]);
-+ topology[*nnodes].type_flag =
-+ FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
-+ (*nnodes)++;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * zynqmp_clock_get_topology() - Get topology of clock from firmware using
-+ * PM_API
-+ * @clk_id: Clock index
-+ * @topology: Clock topology
-+ * @num_nodes: Number of nodes
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int zynqmp_clock_get_topology(u32 clk_id,
-+ struct clock_topology *topology,
-+ u32 *num_nodes)
-+{
-+ int j, ret;
-+ u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
-+
-+ *num_nodes = 0;
-+ for (j = 0; j <= MAX_NODES; j += 3) {
-+ ret = zynqmp_pm_clock_get_topology(clk_id, j, pm_resp);
-+ if (ret)
-+ return ret;
-+ ret = __zynqmp_clock_get_topology(topology, pm_resp, num_nodes);
-+ if (ret == END_OF_TOPOLOGY_NODE)
-+ return 0;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * __zynqmp_clock_get_topology() - Get parents info of clock from firmware
-+ * response data
-+ * @parents: Clock parents
-+ * @data: Clock parents data received from firmware
-+ * @nparent: Number of parent
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int __zynqmp_clock_get_parents(struct clock_parent *parents, u32 *data,
-+ u32 *nparent)
-+{
-+ int i;
-+ struct clock_parent *parent;
-+
-+ for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
-+ if (data[i] == NA_PARENT)
-+ return END_OF_PARENTS;
-+
-+ parent = &parents[i];
-+ parent->id = data[i] & CLK_PARENTS_ID_MASK;
-+ if (data[i] == DUMMY_PARENT) {
-+ strcpy(parent->name, "dummy_name");
-+ parent->flag = 0;
-+ } else {
-+ parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
-+ if (zynqmp_get_clock_name(parent->id, parent->name))
-+ continue;
-+ }
-+ *nparent += 1;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
-+ * @clk_id: Clock index
-+ * @parents: Clock parents
-+ * @num_parents: Total number of parents
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents,
-+ u32 *num_parents)
-+{
-+ int j = 0, ret;
-+ u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
-+
-+ *num_parents = 0;
-+ do {
-+ /* Get parents from firmware */
-+ ret = zynqmp_pm_clock_get_parents(clk_id, j, pm_resp);
-+ if (ret)
-+ return ret;
-+
-+ ret = __zynqmp_clock_get_parents(&parents[j], pm_resp,
-+ num_parents);
-+ if (ret == END_OF_PARENTS)
-+ return 0;
-+ j += PM_API_PAYLOAD_LEN;
-+ } while (*num_parents <= MAX_PARENT);
-+
-+ return 0;
-+}
-+
-+/**
-+ * zynqmp_get_parent_list() - Create list of parents name
-+ * @np: Device node
-+ * @clk_id: Clock index
-+ * @parent_list: List of parent's name
-+ * @num_parents: Total number of parents
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id,
-+ const char **parent_list, u32 *num_parents)
-+{
-+ int i = 0, ret;
-+ u32 total_parents = clock[clk_id].num_parents;
-+ struct clock_topology *clk_nodes;
-+ struct clock_parent *parents;
-+
-+ clk_nodes = clock[clk_id].node;
-+ parents = clock[clk_id].parent;
-+
-+ for (i = 0; i < total_parents; i++) {
-+ if (!parents[i].flag) {
-+ parent_list[i] = parents[i].name;
-+ } else if (parents[i].flag == PARENT_CLK_EXTERNAL) {
-+ ret = of_property_match_string(np, "clock-names",
-+ parents[i].name);
-+ if (ret < 0)
-+ strcpy(parents[i].name, "dummy_name");
-+ parent_list[i] = parents[i].name;
-+ } else {
-+ strcat(parents[i].name,
-+ clk_type_postfix[clk_nodes[parents[i].flag - 1].
-+ type]);
-+ parent_list[i] = parents[i].name;
-+ }
-+ }
-+
-+ *num_parents = total_parents;
-+ return 0;
-+}
-+
-+/**
-+ * zynqmp_register_clk_topology() - Register clock topology
-+ * @clk_id: Clock index
-+ * @clk_name: Clock Name
-+ * @num_parents: Total number of parents
-+ * @parent_names: List of parents name
-+ *
-+ * Return: Returns either clock hardware or error+reason
-+ */
-+static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
-+ int num_parents,
-+ const char **parent_names)
-+{
-+ int j;
-+ u32 num_nodes;
-+ char *clk_out = NULL;
-+ struct clock_topology *nodes;
-+ struct clk_hw *hw = NULL;
-+
-+ nodes = clock[clk_id].node;
-+ num_nodes = clock[clk_id].num_nodes;
-+
-+ for (j = 0; j < num_nodes; j++) {
-+ /*
-+ * Clock name received from firmware is output clock name.
-+ * Intermediate clock names are postfixed with type of clock.
-+ */
-+ if (j != (num_nodes - 1)) {
-+ clk_out = kasprintf(GFP_KERNEL, "%s%s", clk_name,
-+ clk_type_postfix[nodes[j].type]);
-+ } else {
-+ clk_out = kasprintf(GFP_KERNEL, "%s", clk_name);
-+ }
-+
-+ if (!clk_topology[nodes[j].type])
-+ continue;
-+
-+ hw = (*clk_topology[nodes[j].type])(clk_out, clk_id,
-+ parent_names,
-+ num_parents,
-+ &nodes[j]);
-+ if (IS_ERR(hw))
-+ pr_warn_once("%s() %s register fail with %ld\n",
-+ __func__, clk_name, PTR_ERR(hw));
-+
-+ parent_names[0] = clk_out;
-+ }
-+ kfree(clk_out);
-+ return hw;
-+}
-+
-+/**
-+ * zynqmp_register_clocks() - Register clocks
-+ * @np: Device node
-+ *
-+ * Return: 0 on success else error code
-+ */
-+static int zynqmp_register_clocks(struct device_node *np)
-+{
-+ int ret;
-+ u32 i, total_parents = 0, type = 0;
-+ const char *parent_names[MAX_PARENT];
-+
-+ for (i = 0; i < clock_max_idx; i++) {
-+ char clk_name[MAX_NAME_LEN];
-+
-+ /* get clock name, continue to next clock if name not found */
-+ if (zynqmp_get_clock_name(i, clk_name))
-+ continue;
-+
-+ /* Check if clock is valid and output clock.
-+ * Do not register invalid or external clock.
-+ */
-+ ret = zynqmp_get_clock_type(i, &type);
-+ if (ret || type != CLK_TYPE_OUTPUT)
-+ continue;
-+
-+ /* Get parents of clock*/
-+ if (zynqmp_get_parent_list(np, i, parent_names,
-+ &total_parents)) {
-+ WARN_ONCE(1, "No parents found for %s\n",
-+ clock[i].clk_name);
-+ continue;
-+ }
-+
-+ zynqmp_data->hws[i] =
-+ zynqmp_register_clk_topology(i, clk_name,
-+ total_parents,
-+ parent_names);
-+ }
-+
-+ for (i = 0; i < clock_max_idx; i++) {
-+ if (IS_ERR(zynqmp_data->hws[i])) {
-+ pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n",
-+ clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));
-+ WARN_ON(1);
-+ }
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
-+ */
-+static void zynqmp_get_clock_info(void)
-+{
-+ int i, ret;
-+ u32 attr, type = 0;
-+
-+ for (i = 0; i < clock_max_idx; i++) {
-+ zynqmp_pm_clock_get_name(i, clock[i].clk_name);
-+ if (!strcmp(clock[i].clk_name, RESERVED_CLK_NAME))
-+ continue;
-+
-+ ret = zynqmp_pm_clock_get_attributes(i, &attr);
-+ if (ret)
-+ continue;
-+
-+ clock[i].valid = attr & CLK_VALID_MASK;
-+ clock[i].type = attr >> CLK_TYPE_SHIFT ? CLK_TYPE_EXTERNAL :
-+ CLK_TYPE_OUTPUT;
-+ }
-+
-+ /* Get topology of all clock */
-+ for (i = 0; i < clock_max_idx; i++) {
-+ ret = zynqmp_get_clock_type(i, &type);
-+ if (ret || type != CLK_TYPE_OUTPUT)
-+ continue;
-+
-+ ret = zynqmp_clock_get_topology(i, clock[i].node,
-+ &clock[i].num_nodes);
-+ if (ret)
-+ continue;
-+
-+ ret = zynqmp_clock_get_parents(i, clock[i].parent,
-+ &clock[i].num_parents);
-+ if (ret)
-+ continue;
-+ }
-+}
-+
-+/**
-+ * zynqmp_clk_setup() - Setup the clock framework and register clocks
-+ * @np: Device node
-+ *
-+ * Return: 0 on success else error code
-+ */
-+static int zynqmp_clk_setup(struct device_node *np)
-+{
-+ int ret;
-+
-+ ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx);
-+ if (ret)
-+ return ret;
-+
-+ zynqmp_data = kzalloc(sizeof(*zynqmp_data) + sizeof(*zynqmp_data) *
-+ clock_max_idx, GFP_KERNEL);
-+ if (!zynqmp_data)
-+ return -ENOMEM;
-+
-+ clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL);
-+ if (!clock) {
-+ kfree(zynqmp_data);
-+ return -ENOMEM;
-+ }
-+
-+ zynqmp_get_clock_info();
-+ zynqmp_register_clocks(np);
-+
-+ zynqmp_data->num = clock_max_idx;
-+ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data);
-+
-+ return 0;
-+}
-+
-+static int zynqmp_clock_probe(struct platform_device *pdev)
-+{
-+ int ret;
-+ struct device *dev = &pdev->dev;
-+
-+ eemi_ops = zynqmp_pm_get_eemi_ops();
-+ if (!eemi_ops)
-+ return -ENXIO;
-+
-+ ret = zynqmp_clk_setup(dev->of_node);
-+
-+ return ret;
-+}
-+
-+static const struct of_device_id zynqmp_clock_of_match[] = {
-+ {.compatible = "xlnx,zynqmp-clk"},
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
-+
-+static struct platform_driver zynqmp_clock_driver = {
-+ .driver = {
-+ .name = "zynqmp_clock",
-+ .of_match_table = zynqmp_clock_of_match,
-+ },
-+ .probe = zynqmp_clock_probe,
-+};
-+module_platform_driver(zynqmp_clock_driver);
-diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
-new file mode 100644
-index 0000000..a371c66
---- /dev/null
-+++ b/drivers/clk/zynqmp/divider.c
-@@ -0,0 +1,217 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Zynq UltraScale+ MPSoC Divider support
-+ *
-+ * Copyright (C) 2016-2018 Xilinx
-+ *
-+ * Adjustable divider clock implementation
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/slab.h>
-+#include "clk-zynqmp.h"
-+
-+/*
-+ * DOC: basic adjustable divider clock that cannot gate
-+ *
-+ * Traits of this clock:
-+ * prepare - clk_prepare only ensures that parents are prepared
-+ * enable - clk_enable only ensures that parents are enabled
-+ * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
-+ * parent - fixed parent. No clk_set_parent support
-+ */
-+
-+#define to_zynqmp_clk_divider(_hw) \
-+ container_of(_hw, struct zynqmp_clk_divider, hw)
-+
-+#define CLK_FRAC BIT(13) /* has a fractional parent */
-+
-+/**
-+ * struct zynqmp_clk_divider - adjustable divider clock
-+ * @hw: handle between common and hardware-specific interfaces
-+ * @flags: Hardware specific flags
-+ * @clk_id: Id of clock
-+ * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
-+ */
-+struct zynqmp_clk_divider {
-+ struct clk_hw hw;
-+ u8 flags;
-+ u32 clk_id;
-+ u32 div_type;
-+};
-+
-+static inline int zynqmp_divider_get_val(unsigned long parent_rate,
-+ unsigned long rate)
-+{
-+ return DIV_ROUND_CLOSEST(parent_rate, rate);
-+}
-+
-+/**
-+ * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
-+ * @hw: handle between common and hardware-specific interfaces
-+ * @parent_rate: rate of parent clock
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = divider->clk_id;
-+ u32 div_type = divider->div_type;
-+ u32 div, value;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ ret = eemi_ops->clock_getdivider(clk_id, &div);
-+
-+ if (ret)
-+ pr_warn_once("%s() get divider failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ if (div_type == TYPE_DIV1)
-+ value = div & 0xFFFF;
-+ else
-+ value = div >> 16;
-+
-+ return DIV_ROUND_UP_ULL(parent_rate, value);
-+}
-+
-+/**
-+ * zynqmp_clk_divider_round_rate() - Round rate of divider clock
-+ * @hw: handle between common and hardware-specific interfaces
-+ * @rate: rate of clock to be set
-+ * @prate: rate of parent clock
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
-+ unsigned long rate,
-+ unsigned long *prate)
-+{
-+ struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = divider->clk_id;
-+ u32 div_type = divider->div_type;
-+ u32 bestdiv;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ /* if read only, just return current value */
-+ if (divider->flags & CLK_DIVIDER_READ_ONLY) {
-+ ret = eemi_ops->clock_getdivider(clk_id, &bestdiv);
-+
-+ if (ret)
-+ pr_warn_once("%s() get divider failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+ if (div_type == TYPE_DIV1)
-+ bestdiv = bestdiv & 0xFFFF;
-+ else
-+ bestdiv = bestdiv >> 16;
-+
-+ return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
-+ }
-+
-+ bestdiv = zynqmp_divider_get_val(*prate, rate);
-+
-+ if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) &&
-+ (divider->flags & CLK_FRAC))
-+ bestdiv = rate % *prate ? 1 : bestdiv;
-+ *prate = rate * bestdiv;
-+
-+ return rate;
-+}
-+
-+/**
-+ * zynqmp_clk_divider_set_rate() - Set rate of divider clock
-+ * @hw: handle between common and hardware-specific interfaces
-+ * @rate: rate of clock to be set
-+ * @parent_rate: rate of parent clock
-+ *
-+ * Return: 0 on success else error+reason
-+ */
-+static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
-+ unsigned long parent_rate)
-+{
-+ struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = divider->clk_id;
-+ u32 div_type = divider->div_type;
-+ u32 value, div;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ value = zynqmp_divider_get_val(parent_rate, rate);
-+ if (div_type == TYPE_DIV1) {
-+ div = value & 0xFFFF;
-+ div |= 0xffff << 16;
-+ } else {
-+ div = 0xffff;
-+ div |= value << 16;
-+ }
-+
-+ ret = eemi_ops->clock_setdivider(clk_id, div);
-+
-+ if (ret)
-+ pr_warn_once("%s() set divider failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ return ret;
-+}
-+
-+static const struct clk_ops zynqmp_clk_divider_ops = {
-+ .recalc_rate = zynqmp_clk_divider_recalc_rate,
-+ .round_rate = zynqmp_clk_divider_round_rate,
-+ .set_rate = zynqmp_clk_divider_set_rate,
-+};
-+
-+/**
-+ * zynqmp_clk_register_divider() - Register a divider clock
-+ * @name: Name of this clock
-+ * @clk_id: Id of clock
-+ * @parents: Name of this clock's parents
-+ * @num_parents: Number of parents
-+ * @nodes: Clock topology node
-+ *
-+ * Return: clock hardware to registered clock divider
-+ */
-+struct clk_hw *zynqmp_clk_register_divider(const char *name,
-+ u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes)
-+{
-+ struct zynqmp_clk_divider *div;
-+ struct clk_hw *hw;
-+ struct clk_init_data init;
-+ int ret;
-+
-+ /* allocate the divider */
-+ div = kzalloc(sizeof(*div), GFP_KERNEL);
-+ if (!div)
-+ return ERR_PTR(-ENOMEM);
-+
-+ init.name = name;
-+ init.ops = &zynqmp_clk_divider_ops;
-+ init.flags = nodes->flag;
-+ init.parent_names = parents;
-+ init.num_parents = 1;
-+
-+ /* struct clk_divider assignments */
-+ div->flags = nodes->type_flag;
-+ div->hw.init = &init;
-+ div->clk_id = clk_id;
-+ div->div_type = nodes->type;
-+
-+ hw = &div->hw;
-+ ret = clk_hw_register(NULL, hw);
-+ if (ret) {
-+ kfree(div);
-+ hw = ERR_PTR(ret);
-+ }
-+
-+ return hw;
-+}
-+EXPORT_SYMBOL_GPL(zynqmp_clk_register_divider);
-diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
-new file mode 100644
-index 0000000..626bb5f
---- /dev/null
-+++ b/drivers/clk/zynqmp/pll.c
-@@ -0,0 +1,335 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Zynq UltraScale+ MPSoC PLL driver
-+ *
-+ * Copyright (C) 2016-2018 Xilinx
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/slab.h>
-+#include "clk-zynqmp.h"
-+
-+/**
-+ * struct zynqmp_pll - PLL clock
-+ * @hw: Handle between common and hardware-specific interfaces
-+ * @clk_id: PLL clock ID
-+ */
-+struct zynqmp_pll {
-+ struct clk_hw hw;
-+ u32 clk_id;
-+};
-+
-+#define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
-+
-+#define PLL_FBDIV_MIN 25
-+#define PLL_FBDIV_MAX 125
-+
-+#define PS_PLL_VCO_MIN 1500000000
-+#define PS_PLL_VCO_MAX 3000000000UL
-+
-+enum pll_mode {
-+ PLL_MODE_INT,
-+ PLL_MODE_FRAC,
-+};
-+
-+#define FRAC_OFFSET 0x8
-+#define PLLFCFG_FRAC_EN BIT(31)
-+#define FRAC_DIV BIT(16) /* 2^16 */
-+
-+/**
-+ * zynqmp_pll_get_mode() - Get mode of PLL
-+ * @hw: Handle between common and hardware-specific interfaces
-+ *
-+ * Return: Mode of PLL
-+ */
-+static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
-+{
-+ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
-+ u32 clk_id = clk->clk_id;
-+ const char *clk_name = clk_hw_get_name(hw);
-+ __le32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ ret = eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_MODE, clk_id, 0,
-+ ret_payload);
-+ if (ret)
-+ pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ return ret_payload[1];
-+}
-+
-+/**
-+ * zynqmp_pll_set_mode() - Set the PLL mode
-+ * @hw: Handle between common and hardware-specific interfaces
-+ * @on: Flag to determine the mode
-+ */
-+static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
-+{
-+ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
-+ u32 clk_id = clk->clk_id;
-+ const char *clk_name = clk_hw_get_name(hw);
-+ int ret;
-+ u32 mode;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ if (on)
-+ mode = PLL_MODE_FRAC;
-+ else
-+ mode = PLL_MODE_INT;
-+
-+ ret = eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode, NULL);
-+ if (ret)
-+ pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+}
-+
-+/**
-+ * zynqmp_pll_round_rate() - Round a clock frequency
-+ * @hw: Handle between common and hardware-specific interfaces
-+ * @rate: Desired clock frequency
-+ * @prate: Clock frequency of parent clock
-+ *
-+ * Return: Frequency closest to @rate the hardware can generate
-+ */
-+static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-+ unsigned long *prate)
-+{
-+ u32 fbdiv;
-+ long rate_div, f;
-+
-+ /* Enable the fractional mode if needed */
-+ rate_div = (rate * FRAC_DIV) / *prate;
-+ f = rate_div % FRAC_DIV;
-+ zynqmp_pll_set_mode(hw, !!f);
-+
-+ if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
-+ if (rate > PS_PLL_VCO_MAX) {
-+ fbdiv = rate / PS_PLL_VCO_MAX;
-+ rate = rate / (fbdiv + 1);
-+ }
-+ if (rate < PS_PLL_VCO_MIN) {
-+ fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
-+ rate = rate * fbdiv;
-+ }
-+ return rate;
-+ }
-+
-+ fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
-+ fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
-+ return *prate * fbdiv;
-+}
-+
-+/**
-+ * zynqmp_pll_recalc_rate() - Recalculate clock frequency
-+ * @hw: Handle between common and hardware-specific interfaces
-+ * @parent_rate: Clock frequency of parent clock
-+ *
-+ * Return: Current clock frequency
-+ */
-+static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
-+ u32 clk_id = clk->clk_id;
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 fbdiv, data;
-+ unsigned long rate, frac;
-+ __le32 ret_payload[PAYLOAD_ARG_CNT];
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ ret = eemi_ops->clock_getdivider(clk_id, &fbdiv);
-+ if (ret)
-+ pr_warn_once("%s() get divider failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ rate = parent_rate * fbdiv;
-+ if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
-+ eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_DATA, clk_id, 0,
-+ ret_payload);
-+ data = ret_payload[1];
-+ frac = (parent_rate * data) / FRAC_DIV;
-+ rate = rate + frac;
-+ }
-+
-+ return rate;
-+}
-+
-+/**
-+ * zynqmp_pll_set_rate() - Set rate of PLL
-+ * @hw: Handle between common and hardware-specific interfaces
-+ * @rate: Frequency of clock to be set
-+ * @parent_rate: Clock frequency of parent clock
-+ *
-+ * Set PLL divider to set desired rate.
-+ *
-+ * Returns: rate which is set on success else error code
-+ */
-+static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
-+ unsigned long parent_rate)
-+{
-+ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
-+ u32 clk_id = clk->clk_id;
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 fbdiv;
-+ long rate_div, frac, m, f;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
-+ rate_div = (rate * FRAC_DIV) / parent_rate;
-+ m = rate_div / FRAC_DIV;
-+ f = rate_div % FRAC_DIV;
-+ m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
-+ rate = parent_rate * m;
-+ frac = (parent_rate * f) / FRAC_DIV;
-+
-+ ret = eemi_ops->clock_setdivider(clk_id, m);
-+ if (ret)
-+ pr_warn_once("%s() set divider failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL);
-+
-+ return rate + frac;
-+ }
-+
-+ fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
-+ fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
-+ ret = eemi_ops->clock_setdivider(clk_id, fbdiv);
-+ if (ret)
-+ pr_warn_once("%s() set divider failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ return parent_rate * fbdiv;
-+}
-+
-+/**
-+ * zynqmp_pll_is_enabled() - Check if a clock is enabled
-+ * @hw: Handle between common and hardware-specific interfaces
-+ *
-+ * Return: 1 if the clock is enabled, 0 otherwise
-+ */
-+static int zynqmp_pll_is_enabled(struct clk_hw *hw)
-+{
-+ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = clk->clk_id;
-+ unsigned int state;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ ret = eemi_ops->clock_getstate(clk_id, &state);
-+ if (ret) {
-+ pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+ return -EIO;
-+ }
-+
-+ return state ? 1 : 0;
-+}
-+
-+/**
-+ * zynqmp_pll_enable() - Enable clock
-+ * @hw: Handle between common and hardware-specific interfaces
-+ *
-+ * Return: 0 on success else error code
-+ */
-+static int zynqmp_pll_enable(struct clk_hw *hw)
-+{
-+ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = clk->clk_id;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ if (zynqmp_pll_is_enabled(hw))
-+ return 0;
-+
-+ ret = eemi_ops->clock_enable(clk_id);
-+ if (ret)
-+ pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+
-+ return ret;
-+}
-+
-+/**
-+ * zynqmp_pll_disable() - Disable clock
-+ * @hw: Handle between common and hardware-specific interfaces
-+ */
-+static void zynqmp_pll_disable(struct clk_hw *hw)
-+{
-+ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
-+ const char *clk_name = clk_hw_get_name(hw);
-+ u32 clk_id = clk->clk_id;
-+ int ret;
-+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
-+
-+ if (!zynqmp_pll_is_enabled(hw))
-+ return;
-+
-+ ret = eemi_ops->clock_disable(clk_id);
-+ if (ret)
-+ pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
-+ __func__, clk_name, ret);
-+}
-+
-+static const struct clk_ops zynqmp_pll_ops = {
-+ .enable = zynqmp_pll_enable,
-+ .disable = zynqmp_pll_disable,
-+ .is_enabled = zynqmp_pll_is_enabled,
-+ .round_rate = zynqmp_pll_round_rate,
-+ .recalc_rate = zynqmp_pll_recalc_rate,
-+ .set_rate = zynqmp_pll_set_rate,
-+};
-+
-+/**
-+ * zynqmp_clk_register_pll() - Register PLL with the clock framework
-+ * @name: PLL name
-+ * @clk_id: Clock ID
-+ * @parents: Name of this clock's parents
-+ * @num_parents: Number of parents
-+ * @nodes: Clock topology node
-+ *
-+ * Return: clock hardware to the registered clock
-+ */
-+struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
-+ const char * const *parents,
-+ u8 num_parents,
-+ const struct clock_topology *nodes)
-+{
-+ struct zynqmp_pll *pll;
-+ struct clk_hw *hw;
-+ struct clk_init_data init;
-+ int ret;
-+
-+ init.name = name;
-+ init.ops = &zynqmp_pll_ops;
-+ init.flags = nodes->flag;
-+ init.parent_names = parents;
-+ init.num_parents = 1;
-+
-+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-+ if (!pll)
-+ return ERR_PTR(-ENOMEM);
-+
-+ pll->hw.init = &init;
-+ pll->clk_id = clk_id;
-+
-+ hw = &pll->hw;
-+ ret = clk_hw_register(NULL, hw);
-+ if (ret) {
-+ kfree(pll);
-+ return ERR_PTR(ret);
-+ }
-+
-+ clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX);
-+ if (ret < 0)
-+ pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret);
-+
-+ return hw;
-+}
-diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
-index 58a7478..a3ef7d6 100644
---- a/include/linux/firmware/xlnx-zynqmp.h
-+++ b/include/linux/firmware/xlnx-zynqmp.h
-@@ -72,6 +72,7 @@ enum pm_query_id {
- PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
- PM_QID_CLOCK_GET_PARENTS,
- PM_QID_CLOCK_GET_ATTRIBUTES,
-+ PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
- };
-
- /**
-
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-From: Rajan Vaja <rajan.vaja@xilinx.com>
-
-As of all of child of ZynqMP firmware are platform
-driver, there is no need of init call in firmware
-driver. Earlier clock driver was init method so
-firmware driver had to use init call to make sure
-firmware init is done in early stage.
-
-Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
-Signed-off-by: Jolly Shah <jollys@xilinx.com>
----
- drivers/firmware/xilinx/zynqmp.c | 63 ++++++++++++----------------------------
- 1 file changed, 18 insertions(+), 45 deletions(-)
-
-diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
-index 7ccedf0..ce6c746 100644
---- a/drivers/firmware/xilinx/zynqmp.c
-+++ b/drivers/firmware/xilinx/zynqmp.c
-@@ -476,50 +476,17 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_get_eemi_ops);
- static int zynqmp_firmware_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
--
-- return of_platform_populate(dev->of_node, NULL, NULL, dev);
--}
--
--static const struct of_device_id zynqmp_firmware_of_match[] = {
-- {.compatible = "xlnx,zynqmp-firmware"},
-- {},
--};
--MODULE_DEVICE_TABLE(of, zynqmp_firmware_of_match);
--
--static struct platform_driver zynqmp_firmware_driver = {
-- .driver = {
-- .name = "zynqmp_firmware",
-- .of_match_table = zynqmp_firmware_of_match,
-- },
-- .probe = zynqmp_firmware_probe,
--};
--module_platform_driver(zynqmp_firmware_driver);
--
--static int __init zynqmp_plat_init(void)
--{
-- int ret;
- struct device_node *np;
-+ int ret;
-
- np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp");
- if (!np)
- return 0;
- of_node_put(np);
-
-- /*
-- * We're running on a ZynqMP machine,
-- * the zynqmp-firmware node is mandatory.
-- */
-- np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp-firmware");
-- if (!np) {
-- pr_warn("%s: zynqmp-firmware node not found\n", __func__);
-- return -ENXIO;
-- }
--
-- ret = get_set_conduit_method(np);
-- if (ret) {
-- of_node_put(np);
-+ ret = get_set_conduit_method(dev->of_node);
-+ if (ret)
- return ret;
-- }
-
- /* Check PM API version number */
- zynqmp_pm_get_api_version(&pm_api_version);
-@@ -547,16 +514,22 @@ static int __init zynqmp_plat_init(void)
- pr_info("%s Trustzone version v%d.%d\n", __func__,
- pm_tz_version >> 16, pm_tz_version & 0xFFFF);
-
-- of_node_put(np);
-+ zynqmp_pm_api_debugfs_init();
-
-- return ret;
-+ return of_platform_populate(dev->of_node, NULL, NULL, dev);
- }
--early_initcall(zynqmp_plat_init);
-
--static int zynqmp_firmware_init(void)
--{
-- zynqmp_pm_api_debugfs_init();
-+static const struct of_device_id zynqmp_firmware_of_match[] = {
-+ {.compatible = "xlnx,zynqmp-firmware"},
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, zynqmp_firmware_of_match);
-
-- return 0;
--}
--device_initcall(zynqmp_firmware_init);
-+static struct platform_driver zynqmp_firmware_driver = {
-+ .driver = {
-+ .name = "zynqmp_firmware",
-+ .of_match_table = zynqmp_firmware_of_match,
-+ },
-+ .probe = zynqmp_firmware_probe,
-+};
-+module_platform_driver(zynqmp_firmware_driver);
diff --git a/arm64-rockchip-add-initial-Rockpro64.patch b/arm64-rockchip-add-initial-Rockpro64.patch
deleted file mode 100644
index 5ccb2e955..000000000
--- a/arm64-rockchip-add-initial-Rockpro64.patch
+++ /dev/null
@@ -1,862 +0,0 @@
-From patchwork Wed Sep 26 06:24:57 2018
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-From: Akash Gajjar <Akash_Gajjar@mentor.com>
-To: <heiko@sntech.de>
-Subject: [PATCH v3] arm64: dts: rockchip: add initial dts support for
- Rockpro64
-Date: Wed, 26 Sep 2018 11:54:57 +0530
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-Rockpro64 is a rockchip RK3399 based board from pine64.org.
-This patch adds basic device node support for Rockpro64 board and make it able
-to bring up.
-
-Peripheral Works
-- Sdcard
-- USB 2.0, 3.0
-- Leds
-- Ethernet
-- Debug console
-
-Not working:
-- USB Type-C
-
-Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
-Acked-by: Deepak Das <Deepak_Das@mentor.com>
----
-changes for v2
-- Added support for usb 2.0, 3.0
-- Added fusb302 node and its regulator support
-- Cleanup pinctrl node
-- Remove backlight, pcie, sound codec node inherited from firefly-rk3399 dts
-changes for v3
-- Added copyright properly
-- Typo correction in commit message
-
- Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts | 692 +++++++++++++++++++++
- 3 files changed, 697 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
-
-diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
-index acfd3c7..ac95183 100644
---- a/Documentation/devicetree/bindings/arm/rockchip.txt
-+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
-@@ -160,6 +160,10 @@ Rockchip platforms device tree bindings
- Required root node properties:
- - compatible = "pine64,rock64", "rockchip,rk3328";
-
-+- Pine64 RockPro64 board:
-+ Required root node properties:
-+ - compatible = "pine64,rockpro64", "rockchip,rk3399";
-+
- - Rockchip PX3 Evaluation board:
- Required root node properties:
- - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
-diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
-index b0092d9..03d523a 100644
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -15,5 +15,6 @@
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
-new file mode 100644
-index 0000000..1d35f54
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
-@@ -0,0 +1,692 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
-+ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/input/linux-event-codes.h>
-+#include <dt-bindings/pwm/pwm.h>
-+#include "rk3399.dtsi"
-+#include "rk3399-opp.dtsi"
-+
-+/ {
-+ model = "Pine64 RockPro64";
-+ compatible = "pine64,rockpro64", "rockchip,rk3399";
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ clkin_gmac: external-gmac-clock {
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "clkin_gmac";
-+ #clock-cells = <0>;
-+ };
-+
-+ dc_12v: dc-12v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "dc_12v";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <12000000>;
-+ regulator-max-microvolt = <12000000>;
-+ };
-+
-+ gpio-keys {
-+ compatible = "gpio-keys";
-+ autorepeat;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pwrbtn>;
-+
-+ power {
-+ debounce-interval = <100>;
-+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
-+ label = "GPIO Key Power";
-+ linux,code = <KEY_POWER>;
-+ wakeup-source;
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
-+
-+ work-led {
-+ label = "work";
-+ default-state = "on";
-+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ diy-led {
-+ label = "diy";
-+ default-state = "off";
-+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+
-+ sdio_pwrseq: sdio-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ clocks = <&rk808 1>;
-+ clock-names = "ext_clock";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_enable_h>;
-+
-+ /*
-+ * On the module itself this is one of these (depending
-+ * on the actual card populated):
-+ * - SDIO_RESET_L_WL_REG_ON
-+ * - PDN (power down when low)
-+ */
-+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
-+ };
-+
-+ /* switched by pmic_sleep */
-+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc1v8_s3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8>;
-+ };
-+
-+ vcc3v3_pcie: vcc3v3-pcie-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_pwr_en>;
-+ regulator-name = "vcc3v3_pcie";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ vin-supply = <&dc_12v>;
-+ };
-+
-+ vcc3v3_sys: vcc3v3-sys {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc_sys>;
-+ };
-+
-+ /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
-+ vcc5v0_host: vcc5v0-host-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_host_en>;
-+ regulator-name = "vcc5v0_host";
-+ regulator-always-on;
-+ vin-supply = <&vcc_sys>;
-+ };
-+
-+ vcc5v0_typec: vcc5v0-typec-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_typec_en>;
-+ regulator-name = "vcc5v0_typec";
-+ regulator-always-on;
-+ vin-supply = <&vcc_sys>;
-+ };
-+
-+ vcc_sys: vcc-sys {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&dc_12v>;
-+ };
-+
-+ vdd_log: vdd-log {
-+ compatible = "pwm-regulator";
-+ pwms = <&pwm2 0 25000 1>;
-+ regulator-name = "vdd_log";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1400000>;
-+ vin-supply = <&vcc_sys>;
-+ };
-+};
-+
-+&cpu_l0 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l1 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l2 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l3 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_b0 {
-+ cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&cpu_b1 {
-+ cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&emmc_phy {
-+ status = "okay";
-+};
-+
-+&gmac {
-+ assigned-clocks = <&cru SCLK_RMII_SRC>;
-+ assigned-clock-parents = <&clkin_gmac>;
-+ clock_in_out = "input";
-+ phy-supply = <&vcc_lan>;
-+ phy-mode = "rgmii";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rgmii_pins>;
-+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
-+ snps,reset-active-low;
-+ snps,reset-delays-us = <0 10000 50000>;
-+ tx_delay = <0x28>;
-+ rx_delay = <0x11>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ clock-frequency = <400000>;
-+ i2c-scl-rising-time-ns = <168>;
-+ i2c-scl-falling-time-ns = <4>;
-+ status = "okay";
-+
-+ rk808: pmic@1b {
-+ compatible = "rockchip,rk808";
-+ reg = <0x1b>;
-+ interrupt-parent = <&gpio1>;
-+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ clock-output-names = "xin32k", "rk808-clkout2";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int_l>;
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc_sys>;
-+ vcc2-supply = <&vcc_sys>;
-+ vcc3-supply = <&vcc_sys>;
-+ vcc4-supply = <&vcc_sys>;
-+ vcc6-supply = <&vcc_sys>;
-+ vcc7-supply = <&vcc_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc_sys>;
-+ vcc10-supply = <&vcc_sys>;
-+ vcc11-supply = <&vcc_sys>;
-+ vcc12-supply = <&vcc3v3_sys>;
-+ vddio-supply = <&vcc1v8_pmu>;
-+
-+ regulators {
-+ vdd_center: DCDC_REG1 {
-+ regulator-name = "vdd_center";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_cpu_l: DCDC_REG2 {
-+ regulator-name = "vdd_cpu_l";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG4 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcc1v8_dvp: LDO_REG1 {
-+ regulator-name = "vcc1v8_dvp";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc2v8_dvp: LDO_REG2 {
-+ regulator-name = "vcc2v8_dvp";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <2800000>;
-+ regulator-max-microvolt = <2800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc1v8_pmu: LDO_REG3 {
-+ regulator-name = "vcc1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcc_sdio: LDO_REG4 {
-+ regulator-name = "vcc_sdio";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3000000>;
-+ };
-+ };
-+
-+ vcca3v0_codec: LDO_REG5 {
-+ regulator-name = "vcca3v0_codec";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3000000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v5: LDO_REG6 {
-+ regulator-name = "vcc_1v5";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1500000>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1500000>;
-+ };
-+ };
-+
-+ vcca1v8_codec: LDO_REG7 {
-+ regulator-name = "vcca1v8_codec";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v0: LDO_REG8 {
-+ regulator-name = "vcc_3v0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3000000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3000000>;
-+ };
-+ };
-+
-+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
-+ regulator-name = "vcc3v3_s3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_s0: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+
-+ vdd_cpu_b: regulator@40 {
-+ compatible = "silergy,syr827";
-+ reg = <0x40>;
-+ fcs,suspend-voltage-selector = <0>;
-+ regulator-name = "vdd_cpu_b";
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-ramp-delay = <1000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ vin-supply = <&vcc_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: regulator@41 {
-+ compatible = "silergy,syr828";
-+ reg = <0x41>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_gpu";
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-ramp-delay = <1000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ vin-supply = <&vcc_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+};
-+
-+&i2c1 {
-+ i2c-scl-rising-time-ns = <300>;
-+ i2c-scl-falling-time-ns = <15>;
-+ status = "okay";
-+};
-+
-+&i2c3 {
-+ i2c-scl-rising-time-ns = <450>;
-+ i2c-scl-falling-time-ns = <15>;
-+ status = "okay";
-+};
-+
-+&i2c4 {
-+ i2c-scl-rising-time-ns = <600>;
-+ i2c-scl-falling-time-ns = <20>;
-+ status = "okay";
-+
-+ fusb0: typec-portc@22 {
-+ compatible = "fcs,fusb302";
-+ reg = <0x22>;
-+ interrupt-parent = <&gpio1>;
-+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&fusb0_int>;
-+ vbus-supply = <&vcc5v0_typec>;
-+ status = "okay";
-+ };
-+};
-+
-+&i2s0 {
-+ rockchip,playback-channels = <8>;
-+ rockchip,capture-channels = <8>;
-+ status = "okay";
-+};
-+
-+&i2s1 {
-+ rockchip,playback-channels = <2>;
-+ rockchip,capture-channels = <2>;
-+ status = "okay";
-+};
-+
-+&i2s2 {
-+ status = "okay";
-+};
-+
-+&io_domains {
-+ status = "okay";
-+
-+ bt656-supply = <&vcc1v8_dvp>;
-+ audio-supply = <&vcca1v8_codec>;
-+ sdmmc-supply = <&vcc_sdio>;
-+ gpio1830-supply = <&vcc_3v0>;
-+};
-+
-+&pmu_io_domains {
-+ pmu1830-supply = <&vcc_3v0>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ buttons {
-+ pwrbtn: pwrbtn {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ fusb302x {
-+ fusb0_int: fusb0-int {
-+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ leds {
-+ work_led_gpio: work_led-gpio {
-+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ diy_led_gpio: diy_led-gpio {
-+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ lcd-panel {
-+ lcd_panel_reset: lcd-panel-reset {
-+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ pcie {
-+ pcie_pwr_en: pcie-pwr-en {
-+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+
-+ vsel1_gpio: vsel1-gpio {
-+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+
-+ vsel2_gpio: vsel2-gpio {
-+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+ };
-+
-+ sdio-pwrseq {
-+ wifi_enable_h: wifi-enable-h {
-+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb-typec {
-+ vcc5v0_typec_en: vcc5v0_typec_en {
-+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb2 {
-+ vcc5v0_host_en: vcc5v0-host-en {
-+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pwm0 {
-+ status = "okay";
-+};
-+
-+&pwm2 {
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca1v8_s3>;
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
-+ disable-wp;
-+ max-frequency = <150000000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ mmc-hs400-1_8v;
-+ mmc-hs400-enhanced-strobe;
-+ non-removable;
-+ status = "okay";
-+};
-+
-+&tcphy0 {
-+ status = "okay";
-+};
-+
-+&tcphy1 {
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ /* tshut mode 0:CRU 1:GPIO */
-+ rockchip,hw-tshut-mode = <1>;
-+ /* tshut polarity 0:LOW 1:HIGH */
-+ rockchip,hw-tshut-polarity = <1>;
-+ status = "okay";
-+};
-+
-+&u2phy0 {
-+ status = "okay";
-+
-+ u2phy0_otg: otg-port {
-+ status = "okay";
-+ };
-+
-+ u2phy0_host: host-port {
-+ phy-supply = <&vcc5v0_host>;
-+ status = "okay";
-+ };
-+};
-+
-+&u2phy1 {
-+ status = "okay";
-+
-+ u2phy1_otg: otg-port {
-+ status = "okay";
-+ };
-+
-+ u2phy1_host: host-port {
-+ phy-supply = <&vcc5v0_host>;
-+ status = "okay";
-+ };
-+};
-+
-+&uart0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usbdrd3_0 {
-+ status = "okay";
-+};
-+
-+&usbdrd_dwc3_0 {
-+ status = "okay";
-+ dr_mode = "otg";
-+};
-+
-+&usbdrd3_1 {
-+ status = "okay";
-+};
-+
-+&usbdrd_dwc3_1 {
-+ status = "okay";
-+ dr_mode = "host";
-+};
-+
-+&vopb {
-+ status = "okay";
-+};
-+
-+&vopb_mmu {
-+ status = "okay";
-+};
-+
-+&vopl {
-+ status = "okay";
-+};
-+
-+&vopl_mmu {
-+ status = "okay";
-+};
diff --git a/configs/fedora/generic/CONFIG_ADXL372_I2C b/configs/fedora/generic/CONFIG_ADXL372_I2C
new file mode 100644
index 000000000..0944246ac
--- /dev/null
+++ b/configs/fedora/generic/CONFIG_ADXL372_I2C
@@ -0,0 +1 @@
+CONFIG_ADXL372_I2C=m
diff --git a/configs/fedora/generic/CONFIG_ADXL372_SPI b/configs/fedora/generic/CONFIG_ADXL372_SPI
new file mode 100644
index 000000000..f38da0660
--- /dev/null
+++ b/configs/fedora/generic/CONFIG_ADXL372_SPI
@@ -0,0 +1 @@
+CONFIG_ADXL372_SPI=m
diff --git a/configs/fedora/generic/CONFIG_LTC1660 b/configs/fedora/generic/CONFIG_LTC1660
new file mode 100644
index 000000000..e9ca00da8
--- /dev/null
+++ b/configs/fedora/generic/CONFIG_LTC1660
@@ -0,0 +1 @@
+CONFIG_LTC1660=m
diff --git a/configs/fedora/generic/CONFIG_MCP3911 b/configs/fedora/generic/CONFIG_MCP3911
new file mode 100644
index 000000000..fd3466b20
--- /dev/null
+++ b/configs/fedora/generic/CONFIG_MCP3911
@@ -0,0 +1 @@
+CONFIG_MCP3911=m
diff --git a/configs/fedora/generic/CONFIG_VL53L0X_I2C b/configs/fedora/generic/CONFIG_VL53L0X_I2C
new file mode 100644
index 000000000..2ee7f58bb
--- /dev/null
+++ b/configs/fedora/generic/CONFIG_VL53L0X_I2C
@@ -0,0 +1 @@
+# CONFIG_VL53L0X_I2C is not set
diff --git a/configs/fedora/generic/arm/CONFIG_MESON_CANVAS b/configs/fedora/generic/arm/CONFIG_MESON_CANVAS
new file mode 100644
index 000000000..72094e634
--- /dev/null
+++ b/configs/fedora/generic/arm/CONFIG_MESON_CANVAS
@@ -0,0 +1 @@
+CONFIG_MESON_CANVAS=m
diff --git a/configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_ADSP b/configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_ADSP
new file mode 100644
index 000000000..733875850
--- /dev/null
+++ b/configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_ADSP
@@ -0,0 +1 @@
+CONFIG_QCOM_Q6V5_ADSP=m
diff --git a/configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_MSS b/configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_MSS
new file mode 100644
index 000000000..6074483d8
--- /dev/null
+++ b/configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_MSS
@@ -0,0 +1 @@
+CONFIG_QCOM_Q6V5_MSS=m
diff --git a/configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_PAS b/configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_PAS
new file mode 100644
index 000000000..8a33aa23f
--- /dev/null
+++ b/configs/fedora/generic/arm/CONFIG_QCOM_Q6V5_PAS
@@ -0,0 +1 @@
+CONFIG_QCOM_Q6V5_PAS=m
diff --git a/configs/fedora/generic/arm/CONFIG_QCOM_SPMI_ADC5 b/configs/fedora/generic/arm/CONFIG_QCOM_SPMI_ADC5
new file mode 100644
index 000000000..48a201cde
--- /dev/null
+++ b/configs/fedora/generic/arm/CONFIG_QCOM_SPMI_ADC5
@@ -0,0 +1 @@
+CONFIG_QCOM_SPMI_ADC5=m
diff --git a/configs/fedora/generic/arm/CONFIG_RESET_QCOM_PDC b/configs/fedora/generic/arm/CONFIG_RESET_QCOM_PDC
new file mode 100644
index 000000000..b995137a0
--- /dev/null
+++ b/configs/fedora/generic/arm/CONFIG_RESET_QCOM_PDC
@@ -0,0 +1 @@
+CONFIG_RESET_QCOM_PDC=m
diff --git a/configs/fedora/generic/arm/CONFIG_VIDEO_IMX_PXP b/configs/fedora/generic/arm/CONFIG_VIDEO_IMX_PXP
new file mode 100644
index 000000000..6b98c7c3f
--- /dev/null
+++ b/configs/fedora/generic/arm/CONFIG_VIDEO_IMX_PXP
@@ -0,0 +1 @@
+CONFIG_VIDEO_IMX_PXP=m
diff --git a/configs/fedora/generic/arm/armv7/CONFIG_IMX_SCU b/configs/fedora/generic/arm/armv7/CONFIG_IMX_SCU
new file mode 100644
index 000000000..f044bdbb0
--- /dev/null
+++ b/configs/fedora/generic/arm/armv7/CONFIG_IMX_SCU
@@ -0,0 +1 @@
+CONFIG_IMX_SCU=y
diff --git a/gitrev b/gitrev
index 7e28936b4..9e89def85 100644
--- a/gitrev
+++ b/gitrev
@@ -1 +1 @@
-673c790e72822ee433931ea701e4fceef75a0eac
+11743c56785c751c087eecdb98713eef796609e0
diff --git a/kernel-aarch64-debug.config b/kernel-aarch64-debug.config
index 23f34cdb8..a11057863 100644
--- a/kernel-aarch64-debug.config
+++ b/kernel-aarch64-debug.config
@@ -147,6 +147,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -3118,6 +3120,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3192,6 +3195,7 @@ CONFIG_MAXSMP=y
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -3264,6 +3268,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
# CONFIG_MEMTEST is not set
# CONFIG_MEN_A21_WDT is not set
+CONFIG_MESON_CANVAS=m
CONFIG_MESON_EFUSE=m
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_GXL_PHY=m
@@ -4689,6 +4694,9 @@ CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_PDC=y
+CONFIG_QCOM_Q6V5_ADSP=m
+CONFIG_QCOM_Q6V5_MSS=m
+CONFIG_QCOM_Q6V5_PAS=m
CONFIG_QCOM_Q6V5_PIL=m
# CONFIG_QCOM_Q6V5_WCSS is not set
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
@@ -4700,6 +4708,7 @@ CONFIG_QCOM_SMD_RPM=m
CONFIG_QCOM_SMEM=m
CONFIG_QCOM_SMP2P=m
CONFIG_QCOM_SMSM=m
+CONFIG_QCOM_SPMI_ADC5=m
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_TEMP_ALARM=m
CONFIG_QCOM_SPMI_VADC=m
@@ -4885,6 +4894,7 @@ CONFIG_RESET_HISI=y
# CONFIG_RESET_HSDK_V1 is not set
# CONFIG_RESET_MESON_AUDIO_ARB is not set
# CONFIG_RESET_QCOM_AOSS is not set
+CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_SIMPLE=y
# CONFIG_RESET_TI_SCI is not set
# CONFIG_RESET_TI_SYSCON is not set
@@ -6952,6 +6962,7 @@ CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_HEXIUM_GEMINI=m
CONFIG_VIDEO_HEXIUM_ORION=m
+CONFIG_VIDEO_IMX_PXP=m
# CONFIG_VIDEO_IVTV_ALSA is not set
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
CONFIG_VIDEO_IVTV=m
@@ -7023,6 +7034,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-aarch64.config b/kernel-aarch64.config
index 902f3c892..019e4ca01 100644
--- a/kernel-aarch64.config
+++ b/kernel-aarch64.config
@@ -147,6 +147,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -3098,6 +3100,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3171,6 +3174,7 @@ CONFIG_MAX_RAW_DEVS=8192
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -3243,6 +3247,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
# CONFIG_MEMTEST is not set
# CONFIG_MEN_A21_WDT is not set
+CONFIG_MESON_CANVAS=m
CONFIG_MESON_EFUSE=m
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_GXL_PHY=m
@@ -4666,6 +4671,9 @@ CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_PDC=y
+CONFIG_QCOM_Q6V5_ADSP=m
+CONFIG_QCOM_Q6V5_MSS=m
+CONFIG_QCOM_Q6V5_PAS=m
CONFIG_QCOM_Q6V5_PIL=m
# CONFIG_QCOM_Q6V5_WCSS is not set
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
@@ -4677,6 +4685,7 @@ CONFIG_QCOM_SMD_RPM=m
CONFIG_QCOM_SMEM=m
CONFIG_QCOM_SMP2P=m
CONFIG_QCOM_SMSM=m
+CONFIG_QCOM_SPMI_ADC5=m
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_TEMP_ALARM=m
CONFIG_QCOM_SPMI_VADC=m
@@ -4862,6 +4871,7 @@ CONFIG_RESET_HISI=y
# CONFIG_RESET_HSDK_V1 is not set
# CONFIG_RESET_MESON_AUDIO_ARB is not set
# CONFIG_RESET_QCOM_AOSS is not set
+CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_SIMPLE=y
# CONFIG_RESET_TI_SCI is not set
# CONFIG_RESET_TI_SYSCON is not set
@@ -6928,6 +6938,7 @@ CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_HEXIUM_GEMINI=m
CONFIG_VIDEO_HEXIUM_ORION=m
+CONFIG_VIDEO_IMX_PXP=m
# CONFIG_VIDEO_IVTV_ALSA is not set
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
CONFIG_VIDEO_IVTV=m
@@ -6999,6 +7010,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-armv7hl-debug.config b/kernel-armv7hl-debug.config
index d140e0a8f..bad80c197 100644
--- a/kernel-armv7hl-debug.config
+++ b/kernel-armv7hl-debug.config
@@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
CONFIG_AEABI=y
# CONFIG_AFE4403 is not set
@@ -2541,6 +2543,7 @@ CONFIG_IMX_GPCV2=y
CONFIG_IMX_IPUV3_CORE=m
CONFIG_IMX_MBOX=m
CONFIG_IMX_REMOTEPROC=m
+CONFIG_IMX_SCU=y
CONFIG_IMX_SDMA=m
CONFIG_IMX_THERMAL=m
CONFIG_IMX_WEIM=y
@@ -3263,6 +3266,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=32768
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3356,6 +3360,7 @@ CONFIG_MAXSMP=y
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -3428,6 +3433,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
# CONFIG_MEMTEST is not set
# CONFIG_MEN_A21_WDT is not set
+CONFIG_MESON_CANVAS=m
CONFIG_MESON_EFUSE=m
# CONFIG_MESON_GXBB_WATCHDOG is not set
# CONFIG_MESON_GXL_PHY is not set
@@ -4959,6 +4965,9 @@ CONFIG_QCOM_IOMMU=y
CONFIG_QCOM_PDC=y
CONFIG_QCOM_PM8XXX_XOADC=m
CONFIG_QCOM_PM=y
+CONFIG_QCOM_Q6V5_ADSP=m
+CONFIG_QCOM_Q6V5_MSS=m
+CONFIG_QCOM_Q6V5_PAS=m
CONFIG_QCOM_Q6V5_PIL=m
# CONFIG_QCOM_Q6V5_WCSS is not set
CONFIG_QCOM_QFPROM=m
@@ -4969,6 +4978,7 @@ CONFIG_QCOM_SMD_RPM=m
CONFIG_QCOM_SMEM=m
CONFIG_QCOM_SMP2P=m
CONFIG_QCOM_SMSM=m
+CONFIG_QCOM_SPMI_ADC5=m
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_TEMP_ALARM=m
CONFIG_QCOM_SPMI_VADC=m
@@ -5174,6 +5184,7 @@ CONFIG_RESET_GPIO=y
# CONFIG_RESET_HSDK_V1 is not set
# CONFIG_RESET_MESON_AUDIO_ARB is not set
# CONFIG_RESET_QCOM_AOSS is not set
+CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_SIMPLE=y
# CONFIG_RESET_TI_SCI is not set
# CONFIG_RESET_TI_SYSCON is not set
@@ -7426,6 +7437,7 @@ CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_HEXIUM_GEMINI=m
CONFIG_VIDEO_HEXIUM_ORION=m
# CONFIG_VIDEO_IMX_MEDIA is not set
+CONFIG_VIDEO_IMX_PXP=m
CONFIG_VIDEO_IMX_VDOA=m
# CONFIG_VIDEO_IVTV_ALSA is not set
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
@@ -7519,6 +7531,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-armv7hl-lpae-debug.config b/kernel-armv7hl-lpae-debug.config
index 5a6a1a2f3..1e3b884df 100644
--- a/kernel-armv7hl-lpae-debug.config
+++ b/kernel-armv7hl-lpae-debug.config
@@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
CONFIG_AEABI=y
# CONFIG_AFE4403 is not set
@@ -2420,6 +2422,7 @@ CONFIG_IMA=y
# CONFIG_IMG_ASCII_LCD is not set
# CONFIG_IMX_IPUV3_CORE is not set
CONFIG_IMX_MBOX=m
+CONFIG_IMX_SCU=y
# CONFIG_INA2XX_ADC is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
@@ -3123,6 +3126,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=32768
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3210,6 +3214,7 @@ CONFIG_MAXSMP=y
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -3280,6 +3285,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
# CONFIG_MEMTEST is not set
# CONFIG_MEN_A21_WDT is not set
+CONFIG_MESON_CANVAS=m
CONFIG_MESON_EFUSE=m
# CONFIG_MESON_GXBB_WATCHDOG is not set
# CONFIG_MESON_GXL_PHY is not set
@@ -4698,10 +4704,14 @@ CONFIG_QCOM_CLK_APCS_MSM8916=m
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_PDC=y
CONFIG_QCOM_PM8XXX_XOADC=m
+CONFIG_QCOM_Q6V5_ADSP=m
+CONFIG_QCOM_Q6V5_MSS=m
+CONFIG_QCOM_Q6V5_PAS=m
# CONFIG_QCOM_Q6V5_WCSS is not set
CONFIG_QCOM_RMTFS_MEM=m
# CONFIG_QCOM_RPMH is not set
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
+CONFIG_QCOM_SPMI_ADC5=m
CONFIG_QCOM_SYSMON=m
CONFIG_QEDE=m
CONFIG_QEDF=m
@@ -4883,6 +4893,7 @@ CONFIG_RESET_GPIO=y
# CONFIG_RESET_HSDK_V1 is not set
# CONFIG_RESET_MESON_AUDIO_ARB is not set
# CONFIG_RESET_QCOM_AOSS is not set
+CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_SIMPLE=y
# CONFIG_RESET_TI_SCI is not set
# CONFIG_RESET_TI_SYSCON is not set
@@ -6990,6 +7001,7 @@ CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_HEXIUM_GEMINI=m
CONFIG_VIDEO_HEXIUM_ORION=m
# CONFIG_VIDEO_IMX_MEDIA is not set
+CONFIG_VIDEO_IMX_PXP=m
# CONFIG_VIDEO_IVTV_ALSA is not set
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
CONFIG_VIDEO_IVTV=m
@@ -7069,6 +7081,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-armv7hl-lpae.config b/kernel-armv7hl-lpae.config
index fdeec2385..4633f7595 100644
--- a/kernel-armv7hl-lpae.config
+++ b/kernel-armv7hl-lpae.config
@@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
CONFIG_AEABI=y
# CONFIG_AFE4403 is not set
@@ -2402,6 +2404,7 @@ CONFIG_IMA=y
# CONFIG_IMG_ASCII_LCD is not set
# CONFIG_IMX_IPUV3_CORE is not set
CONFIG_IMX_MBOX=m
+CONFIG_IMX_SCU=y
# CONFIG_INA2XX_ADC is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
@@ -3103,6 +3106,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=32768
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3189,6 +3193,7 @@ CONFIG_MAX_RAW_DEVS=8192
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -3259,6 +3264,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
# CONFIG_MEMTEST is not set
# CONFIG_MEN_A21_WDT is not set
+CONFIG_MESON_CANVAS=m
CONFIG_MESON_EFUSE=m
# CONFIG_MESON_GXBB_WATCHDOG is not set
# CONFIG_MESON_GXL_PHY is not set
@@ -4675,10 +4681,14 @@ CONFIG_QCOM_CLK_APCS_MSM8916=m
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_PDC=y
CONFIG_QCOM_PM8XXX_XOADC=m
+CONFIG_QCOM_Q6V5_ADSP=m
+CONFIG_QCOM_Q6V5_MSS=m
+CONFIG_QCOM_Q6V5_PAS=m
# CONFIG_QCOM_Q6V5_WCSS is not set
CONFIG_QCOM_RMTFS_MEM=m
# CONFIG_QCOM_RPMH is not set
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
+CONFIG_QCOM_SPMI_ADC5=m
CONFIG_QCOM_SYSMON=m
CONFIG_QEDE=m
CONFIG_QEDF=m
@@ -4860,6 +4870,7 @@ CONFIG_RESET_GPIO=y
# CONFIG_RESET_HSDK_V1 is not set
# CONFIG_RESET_MESON_AUDIO_ARB is not set
# CONFIG_RESET_QCOM_AOSS is not set
+CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_SIMPLE=y
# CONFIG_RESET_TI_SCI is not set
# CONFIG_RESET_TI_SYSCON is not set
@@ -6966,6 +6977,7 @@ CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_HEXIUM_GEMINI=m
CONFIG_VIDEO_HEXIUM_ORION=m
# CONFIG_VIDEO_IMX_MEDIA is not set
+CONFIG_VIDEO_IMX_PXP=m
# CONFIG_VIDEO_IVTV_ALSA is not set
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
CONFIG_VIDEO_IVTV=m
@@ -7045,6 +7057,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-armv7hl.config b/kernel-armv7hl.config
index 61b0a9d2b..0ccd1991f 100644
--- a/kernel-armv7hl.config
+++ b/kernel-armv7hl.config
@@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
CONFIG_AEABI=y
# CONFIG_AFE4403 is not set
@@ -2523,6 +2525,7 @@ CONFIG_IMX_GPCV2=y
CONFIG_IMX_IPUV3_CORE=m
CONFIG_IMX_MBOX=m
CONFIG_IMX_REMOTEPROC=m
+CONFIG_IMX_SCU=y
CONFIG_IMX_SDMA=m
CONFIG_IMX_THERMAL=m
CONFIG_IMX_WEIM=y
@@ -3243,6 +3246,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=32768
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3335,6 +3339,7 @@ CONFIG_MAX_RAW_DEVS=8192
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -3407,6 +3412,7 @@ CONFIG_MEMSTICK_TIFM_MS=m
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
# CONFIG_MEMTEST is not set
# CONFIG_MEN_A21_WDT is not set
+CONFIG_MESON_CANVAS=m
CONFIG_MESON_EFUSE=m
# CONFIG_MESON_GXBB_WATCHDOG is not set
# CONFIG_MESON_GXL_PHY is not set
@@ -4936,6 +4942,9 @@ CONFIG_QCOM_IOMMU=y
CONFIG_QCOM_PDC=y
CONFIG_QCOM_PM8XXX_XOADC=m
CONFIG_QCOM_PM=y
+CONFIG_QCOM_Q6V5_ADSP=m
+CONFIG_QCOM_Q6V5_MSS=m
+CONFIG_QCOM_Q6V5_PAS=m
CONFIG_QCOM_Q6V5_PIL=m
# CONFIG_QCOM_Q6V5_WCSS is not set
CONFIG_QCOM_QFPROM=m
@@ -4946,6 +4955,7 @@ CONFIG_QCOM_SMD_RPM=m
CONFIG_QCOM_SMEM=m
CONFIG_QCOM_SMP2P=m
CONFIG_QCOM_SMSM=m
+CONFIG_QCOM_SPMI_ADC5=m
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_TEMP_ALARM=m
CONFIG_QCOM_SPMI_VADC=m
@@ -5151,6 +5161,7 @@ CONFIG_RESET_GPIO=y
# CONFIG_RESET_HSDK_V1 is not set
# CONFIG_RESET_MESON_AUDIO_ARB is not set
# CONFIG_RESET_QCOM_AOSS is not set
+CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_SIMPLE=y
# CONFIG_RESET_TI_SCI is not set
# CONFIG_RESET_TI_SYSCON is not set
@@ -7402,6 +7413,7 @@ CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_HEXIUM_GEMINI=m
CONFIG_VIDEO_HEXIUM_ORION=m
# CONFIG_VIDEO_IMX_MEDIA is not set
+CONFIG_VIDEO_IMX_PXP=m
CONFIG_VIDEO_IMX_VDOA=m
# CONFIG_VIDEO_IVTV_ALSA is not set
# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
@@ -7495,6 +7507,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-i686-debug.config b/kernel-i686-debug.config
index edf231390..4dc4cd571 100644
--- a/kernel-i686-debug.config
+++ b/kernel-i686-debug.config
@@ -158,6 +158,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -2995,6 +2997,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3074,6 +3077,7 @@ CONFIG_MAXSMP=y
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -6593,6 +6597,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-i686.config b/kernel-i686.config
index 3764b1fe6..dc248cebc 100644
--- a/kernel-i686.config
+++ b/kernel-i686.config
@@ -158,6 +158,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -2972,6 +2974,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3051,6 +3054,7 @@ CONFIG_MAX_RAW_DEVS=8192
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -6568,6 +6572,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-ppc64le-debug.config b/kernel-ppc64le-debug.config
index 17a7aec5c..a28cdbf49 100644
--- a/kernel-ppc64le-debug.config
+++ b/kernel-ppc64le-debug.config
@@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -2774,6 +2776,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -2848,6 +2851,7 @@ CONFIG_MAXSMP=y
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -6261,6 +6265,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-ppc64le.config b/kernel-ppc64le.config
index 10f195f77..3a1eaf9d6 100644
--- a/kernel-ppc64le.config
+++ b/kernel-ppc64le.config
@@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -2751,6 +2753,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -2824,6 +2827,7 @@ CONFIG_MAX_RAW_DEVS=8192
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -6234,6 +6238,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-s390x-debug.config b/kernel-s390x-debug.config
index 6d715134a..f91cb208f 100644
--- a/kernel-s390x-debug.config
+++ b/kernel-s390x-debug.config
@@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -2719,6 +2721,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -2793,6 +2796,7 @@ CONFIG_MAXSMP=y
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -6152,6 +6156,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-s390x.config b/kernel-s390x.config
index 621c2c993..f57738cd7 100644
--- a/kernel-s390x.config
+++ b/kernel-s390x.config
@@ -120,6 +120,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -2696,6 +2698,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -2769,6 +2772,7 @@ CONFIG_MAX_RAW_DEVS=8192
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -6125,6 +6129,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-x86_64-debug.config b/kernel-x86_64-debug.config
index 2dfd8914b..8045ff5cb 100644
--- a/kernel-x86_64-debug.config
+++ b/kernel-x86_64-debug.config
@@ -161,6 +161,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -3053,6 +3055,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3126,6 +3129,7 @@ CONFIG_MAXSMP=y
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -6644,6 +6648,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel-x86_64.config b/kernel-x86_64.config
index 195d03146..9197d6005 100644
--- a/kernel-x86_64.config
+++ b/kernel-x86_64.config
@@ -161,6 +161,8 @@ CONFIG_ADAPTEC_STARFIRE=m
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
@@ -3030,6 +3032,7 @@ CONFIG_LPFC_NVME_INITIATOR=y
CONFIG_LPFC_NVME_TARGET=y
CONFIG_LSI_ET1011C_PHY=m
CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTC1660=m
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
@@ -3103,6 +3106,7 @@ CONFIG_MAX_RAW_DEVS=8192
# CONFIG_MCORE2 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
+CONFIG_MCP3911=m
CONFIG_MCP4018=m
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
@@ -6619,6 +6623,7 @@ CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO=y
CONFIG_VIRTUALIZATION=y
CONFIG_VITESSE_PHY=m
+# CONFIG_VL53L0X_I2C is not set
CONFIG_VL6180=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q=m
diff --git a/kernel.spec b/kernel.spec
index af5e7f473..1bac98884 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -69,7 +69,7 @@ Summary: The Linux kernel
# The rc snapshot level
%global rcrev 0
# The git snapshot level
-%define gitrev 5
+%define gitrev 6
# Set rpm version accordingly
%define rpmversion 4.%{upstream_sublevel}.0
%endif
@@ -581,12 +581,6 @@ Patch305: qcom-msm89xx-fixes.patch
# https://patchwork.kernel.org/project/linux-mmc/list/?submitter=71861
Patch306: arm-sdhci-esdhc-imx-fixes.patch
-# https://www.spinics.net/lists/arm-kernel/msg670137.html
-Patch307: arm64-ZynqMP-firmware-clock-drivers-core.patch
-
-Patch308: arm64-96boards-Rock960-CE-board-support.patch
-Patch309: arm64-rockchip-add-initial-Rockpro64.patch
-
Patch330: bcm2835-cpufreq-add-CPU-frequency-control-driver.patch
Patch331: bcm283x-drm-vc4-set-is_yuv-to-false-when-num_planes-1.patch
@@ -1882,6 +1876,9 @@ fi
#
#
%changelog
+* Tue Oct 30 2018 Justin M. Forbes <jforbes@fedoraproject.org> - 4.20.0-0.rc0.git6.1
+- Linux v4.19-11706-g11743c56785c
+
* Mon Oct 29 2018 Justin M. Forbes <jforbes@fedoraproject.org> - 4.20.0-0.rc0.git5.1
- Linux v4.19-9448-g673c790e7282
diff --git a/sources b/sources
index 0c7c25baf..b51633461 100644
--- a/sources
+++ b/sources
@@ -1,2 +1,2 @@
SHA512 (linux-4.19.tar.xz) = ab67cc746b375a8b135e8b23e35e1d6787930d19b3c26b2679787d62951cbdbc3bb66f8ededeb9b890e5008b2459397f9018f1a6772fdef67780b06a4cb9f6f4
-SHA512 (patch-4.19-git5.xz) = cdac8f1b9408ea7a7094ce1def5f4b8f8fd54781b7b02badcd2ae5d10dd0cd67388b9b392b38f58fd87ab4f68d828153d68631f23326e958fe978414963b7948
+SHA512 (patch-4.19-git6.xz) = 1936630e0205da2c4823be3401e645b743027d2e05ab310c6a89293187b3ad3dfb891ffb2365e594317368844a63b58383d86ddd3ca2bc45a6fc7b06b32091f3