diff options
Diffstat (limited to '0003-drm-nouveau-disp-sor-gf119-both-links-use-the-same-t.patch')
| -rw-r--r-- | 0003-drm-nouveau-disp-sor-gf119-both-links-use-the-same-t.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/0003-drm-nouveau-disp-sor-gf119-both-links-use-the-same-t.patch b/0003-drm-nouveau-disp-sor-gf119-both-links-use-the-same-t.patch new file mode 100644 index 000000000..b93bdff17 --- /dev/null +++ b/0003-drm-nouveau-disp-sor-gf119-both-links-use-the-same-t.patch @@ -0,0 +1,46 @@ +From de35f524e89daf8862d49724b9045f9254bfdfea Mon Sep 17 00:00:00 2001 +From: Fedora Kernel Team <kernel-team@fedoraproject.org> +Date: Mon, 20 Jun 2016 14:52:01 +0200 +Subject: [PATCH 3/6] drm/nouveau/disp/sor/gf119: both links use the same + training register + +Upstream: drm-fixes for 4.7 (and cc'd 4.6-stable) +commit a8953c52b95167b5d21a66f0859751570271d834 + +Author: Ben Skeggs <bskeggs@redhat.com> +AuthorDate: Fri Jun 3 14:37:40 2016 +1000 +Commit: Ben Skeggs <bskeggs@redhat.com> +CommitDate: Tue Jun 7 08:11:14 2016 +1000 + + drm/nouveau/disp/sor/gf119: both links use the same training register + + It appears that, for whatever reason, both link A and B use the same + register to control the training pattern. It's a little odd, as the + GPUs before this (Tesla/Fermi1) have per-link registers, as do newer + GPUs (Maxwell). + + Fixes the third DP output on NVS 510 (GK107). + + Signed-off-by: Ben Skeggs <bskeggs@redhat.com> + Cc: stable@vger.kernel.org +--- + drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c +index b4b41b1..5111560 100644 +--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c ++++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c +@@ -40,8 +40,7 @@ static int + gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) + { + struct nvkm_device *device = outp->base.disp->engine.subdev.device; +- const u32 loff = gf119_sor_loff(outp); +- nvkm_mask(device, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); ++ nvkm_mask(device, 0x61c110, 0x0f0f0f0f, 0x01010101 * pattern); + return 0; + } + +-- +2.7.4 + |