fix i.MX6 gpu module loading, fix Jetson TX1 usb

1 files changed, 53 insertions, 0 deletions

diff --git a/usb-phy-tegra-Add-38.4MHz-clock-table-entry.patch b/usb-phy-tegra-Add-38.4MHz-clock-table-entry.patch
new file mode 100644
index 000000000..2a44851d7
--- /dev/null
+++ b/usb-phy-tegra-Add-38.4MHz-clock-table-entry.patch
@@ -0,0 +1,53 @@
+From patchwork Wed Apr  6 07:54:05 2016
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: usb: phy: tegra: Add 38.4MHz clock table entry
+From: Hunter Laux <hunterlaux@gmail.com>
+X-Patchwork-Id: 606877
+Message-Id: <1459929245-23449-1-git-send-email-hunterlaux@gmail.com>
+To: Stephen Warren <swarren@wwwdotorg.org>,
+ Thierry Reding <thierry.reding@gmail.com>,
+ Alexandre Courbot <gnurou@gmail.com>, linux-tegra@vger.kernel.org
+Cc: Hunter Laux <hunterlaux@gmail.com>
+Date: Wed,  6 Apr 2016 00:54:05 -0700
+
+The Tegra210 uses a 38.4MHz OSC. This clock table entry is required to
+use the ehci phy on the Jetson TX1.
+
+The xtal_freq_count is actually a 12 bit value, so it should be a u16
+instead of u8.
+
+Signed-off-by: Hunter Laux <hunterlaux@gmail.com>
+---
+ drivers/usb/phy/phy-tegra-usb.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c
+index 5fe4a57..f0431f0 100644
+--- a/drivers/usb/phy/phy-tegra-usb.c
++++ b/drivers/usb/phy/phy-tegra-usb.c
+@@ -164,7 +164,7 @@ struct tegra_xtal_freq {
+ 	u8 enable_delay;
+ 	u8 stable_count;
+ 	u8 active_delay;
+-	u8 xtal_freq_count;
++	u16 xtal_freq_count;
+ 	u16 debounce;
+ };
+ 
+@@ -201,6 +201,14 @@ static const struct tegra_xtal_freq tegra_freq_table[] = {
+ 		.xtal_freq_count = 0xFE,
+ 		.debounce = 0xFDE8,
+ 	},
++	{
++		.freq = 38400000,
++		.enable_delay = 0x00,
++		.stable_count = 0x00,
++		.active_delay = 0x18,
++		.xtal_freq_count = 0x177,
++		.debounce = 0xBB80,
++	},
+ };
+ 
+ static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)