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| author | Laura Abbott <labbott@fedoraproject.org> | 2016-12-15 15:35:40 -0800 |
|---|---|---|
| committer | Laura Abbott <labbott@fedoraproject.org> | 2016-12-15 15:35:40 -0800 |
| commit | 68eebd5c343394f45361e9e3732cfbb8a3e32e32 (patch) | |
| tree | 5c2ba83f864fd69c4e7620c6983b8814b11a919d /qcom-QDF2432-tmp-errata.patch | |
| parent | 5de569a890be505e0ec46d2b1c9691f0405a17c6 (diff) | |
| download | kernel-68eebd5c343394f45361e9e3732cfbb8a3e32e32.tar.gz kernel-68eebd5c343394f45361e9e3732cfbb8a3e32e32.tar.xz kernel-68eebd5c343394f45361e9e3732cfbb8a3e32e32.zip | |
Linux v4.9 rebase
Diffstat (limited to 'qcom-QDF2432-tmp-errata.patch')
| -rw-r--r-- | qcom-QDF2432-tmp-errata.patch | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/qcom-QDF2432-tmp-errata.patch b/qcom-QDF2432-tmp-errata.patch new file mode 100644 index 000000000..f7ace4787 --- /dev/null +++ b/qcom-QDF2432-tmp-errata.patch @@ -0,0 +1,59 @@ +From edc7986d4d405daebaf2f66269b353da579fce5f Mon Sep 17 00:00:00 2001 +From: Christopher Covington <cov@codeaurora.org> +Date: Tue, 31 May 2016 16:19:02 -0400 +Subject: arm64: Workaround for QDF2432 ID_AA64 SR accesses + +The ARMv8.0 architecture reserves several system register encodings for +future use. These encodings should behave as read-only and always return +zero on a read. As described in Errata 94, the CPU cores in the QDF2432 +errantly cause an instruction abort if an AArch64 MRS instruction attempts +to read any of the following system register encodings: + + Op0, Op1, CRn, CRm, Op2 + 3, 0, C0, [C4-C7], [2-3, 6-7] + 3, 0, C0, C3, [3-7] + 3, 0, C0, [C4,C6,C7], [4-5] + 3, 0, C0, C2, [6-7] + +Naively projecting ARMv8.0 names, this space includes: + + ID_AA64PFR[2-7]_EL1 + ID_AA64DFR[2-3]_EL1 + ID_AA64AFR[2-3]_EL1 + ID_AA64ISAR[2-7]_EL1 + ID_AA64MMFR[2-7]_EL1 + +As of v4.8-rc2, Linux only attempts to query one register in this space, +ID_AA64MMFR2_EL1. As simple workaround, skip that access when the affected +MIDR is detected. + +Signed-off-by: Christopher Covington <cov@codeaurora.org> +--- + arch/arm64/kernel/cpuinfo.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c +index ed1b84f..790de6b 100644 +--- a/arch/arm64/kernel/cpuinfo.c ++++ b/arch/arm64/kernel/cpuinfo.c +@@ -325,6 +325,8 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) + + static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) + { ++ bool qdf2432_cpu = read_cpuid_id() == 0x510f2811; ++ + info->reg_cntfrq = arch_timer_get_cntfrq(); + info->reg_ctr = read_cpuid_cachetype(); + info->reg_dczid = read_cpuid(DCZID_EL0); +@@ -337,7 +339,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) + info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); + info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); + info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); +- info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); ++ info->reg_id_aa64mmfr2 = qdf2432_cpu ? 0 : read_cpuid(ID_AA64MMFR2_EL1); + info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); + info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); + +-- +cgit v0.12 + |