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authorJustin M. Forbes <jforbes@redhat.com>2016-12-15 08:36:44 -0600
committerJustin M. Forbes <jforbes@redhat.com>2016-12-15 08:36:44 -0600
commit188bddcce08626d1cba389e1586c397df63dfdf4 (patch)
tree36239a251e3fe27b7487a7f5ccf6848e16d218a1 /kvm-nVMX-allow-L1-to-intercept-software-exceptions.patch
parentb3839d9074a75b2a91091fa39d82a8b7fc5ffbbf (diff)
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CVE-2016-9588 fix possible DoS in nVMX (rhbz 1404924 1404925)
Diffstat (limited to 'kvm-nVMX-allow-L1-to-intercept-software-exceptions.patch')
-rw-r--r--kvm-nVMX-allow-L1-to-intercept-software-exceptions.patch68
1 files changed, 68 insertions, 0 deletions
diff --git a/kvm-nVMX-allow-L1-to-intercept-software-exceptions.patch b/kvm-nVMX-allow-L1-to-intercept-software-exceptions.patch
new file mode 100644
index 000000000..b408fc604
--- /dev/null
+++ b/kvm-nVMX-allow-L1-to-intercept-software-exceptions.patch
@@ -0,0 +1,68 @@
+From: Jim Mattson <jmattson@google.com>
+To: kvm@vger.kernel.org
+Cc: Jim Mattson <jmattson@google.com>
+Subject: [PATCH] kvm: nVMX: Allow L1 to intercept software exceptions (#BP and #OF)
+Date: Wed, 14 Dec 2016 11:41:59 -0800
+
+When L2 exits to L0 due to "exception or NMI", software exceptions
+(#BP and #OF) for which L1 has requested an intercept should be
+handled by L1 rather than L0. Previously, only hardware exceptions
+were forwarded to L1.
+
+Signed-off-by: Jim Mattson <jmattson@google.com>
+---
+ arch/x86/kvm/vmx.c | 11 +++++------
+ 1 file changed, 5 insertions(+), 6 deletions(-)
+
+diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
+index 5382b82..64774f4 100644
+--- a/arch/x86/kvm/vmx.c
++++ b/arch/x86/kvm/vmx.c
+@@ -1343,10 +1343,10 @@ static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
+ return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
+ }
+
+-static inline bool is_exception(u32 intr_info)
++static inline bool is_nmi(u32 intr_info)
+ {
+ return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
+- == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
++ == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
+ }
+
+ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
+@@ -5476,7 +5476,7 @@ static int handle_exception(struct kvm_vcpu *vcpu)
+ if (is_machine_check(intr_info))
+ return handle_machine_check(vcpu);
+
+- if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
++ if (is_nmi(intr_info))
+ return 1; /* already handled by vmx_vcpu_run() */
+
+ if (is_no_device(intr_info)) {
+@@ -8018,7 +8018,7 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
+
+ switch (exit_reason) {
+ case EXIT_REASON_EXCEPTION_NMI:
+- if (!is_exception(intr_info))
++ if (is_nmi(intr_info))
+ return false;
+ else if (is_page_fault(intr_info))
+ return enable_ept;
+@@ -8611,8 +8611,7 @@ static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
+ kvm_machine_check();
+
+ /* We need to handle NMIs before interrupts are enabled */
+- if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
+- (exit_intr_info & INTR_INFO_VALID_MASK)) {
++ if (is_nmi(exit_intr_info)) {
+ kvm_before_handle_nmi(&vmx->vcpu);
+ asm("int $2");
+ kvm_after_handle_nmi(&vmx->vcpu);
+--
+2.8.0.rc3.226.g39d4020
+
+--
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