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| author | Peter Jones <pjones@redhat.com> | 2018-11-30 14:36:02 -0500 |
|---|---|---|
| committer | Peter Jones <pjones@redhat.com> | 2018-11-30 14:36:02 -0500 |
| commit | fe9e33a8873b2c30e54ac7b1f34e8aab081f35cf (patch) | |
| tree | 12be6ca935c52a995307cf0cc9c258467a04b1b9 /kernel-x86_64.config | |
| parent | f8216ee47abe1997e9fc7efb3d819d6105d898f5 (diff) | |
| download | kernel-fe9e33a8873b2c30e54ac7b1f34e8aab081f35cf.tar.gz kernel-fe9e33a8873b2c30e54ac7b1f34e8aab081f35cf.tar.xz kernel-fe9e33a8873b2c30e54ac7b1f34e8aab081f35cf.zip | |
Re-enable CONFIG_CRYPTO_DEV_SP_PSP so I can work on SEV stuff.
Waaay back in October, we saw some issues with various system firmware
talking to the AMD SP PSP devices (the secure processor feature), and so
CONFIG_CRYPTO_DEV_SP_PSP got disabled in all of our kernel trees, as
Laura noted here: https://bugzilla.redhat.com/show_bug.cgi?id=1608242#c44 .
I'm trying to use it, and this obviously makes that impossible to do, so
I'm going to re-enable it in rawhide, because the timeout that's being
discussed in that bugzilla thread is already there, and so this firmware
bugs people saw before shouldn't make things completely unusable.
If you *do* see debilitating stalls on AMD EPYC hardware starting after
the next rawhide build, make some noise so we can disable it again.
(I've also posted this to kernel@l.fp.o: https://lists.fedoraproject.org/archives/list/kernel@lists.fedoraproject.org/thread/22XCMRU4R75M4D5OSXE7YMWYVOBQIU2M/ )
Signed-off-by: Peter Jones <pjones@redhat.com>
Diffstat (limited to 'kernel-x86_64.config')
| -rw-r--r-- | kernel-x86_64.config | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel-x86_64.config b/kernel-x86_64.config index 6eabdf973..5dd8d004c 100644 --- a/kernel-x86_64.config +++ b/kernel-x86_64.config @@ -975,7 +975,7 @@ CONFIG_CRYPTO_DEV_QAT_C62XVF=m CONFIG_CRYPTO_DEV_QAT_DH895xCC=m CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m # CONFIG_CRYPTO_DEV_SP_CCP is not set -# CONFIG_CRYPTO_DEV_SP_PSP is not set +CONFIG_CRYPTO_DEV_SP_PSP=y CONFIG_CRYPTO_DEV_VIRTIO=m CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DRBG_CTR=y |