Linux v5.5.6 rebase

1 files changed, 232 insertions, 0 deletions

diff --git a/bcm2835-irqchip-Quiesce-IRQs-left-enabled-by-bootloader.patch b/bcm2835-irqchip-Quiesce-IRQs-left-enabled-by-bootloader.patch
new file mode 100644
index 000000000..9cb8ff5d7
--- /dev/null
+++ b/bcm2835-irqchip-Quiesce-IRQs-left-enabled-by-bootloader.patch
@@ -0,0 +1,232 @@
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+From: Lukas Wunner <lukas@wunner.de>
+Date: Mon, 10 Feb 2020 10:52:20 +0100
+Subject: [PATCH v2] irqchip/bcm2835: Quiesce IRQs left enabled by bootloader
+To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>,
+ Marc Zyngier <maz@kernel.org>,
+ "Nicolas Saenz Julienne" <nsaenzjulienne@suse.de>
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+
+Customers of our "Revolution Pi" open source PLCs (which are based on
+the Raspberry Pi) have reported random lockups as well as jittery eMMC,
+UART and SPI latency.  We were able to reproduce the lockups in our lab
+and hooked up a JTAG debugger:
+
+It turns out that the USB controller's interrupt is already enabled when
+the kernel boots.  All interrupts are disabled when the chip comes out
+of power-on reset, according to the spec.  So apparently the bootloader
+enables the interrupt but neglects to disable it before handing over
+control to the kernel.
+
+The bootloader is a closed source blob provided by the Raspberry Pi
+Foundation.  Development of an alternative open source bootloader was
+begun by Kristina Brooks but it's not fully functional yet.  Usage of
+the blob is thus without alternative for the time being.
+
+The Raspberry Pi Foundation's downstream kernel has a performance-
+optimized USB driver (which we use on our Revolution Pi products).
+The driver takes advantage of the FIQ fast interrupt.  Because the
+regular USB interrupt was left enabled by the bootloader, both the
+FIQ and the normal interrupt is enabled once the USB driver probes.
+
+The spec has the following to say on simultaneously enabling the FIQ
+and the normal interrupt of a peripheral:
+
+"One interrupt source can be selected to be connected to the ARM FIQ
+ input.  An interrupt which is selected as FIQ should have its normal
+ interrupt enable bit cleared.  Otherwise a normal and an FIQ interrupt
+ will be fired at the same time.  Not a good idea!"
+                                  ^^^^^^^^^^^^^^^
+https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
+page 110
+
+On a multicore Raspberry Pi, the Foundation's kernel routes all normal
+interrupts to CPU 0 and the FIQ to CPU 1.  Because both the FIQ and the
+normal interrupt is enabled, a USB interrupt causes CPU 0 to spin in
+bcm2836_chained_handle_irq() until the FIQ on CPU 1 has cleared it.
+Interrupts with a lower priority than USB are starved as long.
+
+That explains the jittery eMMC, UART and SPI latency:  On one occasion
+I've seen CPU 0 blocked for no less than 2.9 msec.  Basically,
+everything not USB takes a performance hit:  Whereas eMMC throughput
+on a Compute Module 3 remains relatively constant at 23.5 MB/s with
+this commit, it irregularly dips to 23.0 MB/s without this commit.
+
+The lockups occur when CPU 0 receives a USB interrupt while holding a
+lock which CPU 1 is trying to acquire while the FIQ is temporarily
+disabled on CPU 1.
+
+I've tested old releases of the Foundation's bootloader as far back as
+1.20160202-1 and they all leave the USB interrupt enabled.  Still older
+releases fail to boot a contemporary kernel on a Compute Module 1 or 3,
+which are the only Raspberry Pi variants I have at my disposal for
+testing.
+
+Fix by disabling IRQs left enabled by the bootloader.  Although the
+impact is most pronounced on the Foundation's downstream kernel,
+it seems prudent to apply the fix to the upstream kernel to guard
+against such mistakes in any present and future bootloader.
+
+Signed-off-by: Lukas Wunner <lukas@wunner.de>
+Cc: Serge Schneider <serge@raspberrypi.org>
+Cc: Kristina Brooks <notstina@gmail.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+Changes since v1:
+* Use "relaxed" MMIO accessors to avoid memory barriers (Marc)
+* Use u32 instead of int for register access (Marc)
+* Quiesce FIQ as well (Marc)
+* Quiesce IRQs after mapping them for better readability
+* Drop alternative approach from commit message (Marc)
+
+Link to v1:
+https://lore.kernel.org/lkml/988737dbbc4e499c2faaaa4e567ba3ed8deb9a89.1581089797.git.lukas@wunner.de/
+
+ drivers/irqchip/irq-bcm2835.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c
+index 418245d31921..63539c88ac3a 100644
+--- a/drivers/irqchip/irq-bcm2835.c
++++ b/drivers/irqchip/irq-bcm2835.c
+@@ -61,6 +61,7 @@
+ 					| SHORTCUT1_MASK | SHORTCUT2_MASK)
+ 
+ #define REG_FIQ_CONTROL		0x0c
++#define REG_FIQ_ENABLE		0x80
+ 
+ #define NR_BANKS		3
+ #define IRQS_PER_BANK		32
+@@ -135,6 +136,7 @@ static int __init armctrl_of_init(struct device_node *node,
+ {
+ 	void __iomem *base;
+ 	int irq, b, i;
++	u32 reg;
+ 
+ 	base = of_iomap(node, 0);
+ 	if (!base)
+@@ -157,6 +159,19 @@ static int __init armctrl_of_init(struct device_node *node,
+ 				handle_level_irq);
+ 			irq_set_probe(irq);
+ 		}
++
++		reg = readl_relaxed(intc.enable[b]);
++		if (reg) {
++			writel_relaxed(reg, intc.disable[b]);
++			pr_err(FW_BUG "Bootloader left irq enabled: "
++			       "bank %d irq %*pbl\n", b, IRQS_PER_BANK, &reg);
++		}
++	}
++
++	reg = readl_relaxed(base + REG_FIQ_CONTROL);
++	if (reg & REG_FIQ_ENABLE) {
++		writel_relaxed(0, base + REG_FIQ_CONTROL);
++		pr_err(FW_BUG "Bootloader left fiq enabled\n");
+ 	}
+ 
+ 	if (is_2836) {