Raspberry Pi DT updates, Update AllWinner A64 timer errata workaround

9 files changed, 1668 insertions, 481 deletions

diff --git a/ARM-dts-bcm283x-Several-DTS-improvements.patch b/ARM-dts-bcm283x-Several-DTS-improvements.patch
new file mode 100644
index 000000000..807903afa
--- /dev/null
+++ b/ARM-dts-bcm283x-Several-DTS-improvements.patch
@@ -0,0 +1,1130 @@
+From patchwork Sat Jan 12 12:43:23 2019
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+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
+ Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>, Eric Anholt <eric@anholt.net>
+Subject: [PATCH 1/6] ARM: dts: bcm283x: Fix DTC warning for memory node
+Date: Sat, 12 Jan 2019 13:43:23 +0100
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+Cc: Gottfried Haider <gottfried.haider@gmail.com>, devicetree@vger.kernel.org,
+ Stefan Wahren <stefan.wahren@i2se.com>, Phil Elwell <phil@raspberrypi.org>,
+ bcm-kernel-feedback-list@broadcom.com, Peter Robinson <pbrobinson@gmail.com>,
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+Compiling the bcm283x DTS with W=1 leads to the following warning:
+
+Warning (unit_address_vs_reg): /memory: node has a reg or ranges property,
+but no unit name
+
+Fix this by adding the unit address.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ arch/arm/boot/dts/bcm2835-rpi.dtsi         | 2 +-
+ arch/arm/boot/dts/bcm2836-rpi-2-b.dts      | 2 +-
+ arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 2 +-
+ arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 2 +-
+ arch/arm/boot/dts/bcm2837-rpi-3-b.dts      | 2 +-
+ arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi     | 2 +-
+ 6 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
+index c6e2b23..e490f2a 100644
+--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
++++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
+@@ -1,7 +1,7 @@
+ #include <dt-bindings/power/raspberrypi-power.h>
+ 
+ / {
+-	memory {
++	memory@0 {
+ 		device_type = "memory";
+ 		reg = <0 0x10000000>;
+ 	};
+diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+index ac4408b..871fc4a 100644
+--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
++++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+@@ -9,7 +9,7 @@
+ 	compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
+ 	model = "Raspberry Pi 2 Model B";
+ 
+-	memory {
++	memory@0 {
+ 		reg = <0 0x40000000>;
+ 	};
+ 
+diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
+index e9fadd3..7f4437a 100644
+--- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
++++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
+@@ -13,7 +13,7 @@
+ 		stdout-path = "serial1:115200n8";
+ 	};
+ 
+-	memory {
++	memory@0 {
+ 		reg = <0 0x20000000>;
+ 	};
+ 
+diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+index 42bb090..7d65013 100644
+--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
++++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+@@ -14,7 +14,7 @@
+ 		stdout-path = "serial1:115200n8";
+ 	};
+ 
+-	memory {
++	memory@0 {
+ 		reg = <0 0x40000000>;
+ 	};
+ 
+diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+index 0c155dd..9abb9c5 100644
+--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
++++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+@@ -14,7 +14,7 @@
+ 		stdout-path = "serial1:115200n8";
+ 	};
+ 
+-	memory {
++	memory@0 {
+ 		reg = <0 0x40000000>;
+ 	};
+ 
+diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
+index 4a89a18..81399b2 100644
+--- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
++++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
+@@ -4,7 +4,7 @@
+ #include "bcm2836-rpi.dtsi"
+ 
+ / {
+-	memory {
++	memory@0 {
+ 		reg = <0 0x40000000>;
+ 	};
+ 
+
+From patchwork Sat Jan 12 12:43:24 2019
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+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
+ Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
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+Subject: [PATCH 2/6] ARM: dts: bcm2835-rpi: Drop unnecessary
+ #address-cells/#size-cells
+Date: Sat, 12 Jan 2019 13:43:24 +0100
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+Compiling the bcm2835-rpi.dtsi with W=1 leads to the following warning:
+
+Warning (avoid_unnecessary_addr_size): /soc/firmware: unnecessary
+ #address-cells/#size-cells without "ranges" or child "reg" property
+
+Fix this by removing these unnecessary properties.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
+index e490f2a..715d50c 100644
+--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
++++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
+@@ -19,8 +19,6 @@
+ 	soc {
+ 		firmware: firmware {
+ 			compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
+-			#address-cells = <0>;
+-			#size-cells = <0>;
+ 			mboxes = <&mailbox>;
+ 		};
+ 
+
+From patchwork Sat Jan 12 12:43:25 2019
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+ id 1N49Qd-1hPmUb47ST-0101Wy; Sat, 12 Jan 2019 13:44:01 +0100
+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
+ Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>, Eric Anholt <eric@anholt.net>
+Subject: [PATCH 3/6] ARM: dts: bcm2835: Fix labels for GPIO 0,1
+Date: Sat, 12 Jan 2019 13:43:25 +0100
+Message-Id: <1547297008-2740-4-git-send-email-stefan.wahren@i2se.com>
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+Cc: Gottfried Haider <gottfried.haider@gmail.com>, devicetree@vger.kernel.org,
+ Stefan Wahren <stefan.wahren@i2se.com>, Phil Elwell <phil@raspberrypi.org>,
+ bcm-kernel-feedback-list@broadcom.com, Peter Robinson <pbrobinson@gmail.com>,
+ linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org
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+
+According to the schematics for all RPis with a 40 pin header,
+the GPIOs 0 and 1 are labeled as ID_SD and ID_SC. In order to
+clarify that is a I2C bus, append the third letter.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 4 ++--
+ arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 4 ++--
+ arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 4 ++--
+ arch/arm/boot/dts/bcm2835-rpi-zero.dts   | 4 ++--
+ 4 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+index 2cd9c5e..db8a601 100644
+--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
++++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+@@ -31,8 +31,8 @@
+ 	 * "FOO" = GPIO line named "FOO" on the schematic
+ 	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ 	 */
+-	gpio-line-names = "SDA0",
+-			  "SCL0",
++	gpio-line-names = "ID_SDA",
++			  "ID_SCL",
+ 			  "SDA1",
+ 			  "SCL1",
+ 			  "GPIO_GCLK",
+diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+index cfbdaac..1e40d67 100644
+--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
++++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+@@ -33,8 +33,8 @@
+ 	 * "FOO" = GPIO line named "FOO" on the schematic
+ 	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ 	 */
+-	gpio-line-names = "SDA0",
+-			  "SCL0",
++	gpio-line-names = "ID_SDA",
++			  "ID_SCL",
+ 			  "SDA1",
+ 			  "SCL1",
+ 			  "GPIO_GCLK",
+diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+index 644d907..5765d34 100644
+--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
++++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+@@ -40,8 +40,8 @@
+ 	 * "FOO" = GPIO line named "FOO" on the schematic
+ 	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ 	 */
+-	gpio-line-names = "GPIO0",
+-			  "GPIO1",
++	gpio-line-names = "ID_SDA",
++			  "ID_SCL",
+ 			  "SDA1",
+ 			  "SCL1",
+ 			  "GPIO_GCLK",
+diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+index 00323ba..3b35a8a 100644
+--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
++++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+@@ -28,8 +28,8 @@
+ 	 * "FOO" = GPIO line named "FOO" on the schematic
+ 	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ 	 */
+-	gpio-line-names = "SDA0",
+-			  "SCL0",
++	gpio-line-names = "ID_SDA",
++			  "ID_SCL",
+ 			  "SDA1",
+ 			  "SCL1",
+ 			  "GPIO_GCLK",
+
+From patchwork Sat Jan 12 12:43:26 2019
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+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
+ Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>, Eric Anholt <eric@anholt.net>
+Subject: [PATCH 4/6] ARM: dts: bcm2837-rpi-3-b: Use consistent label for HDMI
+ hotplug
+Date: Sat, 12 Jan 2019 13:43:26 +0100
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+This make the GPIO label for HDMI hotplug more consistent to the other
+boards.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+index 9abb9c5..31b1c03 100644
+--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
++++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+@@ -39,7 +39,7 @@
+ 				  "WL_ON",
+ 				  "STATUS_LED",
+ 				  "LAN_RUN",
+-				  "HPD_N",
++				  "HDMI_HPD_N",
+ 				  "CAM_GPIO0",
+ 				  "CAM_GPIO1",
+ 				  "PWR_LOW_N";
+
+From patchwork Sat Jan 12 12:43:27 2019
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+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
+ Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>, Eric Anholt <eric@anholt.net>
+Subject: [PATCH 5/6] ARM: dts: bcm2837-rpi-3-b-plus: Clarify label for
+ STATUS_LED
+Date: Sat, 12 Jan 2019 13:43:27 +0100
+Message-Id: <1547297008-2740-6-git-send-email-stefan.wahren@i2se.com>
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+Cc: Gottfried Haider <gottfried.haider@gmail.com>, devicetree@vger.kernel.org,
+ Stefan Wahren <stefan.wahren@i2se.com>, Phil Elwell <phil@raspberrypi.org>,
+ bcm-kernel-feedback-list@broadcom.com, Peter Robinson <pbrobinson@gmail.com>,
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+The RPI 3 B+ provides control to both LEDs (PWR and ACT). So append
+the first letter of the LED color (like in the schematics) in order
+to clarify this.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+index 7d65013..d3ec6cd 100644
+--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
++++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+@@ -42,7 +42,7 @@
+ 		#gpio-cells = <2>;
+ 		gpio-line-names = "BT_ON",
+ 				  "WL_ON",
+-				  "STATUS_LED",
++				  "STATUS_LED_R",
+ 				  "LAN_RUN",
+ 				  "",
+ 				  "CAM_GPIO0",
+
+From patchwork Sat Jan 12 12:43:28 2019
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+ id 1MdNLi-1hHMPa2aSu-00ZS8f; Sat, 12 Jan 2019 13:44:02 +0100
+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
+ Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>, Eric Anholt <eric@anholt.net>
+Subject: [PATCH 6/6] ARM: dts: bcm283x: Add missing GPIO line names
+Date: Sat, 12 Jan 2019 13:43:28 +0100
+Message-Id: <1547297008-2740-7-git-send-email-stefan.wahren@i2se.com>
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+Cc: Gottfried Haider <gottfried.haider@gmail.com>, devicetree@vger.kernel.org,
+ Stefan Wahren <stefan.wahren@i2se.com>, Phil Elwell <phil@raspberrypi.org>,
+ bcm-kernel-feedback-list@broadcom.com, Peter Robinson <pbrobinson@gmail.com>,
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+
+The GPIO sysfs is deprecated and disabled in the defconfig files.
+So in order to motivate the usage of the new GPIO character device API
+add the missing GPIO line names for Raspberry Pi 2 and 3. In the lack
+of full schematics i would leave all undocumented pins as unnamed.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ arch/arm/boot/dts/bcm2836-rpi-2-b.dts      | 66 ++++++++++++++++++++++++++++
+ arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 70 ++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/bcm2837-rpi-3-b.dts      | 70 ++++++++++++++++++++++++++++++
+ 3 files changed, 206 insertions(+)
+
+diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+index 871fc4a..7b4e651 100644
+--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
++++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+@@ -28,6 +28,72 @@
+ };
+ 
+ &gpio {
++	/*
++	 * Taken from rpi_SCH_2b_1p2_reduced.pdf and
++	 * the official GPU firmware DT blob.
++	 *
++	 * Legend:
++	 * "NC" = not connected (no rail from the SoC)
++	 * "FOO" = GPIO line named "FOO" on the schematic
++	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
++	 */
++	gpio-line-names = "ID_SDA",
++			  "ID_SCL",
++			  "SDA1",
++			  "SCL1",
++			  "GPIO_GCLK",
++			  "GPIO5",
++			  "GPIO6",
++			  "SPI_CE1_N",
++			  "SPI_CE0_N",
++			  "SPI_MISO",
++			  "SPI_MOSI",
++			  "SPI_SCLK",
++			  "GPIO12",
++			  "GPIO13",
++			  /* Serial port */
++			  "TXD0",
++			  "RXD0",
++			  "GPIO16",
++			  "GPIO17",
++			  "GPIO18",
++			  "GPIO19",
++			  "GPIO20",
++			  "GPIO21",
++			  "GPIO22",
++			  "GPIO23",
++			  "GPIO24",
++			  "GPIO25",
++			  "GPIO26",
++			  "GPIO27",
++			  "SDA0",
++			  "SCL0",
++			  "", /* GPIO30 */
++			  "LAN_RUN",
++			  "CAM_GPIO1",
++			  "", /* GPIO33 */
++			  "", /* GPIO34 */
++			  "PWR_LOW_N",
++			  "", /* GPIO36 */
++			  "", /* GPIO37 */
++			  "USB_LIMIT",
++			  "", /* GPIO39 */
++			  "PWM0_OUT",
++			  "CAM_GPIO0",
++			  "SMPS_SCL",
++			  "SMPS_SDA",
++			  "ETHCLK",
++			  "PWM1_OUT",
++			  "HDMI_HPD_N",
++			  "STATUS_LED",
++			  /* Used by SD Card */
++			  "SD_CLK_R",
++			  "SD_CMD_R",
++			  "SD_DATA0_R",
++			  "SD_DATA1_R",
++			  "SD_DATA2_R",
++			  "SD_DATA3_R";
++
+ 	pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
+ 
+ 	/* I2S interface */
+diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+index d3ec6cd..c6fa34c 100644
+--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
++++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+@@ -52,6 +52,76 @@
+ 	};
+ };
+ 
++&gpio {
++	/*
++	 * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and
++	 * the official GPU firmware DT blob.
++	 *
++	 * Legend:
++	 * "NC" = not connected (no rail from the SoC)
++	 * "FOO" = GPIO line named "FOO" on the schematic
++	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
++	 */
++	gpio-line-names = "ID_SDA",
++			  "ID_SCL",
++			  "SDA1",
++			  "SCL1",
++			  "GPIO_GCLK",
++			  "GPIO5",
++			  "GPIO6",
++			  "SPI_CE1_N",
++			  "SPI_CE0_N",
++			  "SPI_MISO",
++			  "SPI_MOSI",
++			  "SPI_SCLK",
++			  "GPIO12",
++			  "GPIO13",
++			  /* Serial port */
++			  "TXD1",
++			  "RXD1",
++			  "GPIO16",
++			  "GPIO17",
++			  "GPIO18",
++			  "GPIO19",
++			  "GPIO20",
++			  "GPIO21",
++			  "GPIO22",
++			  "GPIO23",
++			  "GPIO24",
++			  "GPIO25",
++			  "GPIO26",
++			  "GPIO27",
++			  "HDMI_HPD_N",
++			  "STATUS_LED_G",
++			  /* Used by BT module */
++			  "CTS0",
++			  "RTS0",
++			  "TXD0",
++			  "RXD0",
++			  /* Used by Wifi */
++			  "SD1_CLK",
++			  "SD1_CMD",
++			  "SD1_DATA0",
++			  "SD1_DATA1",
++			  "SD1_DATA2",
++			  "SD1_DATA3",
++			  "PWM0_OUT",
++			  "PWM1_OUT",
++			  "ETHCLK",
++			  "WIFI_CLK",
++			  "SDA0",
++			  "SCL0",
++			  "SMPS_SCL",
++			  "SMPS_SDA",
++			  /* Used by SD Card */
++			  "SD_CLK_R",
++			  "SD_CMD_R",
++			  "SD_DATA0_R",
++			  "SD_DATA1_R",
++			  "SD_DATA2_R",
++			  "SD_DATA3_R";
++};
++
+ &hdmi {
+ 	hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+ };
+diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+index 31b1c03..ce71f57 100644
+--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
++++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+@@ -47,6 +47,76 @@
+ 	};
+ };
+ 
++&gpio {
++	/*
++	 * Taken from rpi_SCH_3b_1p2_reduced.pdf and
++	 * the official GPU firmware DT blob.
++	 *
++	 * Legend:
++	 * "NC" = not connected (no rail from the SoC)
++	 * "FOO" = GPIO line named "FOO" on the schematic
++	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
++	 */
++	gpio-line-names = "ID_SDA",
++			  "ID_SCL",
++			  "SDA1",
++			  "SCL1",
++			  "GPIO_GCLK",
++			  "GPIO5",
++			  "GPIO6",
++			  "SPI_CE1_N",
++			  "SPI_CE0_N",
++			  "SPI_MISO",
++			  "SPI_MOSI",
++			  "SPI_SCLK",
++			  "GPIO12",
++			  "GPIO13",
++			  /* Serial port */
++			  "TXD1",
++			  "RXD1",
++			  "GPIO16",
++			  "GPIO17",
++			  "GPIO18",
++			  "GPIO19",
++			  "GPIO20",
++			  "GPIO21",
++			  "GPIO22",
++			  "GPIO23",
++			  "GPIO24",
++			  "GPIO25",
++			  "GPIO26",
++			  "GPIO27",
++			  "", /* GPIO 28 */
++			  "LAN_RUN_BOOT",
++			  /* Used by BT module */
++			  "CTS0",
++			  "RTS0",
++			  "TXD0",
++			  "RXD0",
++			  /* Used by Wifi */
++			  "SD1_CLK",
++			  "SD1_CMD",
++			  "SD1_DATA0",
++			  "SD1_DATA1",
++			  "SD1_DATA2",
++			  "SD1_DATA3",
++			  "PWM0_OUT",
++			  "PWM1_OUT",
++			  "ETHCLK",
++			  "WIFI_CLK",
++			  "SDA0",
++			  "SCL0",
++			  "SMPS_SCL",
++			  "SMPS_SDA",
++			  /* Used by SD Card */
++			  "SD_CLK_R",
++			  "SD_CMD_R",
++			  "SD_DATA0_R",
++			  "SD_DATA1_R",
++			  "SD_DATA2_R",
++			  "SD_DATA3_R";
++};
++
+ &pwm {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
diff --git a/Allwinner-A64-timer-workaround.patch b/Allwinner-A64-timer-workaround.patch
new file mode 100644
index 000000000..4e5c3482d
--- /dev/null
+++ b/Allwinner-A64-timer-workaround.patch
@@ -0,0 +1,527 @@
+From patchwork Sun Jan 13 02:17:18 2019
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+ Sat, 12 Jan 2019 21:17:21 -0500 (EST)
+From: Samuel Holland <samuel@sholland.org>
+To: Catalin Marinas <catalin.marinas@arm.com>,
+ Will Deacon <will.deacon@arm.com>,
+ Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
+ Rob Herring <robh+dt@kernel.org>, Mark Rutland <Mark.Rutland@arm.com>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
+Subject: [PATCH v3 1/2] arm64: arch_timer: Workaround for Allwinner A64 timer
+ instability
+Date: Sat, 12 Jan 2019 20:17:18 -0600
+Message-Id: <20190113021719.46457-2-samuel@sholland.org>
+X-Mailer: git-send-email 2.19.2
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+References: <20190113021719.46457-1-samuel@sholland.org>
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+
+The Allwinner A64 SoC is known[1] to have an unstable architectural
+timer, which manifests itself most obviously in the time jumping forward
+a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a
+timer frequency of 24 MHz, implying that the time went slightly backward
+(and this was interpreted by the kernel as it jumping forward and
+wrapping around past the epoch).
+
+Investigation revealed instability in the low bits of CNTVCT at the
+point a high bit rolls over. This leads to power-of-two cycle forward
+and backward jumps. (Testing shows that forward jumps are about twice as
+likely as backward jumps.) Since the counter value returns to normal
+after an indeterminate read, each "jump" really consists of both a
+forward and backward jump from the software perspective.
+
+Unless the kernel is trapping CNTVCT reads, a userspace program is able
+to read the register in a loop faster than it changes. A test program
+running on all 4 CPU cores that reported jumps larger than 100 ms was
+run for 13.6 hours and reported the following:
+
+ Count | Event
+-------+---------------------------
+  9940 | jumped backward      699ms
+   268 | jumped backward     1398ms
+     1 | jumped backward     2097ms
+ 16020 | jumped forward       175ms
+  6443 | jumped forward       699ms
+  2976 | jumped forward      1398ms
+     9 | jumped forward    356516ms
+     9 | jumped forward    357215ms
+     4 | jumped forward    714430ms
+     1 | jumped forward   3578440ms
+
+This works out to a jump larger than 100 ms about every 5.5 seconds on
+each CPU core.
+
+The largest jump (almost an hour!) was the following sequence of reads:
+    0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000
+
+Note that the middle bits don't necessarily all read as all zeroes or
+all ones during the anomalous behavior; however the low 10 bits checked
+by the function in this patch have never been observed with any other
+value.
+
+Also note that smaller jumps are much more common, with backward jumps
+of 2048 (2^11) cycles observed over 400 times per second on each core.
+(Of course, this is partially explained by lower bits rolling over more
+frequently.) Any one of these could have caused the 95 year time skip.
+
+Similar anomalies were observed while reading CNTPCT (after patching the
+kernel to allow reads from userspace). However, the CNTPCT jumps are
+much less frequent, and only small jumps were observed. The same program
+as before (except now reading CNTPCT) observed after 72 hours:
+
+ Count | Event
+-------+---------------------------
+    17 | jumped backward      699ms
+    52 | jumped forward       175ms
+  2831 | jumped forward       699ms
+     5 | jumped forward      1398ms
+
+Further investigation showed that the instability in CNTPCT/CNTVCT also
+affected the respective timer's TVAL register. The following values were
+observed immediately after writing CNVT_TVAL to 0x10000000:
+
+ CNTVCT             | CNTV_TVAL  | CNTV_CVAL          | CNTV_TVAL Error
+--------------------+------------+--------------------+-----------------
+ 0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000
+ 0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000
+ 0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000
+ 0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000
+
+The pattern of errors in CNTV_TVAL seemed to depend on exactly which
+value was written to it. For example, after writing 0x10101010:
+
+ CNTVCT             | CNTV_TVAL  | CNTV_CVAL          | CNTV_TVAL Error
+--------------------+------------+--------------------+-----------------
+ 0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000
+ 0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000
+ 0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000
+ 0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000
+ 0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000
+ 0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000
+
+I was also twice able to reproduce the issue covered by Allwinner's
+workaround[4], that writing to TVAL sometimes fails, and both CVAL and
+TVAL are left with entirely bogus values. One was the following values:
+
+ CNTVCT             | CNTV_TVAL  | CNTV_CVAL
+--------------------+------------+--------------------------------------
+ 0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past)
+
+========================================================================
+
+Because the CPU can read the CNTPCT/CNTVCT registers faster than they
+change, performing two reads of the register and comparing the high bits
+(like other workarounds) is not a workable solution. And because the
+timer can jump both forward and backward, no pair of reads can
+distinguish a good value from a bad one. The only way to guarantee a
+good value from consecutive reads would be to read _three_ times, and
+take the middle value only if the three values are 1) each unique and
+2) increasing. This takes at minimum 3 counter cycles (125 ns), or more
+if an anomaly is detected.
+
+However, since there is a distinct pattern to the bad values, we can
+optimize the common case (1022/1024 of the time) to a single read by
+simply ignoring values that match the error pattern. This still takes no
+more than 3 cycles in the worst case, and requires much less code. As an
+additional safety check, we still limit the loop iteration to the number
+of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods.
+
+For the TVAL registers, the simple solution is to not use them. Instead,
+read or write the CVAL and calculate the TVAL value in software.
+
+Although the manufacturer is aware of at least part of the erratum[4],
+there is no official name for it. For now, use the kernel-internal name
+"UNKNOWN1".
+
+[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
+[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
+[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
+[4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272
+
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Tested-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ Documentation/arm64/silicon-errata.txt |  2 +
+ drivers/clocksource/Kconfig            | 10 +++++
+ drivers/clocksource/arm_arch_timer.c   | 55 ++++++++++++++++++++++++++
+ 3 files changed, 67 insertions(+)
+
+diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
+index 8f9577621144..4a269732d2a0 100644
+--- a/Documentation/arm64/silicon-errata.txt
++++ b/Documentation/arm64/silicon-errata.txt
+@@ -44,6 +44,8 @@ stable kernels.
+ 
+ | Implementor    | Component       | Erratum ID      | Kconfig                     |
+ +----------------+-----------------+-----------------+-----------------------------+
++| Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |
++|                |                 |                 |                             |
+ | ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |
+ | ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |
+ | ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069        |
+diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
+index 55c77e44bb2d..d20ff4da07c3 100644
+--- a/drivers/clocksource/Kconfig
++++ b/drivers/clocksource/Kconfig
+@@ -364,6 +364,16 @@ config ARM64_ERRATUM_858921
+ 	  The workaround will be dynamically enabled when an affected
+ 	  core is detected.
+ 
++config SUN50I_ERRATUM_UNKNOWN1
++	bool "Workaround for Allwinner A64 erratum UNKNOWN1"
++	default y
++	depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
++	select ARM_ARCH_TIMER_OOL_WORKAROUND
++	help
++	  This option enables a workaround for instability in the timer on
++	  the Allwinner A64 SoC. The workaround will only be active if the
++	  allwinner,erratum-unknown1 property is found in the timer node.
++
+ config ARM_GLOBAL_TIMER
+ 	bool "Support for the ARM global timer" if COMPILE_TEST
+ 	select TIMER_OF if OF
+diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
+index 9a7d4dc00b6e..a8b20b65bd4b 100644
+--- a/drivers/clocksource/arm_arch_timer.c
++++ b/drivers/clocksource/arm_arch_timer.c
+@@ -326,6 +326,48 @@ static u64 notrace arm64_1188873_read_cntvct_el0(void)
+ }
+ #endif
+ 
++#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
++/*
++ * The low bits of the counter registers are indeterminate while bit 10 or
++ * greater is rolling over. Since the counter value can jump both backward
++ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
++ * with all ones or all zeros in the low bits. Bound the loop by the maximum
++ * number of CPU cycles in 3 consecutive 24 MHz counter periods.
++ */
++#define __sun50i_a64_read_reg(reg) ({					\
++	u64 _val;							\
++	int _retries = 150;						\
++									\
++	do {								\
++		_val = read_sysreg(reg);				\
++		_retries--;						\
++	} while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries);	\
++									\
++	WARN_ON_ONCE(!_retries);					\
++	_val;								\
++})
++
++static u64 notrace sun50i_a64_read_cntpct_el0(void)
++{
++	return __sun50i_a64_read_reg(cntpct_el0);
++}
++
++static u64 notrace sun50i_a64_read_cntvct_el0(void)
++{
++	return __sun50i_a64_read_reg(cntvct_el0);
++}
++
++static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
++{
++	return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
++}
++
++static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
++{
++	return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
++}
++#endif
++
+ #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+ DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
+ EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
+@@ -423,6 +465,19 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
+ 		.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,
+ 	},
+ #endif
++#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
++	{
++		.match_type = ate_match_dt,
++		.id = "allwinner,erratum-unknown1",
++		.desc = "Allwinner erratum UNKNOWN1",
++		.read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
++		.read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
++		.read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
++		.read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
++		.set_next_event_phys = erratum_set_next_event_tval_phys,
++		.set_next_event_virt = erratum_set_next_event_tval_virt,
++	},
++#endif
+ };
+ 
+ typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
+
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+ Sat, 12 Jan 2019 21:17:22 -0500 (EST)
+From: Samuel Holland <samuel@sholland.org>
+To: Catalin Marinas <catalin.marinas@arm.com>,
+ Will Deacon <will.deacon@arm.com>,
+ Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
+ Rob Herring <robh+dt@kernel.org>, Mark Rutland <Mark.Rutland@arm.com>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
+Subject: [PATCH v3 2/2] arm64: dts: allwinner: a64: Enable A64 timer
+ workaround
+Date: Sat, 12 Jan 2019 20:17:19 -0600
+Message-Id: <20190113021719.46457-3-samuel@sholland.org>
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+
+As instability in the architectural timer has been observed on multiple
+devices using this SoC, inluding the Pine64 and the Orange Pi Win,
+enable the workaround in the SoC's device tree.
+
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index f3a66f888205..13eac92a8c55 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -175,6 +175,7 @@
+ 
+ 	timer {
+ 		compatible = "arm,armv8-timer";
++		allwinner,erratum-unknown1;
+ 		interrupts = <GIC_PPI 13
+ 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ 			     <GIC_PPI 14
diff --git a/arm64-arch_timer-Workaround-for-Allwinner-A64-timer-instability.patch b/arm64-arch_timer-Workaround-for-Allwinner-A64-timer-instability.patch
deleted file mode 100644
index 74c7eb981..000000000
--- a/arm64-arch_timer-Workaround-for-Allwinner-A64-timer-instability.patch
+++ /dev/null
@@ -1,184 +0,0 @@
-From patchwork Fri May 11 02:27:50 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 8bit
-Subject: [1/2] arm64: arch_timer: Workaround for Allwinner A64 timer
- instability
-From: Samuel Holland <samuel@sholland.org>
-X-Patchwork-Id: 10392891
-Message-Id: <20180511022751.9096-2-samuel@sholland.org>
-To: Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>, 
- Catalin Marinas <catalin.marinas@arm.com>,
- Will Deacon <will.deacon@arm.com>,
- Daniel Lezcano <daniel.lezcano@linaro.org>,
- Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
-Cc: linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org, Samuel Holland <samuel@sholland.org>
-Date: Thu, 10 May 2018 21:27:50 -0500
-
-The Allwinner A64 SoC is known [1] to have an unstable architectural
-timer, which manifests itself most obviously in the time jumping forward
-a multiple of 95 years [2][3]. This coincides with 2^56 cycles at a
-timer frequency of 24 MHz, implying that the time went slightly backward
-(and this was interpreted by the kernel as it jumping forward and
-wrapping around past the epoch).
-
-Further investigation revealed instability in the low bits of CNTVCT at
-the point a high bit rolls over. This leads to power-of-two cycle
-forward and backward jumps. (Testing shows that forward jumps are about
-twice as likely as backward jumps.)
-
-Without trapping reads to CNTVCT, a userspace program is able to read it
-in a loop faster than it changes. A test program running on all 4 CPU
-cores that reported jumps larger than 100 ms was run for 13.6 hours and
-reported the following:
-
- Count | Event
--------+---------------------------
-  9940 | jumped backward      699ms
-   268 | jumped backward     1398ms
-     1 | jumped backward     2097ms
- 16020 | jumped forward       175ms
-  6443 | jumped forward       699ms
-  2976 | jumped forward      1398ms
-     9 | jumped forward    356516ms
-     9 | jumped forward    357215ms
-     4 | jumped forward    714430ms
-     1 | jumped forward   3578440ms
-
-This works out to a jump larger than 100 ms about every 5.5 seconds on
-each CPU core.
-
-The largest jump (almost an hour!) was the following sequence of reads:
-      0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000
-
-Note that the middle bits don't necessarily all read as all zeroes or
-all ones during the anomalous behavior; however the low 11 bits checked
-by the function in this patch have never been observed with any other
-value.
-
-Also note that smaller jumps are much more common, with the smallest
-backward jumps of 2048 cycles observed over 400 times per second on each
-core. (Of course, this is partially due to lower bits rolling over more
-frequently.) Any one of these could have caused the 95 year time skip.
-
-Similar anomalies were observed while reading CNTPCT (after patching the
-kernel to allow reads from userspace). However, the jumps are much less
-frequent, and only small jumps were observed. The same program as before
-(except now reading CNTPCT) observed after 72 hours:
-
- Count | Event
--------+---------------------------
-    17 | jumped backward      699ms
-    52 | jumped forward       175ms
-  2831 | jumped forward       699ms
-     5 | jumped forward      1398ms
-Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
-Tested-by: Andre Przywara <andre.przywara@arm.com>
-
-========================================================================
-
-Because the CPU can read the CNTPCT/CNTVCT registers faster than they
-change, performing two reads of the register and comparing the high bits
-(like other workarounds) is not a workable solution. And because the
-timer can jump both forward and backward, no pair of reads can
-distinguish a good value from a bad one. The only way to guarantee a
-good value from consecutive reads would be to read _three_ times, and
-take the middle value iff the three values are 1) individually unique
-and 2) increasing. This takes at minimum 3 cycles (125 ns), or more if
-an anomaly is detected.
-
-However, since there is a distinct pattern to the bad values, we can
-optimize the common case (2046/2048 of the time) to a single read by
-simply ignoring values that match the pattern. This still takes no more
-than 3 cycles in the worst case, and requires much less code.
-
-[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
-[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
-[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/clocksource/Kconfig          | 11 ++++++++++
- drivers/clocksource/arm_arch_timer.c | 39 ++++++++++++++++++++++++++++++++++++
- 2 files changed, 50 insertions(+)
-
-diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
-index 8e8a09755d10..7a5d434dd30b 100644
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -364,6 +364,17 @@ config ARM64_ERRATUM_858921
- 	  The workaround will be dynamically enabled when an affected
- 	  core is detected.
- 
-+config SUN50I_A64_UNSTABLE_TIMER
-+	bool "Workaround for Allwinner A64 timer instability"
-+	default y
-+	depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
-+	select ARM_ARCH_TIMER_OOL_WORKAROUND
-+	help
-+	  This option enables a workaround for instability in the timer on
-+	  the Allwinner A64 SoC. The workaround will only be active if the
-+	  allwinner,sun50i-a64-unstable-timer property is found in the
-+	  timer node.
-+
- config ARM_GLOBAL_TIMER
- 	bool "Support for the ARM global timer" if COMPILE_TEST
- 	select TIMER_OF if OF
-diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
-index 57cb2f00fc07..66ce13578c52 100644
---- a/drivers/clocksource/arm_arch_timer.c
-+++ b/drivers/clocksource/arm_arch_timer.c
-@@ -319,6 +319,36 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
- }
- #endif
- 
-+#ifdef CONFIG_SUN50I_A64_UNSTABLE_TIMER
-+/*
-+ * The low bits of each register can transiently read as all ones or all zeroes
-+ * when bit 11 or greater rolls over. Since the value can jump both backward
-+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), it is simplest to just
-+ * ignore register values with all ones or zeros in the low bits.
-+ */
-+static u64 notrace sun50i_a64_read_cntpct_el0(void)
-+{
-+	u64 val;
-+
-+	do {
-+		val = read_sysreg(cntpct_el0);
-+	} while (((val + 1) & GENMASK(10, 0)) <= 1);
-+
-+	return val;
-+}
-+
-+static u64 notrace sun50i_a64_read_cntvct_el0(void)
-+{
-+	u64 val;
-+
-+	do {
-+		val = read_sysreg(cntvct_el0);
-+	} while (((val + 1) & GENMASK(10, 0)) <= 1);
-+
-+	return val;
-+}
-+#endif
-+
- #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
- DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
- EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
-@@ -408,6 +438,15 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
- 		.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,
- 	},
- #endif
-+#ifdef CONFIG_SUN50I_A64_UNSTABLE_TIMER
-+	{
-+		.match_type = ate_match_dt,
-+		.id = "allwinner,sun50i-a64-unstable-timer",
-+		.desc = "Allwinner A64 timer instability",
-+		.read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
-+		.read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
-+	},
-+#endif
- };
- 
- typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
diff --git a/arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch b/arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch
deleted file mode 100644
index 56f9f159e..000000000
--- a/arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From patchwork Fri May 11 02:27:51 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [2/2] arm64: dts: allwinner: a64: Enable A64 timer workaround
-From: Samuel Holland <samuel@sholland.org>
-X-Patchwork-Id: 10392889
-Message-Id: <20180511022751.9096-3-samuel@sholland.org>
-To: Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>, 
- Catalin Marinas <catalin.marinas@arm.com>,
- Will Deacon <will.deacon@arm.com>,
- Daniel Lezcano <daniel.lezcano@linaro.org>,
- Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
-Cc: linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org, Samuel Holland <samuel@sholland.org>
-Date: Thu, 10 May 2018 21:27:51 -0500
-
-As instability in the architectural timer has been observed on multiple
-devices using this SoC, inluding the Pine64 and the Orange Pi Win,
-enable the workaround in the SoC's device tree.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-index 1b2ef28c42bd..5202b76e9684 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -152,6 +152,7 @@
- 
- 	timer {
- 		compatible = "arm,armv8-timer";
-+		allwinner,sun50i-a64-unstable-timer;
- 		interrupts = <GIC_PPI 13
- 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- 			     <GIC_PPI 14
diff --git a/bcm283x-Add-missing-GPIO-line-names.patch b/bcm283x-Add-missing-GPIO-line-names.patch
deleted file mode 100644
index e27082ad2..000000000
--- a/bcm283x-Add-missing-GPIO-line-names.patch
+++ /dev/null
@@ -1,255 +0,0 @@
-From 99909530ec9b6e9b1b3b756a05a83fa1c7d6d4bc Mon Sep 17 00:00:00 2001
-From: Stefan Wahren <stefan.wahren@i2se.com>
-Date: Tue, 1 Jan 2019 18:29:08 +0100
-Subject: [PATCH] ARM: dts: bcm283x: Add missing GPIO line names
-
-The GPIO sysfs is deprecated and disabled in the defconfig files.
-So in order to motivate the usage of the new GPIO character device API
-add the missing GPIO line names for Raspberry Pi 2 and 3.
-
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
----
- arch/arm/boot/dts/bcm2836-rpi-2-b.dts      | 66 ++++++++++++++++++++
- arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 70 ++++++++++++++++++++++
- arch/arm/boot/dts/bcm2837-rpi-3-b.dts      | 70 ++++++++++++++++++++++
- 3 files changed, 206 insertions(+)
-
-diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
-index 871fc4a558cf..7b4e651bafdd 100644
---- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
-+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
-@@ -28,6 +28,72 @@
- };
- 
- &gpio {
-+	/*
-+	 * Taken from rpi_SCH_2b_1p2_reduced.pdf and
-+	 * the official GPU firmware DT blob.
-+	 *
-+	 * Legend:
-+	 * "NC" = not connected (no rail from the SoC)
-+	 * "FOO" = GPIO line named "FOO" on the schematic
-+	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
-+	 */
-+	gpio-line-names = "ID_SDA",
-+			  "ID_SCL",
-+			  "SDA1",
-+			  "SCL1",
-+			  "GPIO_GCLK",
-+			  "GPIO5",
-+			  "GPIO6",
-+			  "SPI_CE1_N",
-+			  "SPI_CE0_N",
-+			  "SPI_MISO",
-+			  "SPI_MOSI",
-+			  "SPI_SCLK",
-+			  "GPIO12",
-+			  "GPIO13",
-+			  /* Serial port */
-+			  "TXD0",
-+			  "RXD0",
-+			  "GPIO16",
-+			  "GPIO17",
-+			  "GPIO18",
-+			  "GPIO19",
-+			  "GPIO20",
-+			  "GPIO21",
-+			  "GPIO22",
-+			  "GPIO23",
-+			  "GPIO24",
-+			  "GPIO25",
-+			  "GPIO26",
-+			  "GPIO27",
-+			  "SDA0",
-+			  "SCL0",
-+			  "", /* GPIO30 */
-+			  "LAN_RUN",
-+			  "CAM_GPIO1",
-+			  "", /* GPIO33 */
-+			  "", /* GPIO34 */
-+			  "PWR_LOW_N",
-+			  "", /* GPIO36 */
-+			  "", /* GPIO37 */
-+			  "USB_LIMIT",
-+			  "", /* GPIO39 */
-+			  "PWM0_OUT",
-+			  "CAM_GPIO0",
-+			  "SMPS_SCL",
-+			  "SMPS_SDA",
-+			  "ETHCLK",
-+			  "PWM1_OUT",
-+			  "HDMI_HPD_N",
-+			  "STATUS_LED",
-+			  /* Used by SD Card */
-+			  "SD_CLK_R",
-+			  "SD_CMD_R",
-+			  "SD_DATA0_R",
-+			  "SD_DATA1_R",
-+			  "SD_DATA2_R",
-+			  "SD_DATA3_R";
-+
- 	pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
- 
- 	/* I2S interface */
-diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
-index 94886fcaf0b9..9358f8481f36 100644
---- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
-+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
-@@ -52,6 +52,76 @@
- 	};
- };
- 
-+&gpio {
-+	/*
-+	 * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and
-+	 * the official GPU firmware DT blob.
-+	 *
-+	 * Legend:
-+	 * "NC" = not connected (no rail from the SoC)
-+	 * "FOO" = GPIO line named "FOO" on the schematic
-+	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
-+	 */
-+	gpio-line-names = "ID_SDA",
-+			  "ID_SCL",
-+			  "SDA1",
-+			  "SCL1",
-+			  "GPIO_GCLK",
-+			  "GPIO5",
-+			  "GPIO6",
-+			  "SPI_CE1_N",
-+			  "SPI_CE0_N",
-+			  "SPI_MISO",
-+			  "SPI_MOSI",
-+			  "SPI_SCLK",
-+			  "GPIO12",
-+			  "GPIO13",
-+			  /* Serial port */
-+			  "TXD1",
-+			  "RXD1",
-+			  "GPIO16",
-+			  "GPIO17",
-+			  "GPIO18",
-+			  "GPIO19",
-+			  "GPIO20",
-+			  "GPIO21",
-+			  "GPIO22",
-+			  "GPIO23",
-+			  "GPIO24",
-+			  "GPIO25",
-+			  "GPIO26",
-+			  "GPIO27",
-+			  "HDMI_HPD_N",
-+			  "STATUS_LED_G",
-+			  /* Used by BT module */
-+			  "CTS0",
-+			  "RTS0",
-+			  "TXD0",
-+			  "RXD0",
-+			  /* Used by Wifi */
-+			  "SD1_CLK",
-+			  "SD1_CMD",
-+			  "SD1_DATA0",
-+			  "SD1_DATA1",
-+			  "SD1_DATA2",
-+			  "SD1_DATA3",
-+			  "PWM0_OUT",
-+			  "PWM1_OUT",
-+			  "ETHCLK",
-+			  "WIFI_CLK",
-+			  "SDA0",
-+			  "SCL0",
-+			  "SMPS_SCL",
-+			  "SMPS_SDA",
-+			  /* Used by SD Card */
-+			  "SD_CLK_R",
-+			  "SD_CMD_R",
-+			  "SD_DATA0_R",
-+			  "SD_DATA1_R",
-+			  "SD_DATA2_R",
-+			  "SD_DATA3_R";
-+};
-+
- &hdmi {
- 	hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
- };
-diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
-index 31b1c03e0ff7..ce71f578c51a 100644
---- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
-+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
-@@ -47,6 +47,76 @@
- 	};
- };
- 
-+&gpio {
-+	/*
-+	 * Taken from rpi_SCH_3b_1p2_reduced.pdf and
-+	 * the official GPU firmware DT blob.
-+	 *
-+	 * Legend:
-+	 * "NC" = not connected (no rail from the SoC)
-+	 * "FOO" = GPIO line named "FOO" on the schematic
-+	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
-+	 */
-+	gpio-line-names = "ID_SDA",
-+			  "ID_SCL",
-+			  "SDA1",
-+			  "SCL1",
-+			  "GPIO_GCLK",
-+			  "GPIO5",
-+			  "GPIO6",
-+			  "SPI_CE1_N",
-+			  "SPI_CE0_N",
-+			  "SPI_MISO",
-+			  "SPI_MOSI",
-+			  "SPI_SCLK",
-+			  "GPIO12",
-+			  "GPIO13",
-+			  /* Serial port */
-+			  "TXD1",
-+			  "RXD1",
-+			  "GPIO16",
-+			  "GPIO17",
-+			  "GPIO18",
-+			  "GPIO19",
-+			  "GPIO20",
-+			  "GPIO21",
-+			  "GPIO22",
-+			  "GPIO23",
-+			  "GPIO24",
-+			  "GPIO25",
-+			  "GPIO26",
-+			  "GPIO27",
-+			  "", /* GPIO 28 */
-+			  "LAN_RUN_BOOT",
-+			  /* Used by BT module */
-+			  "CTS0",
-+			  "RTS0",
-+			  "TXD0",
-+			  "RXD0",
-+			  /* Used by Wifi */
-+			  "SD1_CLK",
-+			  "SD1_CMD",
-+			  "SD1_DATA0",
-+			  "SD1_DATA1",
-+			  "SD1_DATA2",
-+			  "SD1_DATA3",
-+			  "PWM0_OUT",
-+			  "PWM1_OUT",
-+			  "ETHCLK",
-+			  "WIFI_CLK",
-+			  "SDA0",
-+			  "SCL0",
-+			  "SMPS_SCL",
-+			  "SMPS_SDA",
-+			  /* Used by SD Card */
-+			  "SD_CLK_R",
-+			  "SD_CMD_R",
-+			  "SD_DATA0_R",
-+			  "SD_DATA1_R",
-+			  "SD_DATA2_R",
-+			  "SD_DATA3_R";
-+};
-+
- &pwm {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
diff --git a/configs/fedora/generic/arm/aarch64/CONFIG_SUN50I_ERRATUM_UNKNOWN1 b/configs/fedora/generic/arm/aarch64/CONFIG_SUN50I_ERRATUM_UNKNOWN1
new file mode 100644
index 000000000..24a355b35
--- /dev/null
+++ b/configs/fedora/generic/arm/aarch64/CONFIG_SUN50I_ERRATUM_UNKNOWN1
@@ -0,0 +1 @@
+CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
diff --git a/kernel-aarch64-debug.config b/kernel-aarch64-debug.config
index f23e1467b..ded0235e0 100644
--- a/kernel-aarch64-debug.config
+++ b/kernel-aarch64-debug.config
@@ -6034,6 +6034,7 @@ CONFIG_ST_UVIS25_SPI=m
 CONFIG_SUN50I_A64_CCU=y
 CONFIG_SUN50I_A64_UNSTABLE_TIMER=y
 CONFIG_SUN50I_DE2_BUS=y
+CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
 CONFIG_SUN50I_H6_CCU=y
 CONFIG_SUN50I_H6_R_CCU=y
 # CONFIG_SUN8I_A83T_CCU is not set
diff --git a/kernel-aarch64.config b/kernel-aarch64.config
index a87813526..3b5a17509 100644
--- a/kernel-aarch64.config
+++ b/kernel-aarch64.config
@@ -6011,6 +6011,7 @@ CONFIG_ST_UVIS25_SPI=m
 CONFIG_SUN50I_A64_CCU=y
 CONFIG_SUN50I_A64_UNSTABLE_TIMER=y
 CONFIG_SUN50I_DE2_BUS=y
+CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
 CONFIG_SUN50I_H6_CCU=y
 CONFIG_SUN50I_H6_R_CCU=y
 # CONFIG_SUN8I_A83T_CCU is not set
diff --git a/kernel.spec b/kernel.spec
index 579b27f0f..86c5453ab 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -580,14 +580,14 @@ Patch330: bcm2837-dts-add-Raspberry-Pi-3-A.patch
 # https://patchwork.kernel.org/patch/10741809/
 Patch331: bcm2835-mmc-sdhci-iproc-handle-mmc_of_parse-errors-during-probe.patch
 
-Patch332: bcm283x-Add-missing-GPIO-line-names.patch
+# https://www.spinics.net/lists/arm-kernel/msg699583.html
+Patch332: ARM-dts-bcm283x-Several-DTS-improvements.patch
 
 Patch339: bcm2835-cpufreq-add-CPU-frequency-control-driver.patch
 
 # Fix for AllWinner A64 Timer Errata, still not final
-# https://patchwork.kernel.org/patch/10392891/
-Patch350: arm64-arch_timer-Workaround-for-Allwinner-A64-timer-instability.patch
-Patch351: arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch
+# https://www.spinics.net/lists/arm-kernel/msg699622.html
+Patch350: Allwinner-A64-timer-workaround.patch
 
 # 400 - IBM (ppc/s390x) patches
 
@@ -1876,6 +1876,10 @@ fi
 #
 #
 %changelog
+* Sun Jan 13 2019 Peter Robinson <pbrobinson@fedoraproject.org>
+- Raspberry Pi updates
+- Update AllWinner A64 timer errata workaround
+
 * Fri Jan 11 2019 Laura Abbott <labbott@redhat.com> - 5.0.0-0.rc1.git4.1
 - Linux v5.0-rc1-43-g1bdbe2274920