diff options
| author | Peter Robinson <pbrobinson@gmail.com> | 2020-02-27 22:42:09 +0000 |
|---|---|---|
| committer | Peter Robinson <pbrobinson@gmail.com> | 2020-02-27 22:53:02 +0000 |
| commit | 126f6d685331599ac205a1127a675c1b660e6259 (patch) | |
| tree | 3f867879ff29e410913b4761e753a45cf107bc06 | |
| parent | 70c4f19642f3a196b01f22c9cc8e0629df609727 (diff) | |
| download | kernel-126f6d685331599ac205a1127a675c1b660e6259.tar.gz kernel-126f6d685331599ac205a1127a675c1b660e6259.tar.xz kernel-126f6d685331599ac205a1127a675c1b660e6259.zip | |
Some fixes for Tegra devices
| -rw-r--r-- | ARM64-Tegra-fixes.patch | 477 | ||||
| -rw-r--r-- | backlight-lp855x-Ensure-regulators-are-disabled-on-probe-failure.patch | 186 | ||||
| -rw-r--r-- | kernel.spec | 8 | ||||
| -rw-r--r-- | regulator-pwm-Don-t-warn-on-probe-deferral.patch | 99 |
4 files changed, 769 insertions, 1 deletions
diff --git a/ARM64-Tegra-fixes.patch b/ARM64-Tegra-fixes.patch new file mode 100644 index 000000000..6ddfc2322 --- /dev/null +++ b/ARM64-Tegra-fixes.patch @@ -0,0 +1,477 @@ +From patchwork Mon Feb 24 14:34:33 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Jon Hunter <jonathanh@nvidia.com> +X-Patchwork-Id: 1243145 +Return-Path: <linux-tegra-owner@vger.kernel.org> +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=none (no SPF record) + smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; + helo=vger.kernel.org; + envelope-from=linux-tegra-owner@vger.kernel.org; + receiver=<UNKNOWN>) +Authentication-Results: ozlabs.org; + dmarc=pass (p=none dis=none) header.from=nvidia.com +Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; + unprotected) header.d=nvidia.com header.i=@nvidia.com + header.a=rsa-sha256 header.s=n1 header.b=duOxTEf6; + dkim-atps=neutral +Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) + by ozlabs.org (Postfix) with ESMTP id 48R4Mz3K4gz9sRR + for <incoming@patchwork.ozlabs.org>; + Tue, 25 Feb 2020 01:34:55 +1100 (AEDT) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1727815AbgBXOew (ORCPT <rfc822;incoming@patchwork.ozlabs.org>); + Mon, 24 Feb 2020 09:34:52 -0500 +Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:6094 "EHLO + hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1727498AbgBXOew (ORCPT + <rfc822;linux-tegra@vger.kernel.org>); + Mon, 24 Feb 2020 09:34:52 -0500 +Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by + hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) + id <B5e53debf0001>; Mon, 24 Feb 2020 06:33:35 -0800 +Received: from hqmail.nvidia.com ([172.20.161.6]) + by hqpgpgate101.nvidia.com (PGP Universal service); + Mon, 24 Feb 2020 06:34:51 -0800 +X-PGP-Universal: processed; + by hqpgpgate101.nvidia.com on Mon, 24 Feb 2020 06:34:51 -0800 +Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com + (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; + Mon, 24 Feb 2020 14:34:50 +0000 +Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com + (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via + Frontend Transport; Mon, 24 Feb 2020 14:34:50 +0000 +Received: from thunderball.nvidia.com (Not Verified[10.21.140.91]) by + rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) + id <B5e53df090001>; Mon, 24 Feb 2020 06:34:50 -0800 +From: Jon Hunter <jonathanh@nvidia.com> +To: Thierry Reding <thierry.reding@gmail.com> +CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, + Jon Hunter <jonathanh@nvidia.com>, <stable@vger.kernel.org> +Subject: [PATCH 1/4] ARM64: Tegra: Enable I2C controller for EEPROM +Date: Mon, 24 Feb 2020 14:34:33 +0000 +Message-ID: <20200224143436.5438-1-jonathanh@nvidia.com> +X-Mailer: git-send-email 2.17.1 +X-NVConfidentiality: public +MIME-Version: 1.0 +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; + t=1582554815; bh=SKhUz0YkoB6pD4YoE/4KFxZbYw2qmSp519cZdmcBM3o=; + h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: + X-NVConfidentiality:MIME-Version:Content-Type; + b=duOxTEf6wTpBnmdA4GzgtJ0CYXr5t34ZZNN48pc9hExmRqaCcppGHAY2wcXqnjNmL + YwvDy0gfFikGS9gPJKICW2X6f4iOcgfnVhYOWdgnzSFD1bhtOoN+bEcXPC+LRDY89m + uAwuuKQR4MMohz9C8MW8xyatlc13ZEU0jeW1+S3PYfX2GhwRUooeFCGnmLUso5s2DZ + 65p26CoCGdQNBARsw2TNevBzLshNSXvHBdlFiKSs4S0hB7yJJrCwZx2JsjOm+aRtb3 + dgVHvAZAd8GLLKC8NvPCAhbIRhDt0vkyWmqHnB5suduti7g4QA1Eb8HLAXB5ptvzeK + jor+qP+NC8CVQ== +Sender: linux-tegra-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-tegra.vger.kernel.org> +X-Mailing-List: linux-tegra@vger.kernel.org + +Commit a5b6b67364cb ("arm64: tegra: Add ID EEPROM for Jetson TX1 +module") populated the EEPROM on the Jetson TX1 module, but did not +enable the corresponding I2C controller. Enable the I2C controller so +that this EEPROM can be accessed. + +Fixes: a5b6b67364cb ("arm64: tegra: Add ID EEPROM for Jetson TX1 module") + +Cc: <stable@vger.kernel.org> +Signed-off-by: Jon Hunter <jonathanh@nvidia.com> +--- + arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +index cb58f79deb48..95b1a6e76e6e 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi ++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +@@ -265,6 +265,8 @@ + }; + + i2c@7000c500 { ++ status = "okay"; ++ + /* module ID EEPROM */ + eeprom@50 { + compatible = "atmel,24c02"; + +From patchwork Mon Feb 24 14:34:34 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Jon Hunter <jonathanh@nvidia.com> +X-Patchwork-Id: 1243146 +Return-Path: <linux-tegra-owner@vger.kernel.org> +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=none (no SPF record) + smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; + helo=vger.kernel.org; + envelope-from=linux-tegra-owner@vger.kernel.org; + receiver=<UNKNOWN>) +Authentication-Results: ozlabs.org; + dmarc=pass (p=none dis=none) header.from=nvidia.com +Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; + unprotected) header.d=nvidia.com header.i=@nvidia.com + header.a=rsa-sha256 header.s=n1 header.b=YrupJt5o; + dkim-atps=neutral +Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) + by ozlabs.org (Postfix) with ESMTP id 48R4N1059Pz9sRR + for <incoming@patchwork.ozlabs.org>; + Tue, 25 Feb 2020 01:34:57 +1100 (AEDT) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1727498AbgBXOe4 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>); + Mon, 24 Feb 2020 09:34:56 -0500 +Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:8365 "EHLO + hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1727803AbgBXOe4 (ORCPT + <rfc822;linux-tegra@vger.kernel.org>); + Mon, 24 Feb 2020 09:34:56 -0500 +Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by + hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) + id <B5e53deec0000>; Mon, 24 Feb 2020 06:34:20 -0800 +Received: from hqmail.nvidia.com ([172.20.161.6]) + by hqpgpgate101.nvidia.com (PGP Universal service); + Mon, 24 Feb 2020 06:34:55 -0800 +X-PGP-Universal: processed; + by hqpgpgate101.nvidia.com on Mon, 24 Feb 2020 06:34:55 -0800 +Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com + (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; + Mon, 24 Feb 2020 14:34:55 +0000 +Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com + (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via + Frontend Transport; Mon, 24 Feb 2020 14:34:55 +0000 +Received: from thunderball.nvidia.com (Not Verified[10.21.140.91]) by + rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) + id <B5e53df0d0000>; Mon, 24 Feb 2020 06:34:54 -0800 +From: Jon Hunter <jonathanh@nvidia.com> +To: Thierry Reding <thierry.reding@gmail.com> +CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, + Jon Hunter <jonathanh@nvidia.com> +Subject: [PATCH 2/4] ARM64: tegra: Add EEPROM supplies +Date: Mon, 24 Feb 2020 14:34:34 +0000 +Message-ID: <20200224143436.5438-2-jonathanh@nvidia.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20200224143436.5438-1-jonathanh@nvidia.com> +References: <20200224143436.5438-1-jonathanh@nvidia.com> +X-NVConfidentiality: public +MIME-Version: 1.0 +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; + t=1582554860; bh=XQRed+hM+dOmUn7lEyFBRTITiHe/kmVf6bYnTKyb4yU=; + h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: + In-Reply-To:References:X-NVConfidentiality:MIME-Version: + Content-Type; + b=YrupJt5osNrArZbD3/6N+E76P788S2kgwb7HnwldZ99/x70lrAIXTKHOx35uqz7o0 + bsYj1jAiz+BrmkHt678TBaesev2pBBcp8G+zkGDX+M6MWEvTixhn0bBERoHpnmuhQl + 1fWBcDKGg9r4KT46RFxrjCcRek8FB1gb1nM00FneNHFyguKuZEzRuMvoPfZEPr0Pm3 + HaB3AybSYgm2KABS5aZo/a2/9sIP0Bx2St673Bx+9vz89pPr8lWjHZO9QjIUdJn2Qw + 5rEeeEdOKkbx0RMyKaPAPIdhmrnVzrcyrnZYmf0KnxXJCWitqt2cyAu6uDjPI8kiL+ + JhWqRAza5osKg== +Sender: linux-tegra-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-tegra.vger.kernel.org> +X-Mailing-List: linux-tegra@vger.kernel.org + +The following warning is observed on Jetson TX1, Jetson Nano and Jetson +TX2 platforms because the supply regulators are not specified for the +EEPROMs. + + WARNING KERN at24 0-0050: 0-0050 supply vcc not found, using dummy regulator + WARNING KERN at24 0-0057: 0-0057 supply vcc not found, using dummy regulator + +For both of these platforms the EEPROM is powered by the main 1.8V +supply rail and so populate the supply for these devices to fix these +warnings. + +Signed-off-by: Jon Hunter <jonathanh@nvidia.com> +--- + arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 1 + + arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 1 + + arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 1 + + arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 1 + + arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 ++ + 5 files changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +index d7628f5afb85..961b1be0c56b 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts ++++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +@@ -226,6 +226,7 @@ + compatible = "atmel,24c02"; + reg = <0x57>; + ++ vcc-supply = <&vdd_1v8>; + address-bits = <8>; + page-size = <8>; + size = <256>; +diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +index 947744d0f04c..da96de04d003 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi ++++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +@@ -171,6 +171,7 @@ + compatible = "atmel,24c02"; + reg = <0x50>; + ++ vcc-supply = <&vdd_1v8>; + address-bits = <8>; + page-size = <8>; + size = <256>; +diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +index 95b1a6e76e6e..f87d2437d11c 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi ++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +@@ -272,6 +272,7 @@ + compatible = "atmel,24c02"; + reg = <0x50>; + ++ vcc-supply = <&vdd_1v8>; + address-bits = <8>; + page-size = <8>; + size = <256>; +diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +index a3cafe39ba4c..c70a610f8e3a 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts ++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +@@ -85,6 +85,7 @@ + compatible = "atmel,24c02"; + reg = <0x57>; + ++ vcc-supply = <&vdd_1v8>; + address-bits = <8>; + page-size = <8>; + size = <256>; +diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +index 848afd855da6..21ed1756b889 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts ++++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +@@ -114,6 +114,7 @@ + compatible = "atmel,24c02"; + reg = <0x50>; + ++ vcc-supply = <&vdd_1v8>; + address-bits = <8>; + page-size = <8>; + size = <256>; +@@ -124,6 +125,7 @@ + compatible = "atmel,24c02"; + reg = <0x57>; + ++ vcc-supply = <&vdd_1v8>; + address-bits = <8>; + page-size = <8>; + size = <256>; + +From patchwork Mon Feb 24 14:34:35 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Jon Hunter <jonathanh@nvidia.com> +X-Patchwork-Id: 1243147 +Return-Path: <linux-tegra-owner@vger.kernel.org> +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; 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a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; + t=1582554864; bh=lUBb2WrI059cKuJQ/lQ6zAeA/dUVGu1GIMzWYnFLzuA=; + h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: + In-Reply-To:References:X-NVConfidentiality:MIME-Version: + Content-Type; + b=cDDn02CYOMd1x5bK/t7LoZ9fYn59xu8HcaGTMnsTAUfJYYkF5vUqcWjve/5PtksEv + +bYF/ELx+KLrbyXQ4LtKHW1V8F2iDHhNR1Rrs+/MUuPuxuOXwTsaYJgLd2A/FWO54O + men6fW7E5dJS7lmfJ050sgzZs+TABrFO/dyzOfrekczCVpqlnJEsPvdpFlBbzg125A + ZW3sMSe1pW+54pvkCWL7YF/RFnb9zefc0feJmu0Ky+kMH2QOFPSvufzsFBxOr1bUaJ + wqzLNTYwY6tWNy7axusq4KLKuCViERaAqSs/UlzzsrOQHJeecBOlH2GkFi8z7JASz2 + ucv0C5PUNzlTg== +Sender: linux-tegra-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-tegra.vger.kernel.org> +X-Mailing-List: linux-tegra@vger.kernel.org + +The following warning is observed on the Jetson TX2 platform ... + + WARNING KERN tegra-sor 15540000.sor: 15540000.sor supply \ + vdd-hdmi-dp-pll not found, using dummy regulator + +The problem is caused because the regulator for the SOR device is +missing the '-supply' suffix in Device-Tree. Therefore, add the +'-supply' suffix to fix this warning. + +Fixes: 3fdfaf8718fa arm64: tegra: Enable DP support on Jetson TX2 + +Cc: <stable@vger.kernel.org> +Signed-off-by: Jon Hunter <jonathanh@nvidia.com> +--- + arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +index 961b1be0c56b..1af7f9ffb7b6 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts ++++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +@@ -278,7 +278,7 @@ + status = "okay"; + + avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; +- vdd-hdmi-dp-pll = <&vdd_1v8_ap>; ++ vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; + + nvidia,dpaux = <&dpaux>; + }; + +From patchwork Mon Feb 24 14:34:36 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Jon Hunter <jonathanh@nvidia.com> +X-Patchwork-Id: 1243148 +Return-Path: <linux-tegra-owner@vger.kernel.org> +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; 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a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; + t=1582554826; bh=8MBs7jrK7WrFNE7o6bG0zu41Sicfxu97bK94j6RYNJs=; + h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: + In-Reply-To:References:X-NVConfidentiality:MIME-Version: + Content-Type; + b=K9z8jYfdaYDh/XGz5S/vyzBWYN4ZPYT6jkue5E5YiUVIyQgLCoZqfSIh3h9luB+/C + DhYTYMkUQRLasUE0VX9dr4Bn0Hxeaw8DjYS7BUq4LqfNwWjsCSsNEhk26FGBEUvhRH + i2nMUMk5Ivw78ouR6qNZhI6freANsproJ+yQkA0cC9WXj5mQw4xcKRmL48dccxrX47 + aQi0BDk3SCzZBAa+4G3yynAGiRNiFuLVWkg/vFMcq1JDp6a2mVs/CS3Qj0/heE9gPn + Qr2Wy0Oa6tg3jhxR9hk7qyy5FlkfDAtJOlUt6sPloPS4bhqqDJtbnXZL7lzHDP+sw+ + RZcjavnvJtCIQ== +Sender: linux-tegra-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-tegra.vger.kernel.org> +X-Mailing-List: linux-tegra@vger.kernel.org + +The following warning is observed on Jetson TX1 platform because the +supply regulator is not specified for the backlight. + + WARNING KERN lp855x 0-002c: 0-002c supply power not found, using dummy regulator + +The backlight supply is provided by the 3.3V SYS rail and so add this +as the supply for the backlight. + +Signed-off-by: Jon Hunter <jonathanh@nvidia.com> +--- + arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +index c70a610f8e3a..ea0e1efa6973 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts ++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +@@ -56,6 +56,7 @@ + backlight: backlight@2c { + compatible = "ti,lp8557"; + reg = <0x2c>; ++ power-supply = <&vdd_3v3_sys>; + + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0xff>; diff --git a/backlight-lp855x-Ensure-regulators-are-disabled-on-probe-failure.patch b/backlight-lp855x-Ensure-regulators-are-disabled-on-probe-failure.patch new file mode 100644 index 000000000..08c519629 --- /dev/null +++ b/backlight-lp855x-Ensure-regulators-are-disabled-on-probe-failure.patch @@ -0,0 +1,186 @@ +From patchwork Mon Feb 24 14:07:48 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Jon Hunter <jonathanh@nvidia.com> +X-Patchwork-Id: 1243112 +Return-Path: <linux-tegra-owner@vger.kernel.org> +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=none (no SPF record) + smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; + helo=vger.kernel.org; + envelope-from=linux-tegra-owner@vger.kernel.org; + receiver=<UNKNOWN>) +Authentication-Results: ozlabs.org; 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Mon, 24 Feb 2020 06:07:00 -0800 +Received: from hqmail.nvidia.com ([172.20.161.6]) + by hqpgpgate101.nvidia.com (PGP Universal service); + Mon, 24 Feb 2020 06:08:16 -0800 +X-PGP-Universal: processed; + by hqpgpgate101.nvidia.com on Mon, 24 Feb 2020 06:08:16 -0800 +Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com + (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; + Mon, 24 Feb 2020 14:08:16 +0000 +Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com + (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via + Frontend Transport; Mon, 24 Feb 2020 14:08:15 +0000 +Received: from thunderball.nvidia.com (Not Verified[10.21.140.91]) by + rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) + id <B5e53d8cd0006>; Mon, 24 Feb 2020 06:08:15 -0800 +From: Jon Hunter <jonathanh@nvidia.com> +To: Milo Kim <milo.kim@ti.com>, Lee Jones <lee.jones@linaro.org>, + Daniel Thompson <daniel.thompson@linaro.org>, + Jingoo Han <jingoohan1@gmail.com> +CC: <dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>, + <linux-tegra@vger.kernel.org>, Jon Hunter <jonathanh@nvidia.com> +Subject: [PATCH] backlight: lp855x: Ensure regulators are disabled on probe + failure +Date: Mon, 24 Feb 2020 14:07:48 +0000 +Message-ID: <20200224140748.2182-1-jonathanh@nvidia.com> +X-Mailer: git-send-email 2.17.1 +X-NVConfidentiality: public +MIME-Version: 1.0 +DKIM-Signature: v=1; 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+ if (ret < 0) { + dev_err(lp->dev, "failed to enable vddio: %d\n", ret); +- return ret; ++ goto disable_supply; + } + + /* +@@ -471,24 +471,34 @@ static int lp855x_probe(struct i2c_client *cl, const struct i2c_device_id *id) + ret = lp855x_configure(lp); + if (ret) { + dev_err(lp->dev, "device config err: %d", ret); +- return ret; ++ goto disable_vddio; + } + + ret = lp855x_backlight_register(lp); + if (ret) { + dev_err(lp->dev, + "failed to register backlight. err: %d\n", ret); +- return ret; ++ goto disable_vddio; + } + + ret = sysfs_create_group(&lp->dev->kobj, &lp855x_attr_group); + if (ret) { + dev_err(lp->dev, "failed to register sysfs. err: %d\n", ret); +- return ret; ++ goto disable_vddio; + } + + backlight_update_status(lp->bl); ++ + return 0; ++ ++disable_vddio: ++ if (lp->enable) ++ regulator_disable(lp->enable); ++disable_supply: ++ if (lp->supply) ++ regulator_disable(lp->supply); ++ ++ return ret; + } + + static int lp855x_remove(struct i2c_client *cl) +@@ -497,6 +507,8 @@ static int lp855x_remove(struct i2c_client *cl) + + lp->bl->props.brightness = 0; + backlight_update_status(lp->bl); ++ if (lp->enable) ++ regulator_disable(lp->enable); + if (lp->supply) + regulator_disable(lp->supply); + sysfs_remove_group(&lp->dev->kobj, &lp855x_attr_group); diff --git a/kernel.spec b/kernel.spec index 25c18a929..6b237b0c3 100644 --- a/kernel.spec +++ b/kernel.spec @@ -832,11 +832,16 @@ Patch313: ARM-dts-bcm283x-Add-missing-properties-to-the-PWR-LED.patch Patch314: ARM-dts-bcm2711-Add-pcie0-alias.patch # Tegra bits -Patch320: arm64-tegra-jetson-tx1-fixes.patch +# https://www.spinics.net/lists/linux-tegra/msg48152.html +Patch320: ARM64-Tegra-fixes.patch # http://patchwork.ozlabs.org/patch/1230891/ Patch321: arm64-serial-8250_tegra-Create-Tegra-specific-8250-driver.patch # https://lkml.org/lkml/2020/2/14/401 Patch323: arm64-tegra-fix-pcie.patch +# http://patchwork.ozlabs.org/patch/1243162/ +Patch324: regulator-pwm-Don-t-warn-on-probe-deferral.patch +# http://patchwork.ozlabs.org/patch/1243112/ +Patch325: backlight-lp855x-Ensure-regulators-are-disabled-on-probe-failure.patch # Coral Patch330: arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch @@ -2965,6 +2970,7 @@ fi %changelog * Thu Feb 27 2020 Peter Robinson <pbrobinson@fedoraproject.org> - Fixes and enhancements to some AllWinner Pine64 devices +- Some fixes for Tegra devices * Thu Feb 27 2020 Jeremy Cline <jcline@redhat.com> - 5.6.0-0.rc3.git2.1 - Linux v5.6-rc3-71-gbfdc6d91a25f diff --git a/regulator-pwm-Don-t-warn-on-probe-deferral.patch b/regulator-pwm-Don-t-warn-on-probe-deferral.patch new file mode 100644 index 000000000..a662dd1fb --- /dev/null +++ b/regulator-pwm-Don-t-warn-on-probe-deferral.patch @@ -0,0 +1,99 @@ +From patchwork Mon Feb 24 14:40:48 2020 +Content-Type: text/plain; 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Mon, 24 Feb 2020 14:40:52 +0000 +Received: from thunderball.nvidia.com (Not Verified[10.21.140.91]) by + rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) + id <B5e53e0720007>; Mon, 24 Feb 2020 06:40:51 -0800 +From: Jon Hunter <jonathanh@nvidia.com> +To: Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>, + Thierry Reding <thierry.reding@gmail.com> +CC: <linux-kernel@vger.kernel.org>, <linux-pwm@vger.kernel.org>, + <linux-tegra@vger.kernel.org>, Jon Hunter <jonathanh@nvidia.com> +Subject: [PATCH] regulator: pwm: Don't warn on probe deferral +Date: Mon, 24 Feb 2020 14:40:48 +0000 +Message-ID: <20200224144048.6587-1-jonathanh@nvidia.com> +X-Mailer: git-send-email 2.17.1 +X-NVConfidentiality: public +MIME-Version: 1.0 +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; + t=1582555239; bh=xX7Mgn1VlNejVzsSKFLhZRbMP4+2YtN6WM4DdeoOEHs=; + h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: + X-NVConfidentiality:MIME-Version:Content-Type; + b=GMucuiiqAspPQsWQ1ebM1v5mPEShSHma2lu4iNERqE/uilIy4CUp4eHq6df8Lcsvu + 11bCdd116mWyRJ5/F69vtHcgJHTbeaaRcf+A1/A3DLTuc6Z/PRb5jcySSX/aRCaPfA + +au3XaR3dyBeV+xizDks3Ibot8dmHuQWswqibwwVp5Qanoow2Dj75j/Q++AU7PwM6A + ChvWMkFCBBz6FO8SGi5jCQrCgLTrHtX90cRQZsaaQFrbBYLhLrAsdFkFM2mVLd+xqz + rc7bwTn707Mpf71vRGfmJgoiBm/Pm1qLnRoyLBakyb0xfmEJkCP99y3nO62z9DIpDm + DdSZ9ONzuo7vA== +Sender: linux-tegra-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-tegra.vger.kernel.org> +X-Mailing-List: linux-tegra@vger.kernel.org + +Deferred probe is an expected return value for devm_pwm_get(). Given +that the driver deals with it properly, there's no need to output a +warning that may potentially confuse users. + +Signed-off-by: Jon Hunter <jonathanh@nvidia.com> +Reviewed-by: Thierry Reding <treding@nvidia.com> +--- + drivers/regulator/pwm-regulator.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/regulator/pwm-regulator.c b/drivers/regulator/pwm-regulator.c +index e74e11101fc1..fb25777a7d47 100644 +--- a/drivers/regulator/pwm-regulator.c ++++ b/drivers/regulator/pwm-regulator.c +@@ -354,7 +354,8 @@ static int pwm_regulator_probe(struct platform_device *pdev) + drvdata->pwm = devm_pwm_get(&pdev->dev, NULL); + if (IS_ERR(drvdata->pwm)) { + ret = PTR_ERR(drvdata->pwm); +- dev_err(&pdev->dev, "Failed to get PWM: %d\n", ret); ++ if (ret != -EPROBE_DEFER) ++ dev_err(&pdev->dev, "Failed to get PWM: %d\n", ret); + return ret; + } + |