diff options
| author | Justin M. Forbes <jforbes@fedoraproject.org> | 2017-09-11 13:05:08 -0500 |
|---|---|---|
| committer | Justin M. Forbes <jforbes@fedoraproject.org> | 2017-09-11 13:05:08 -0500 |
| commit | 21e4b83380d4419b3d5c2ce01553807b3dcd2321 (patch) | |
| tree | 29f9e57f7f72e3d8f4a074d75bbd0c4b7f3820a9 | |
| parent | 3a0a8f607a330dd51e5ac6e6ba1ac2264cb15602 (diff) | |
| download | kernel-21e4b83380d4419b3d5c2ce01553807b3dcd2321.tar.gz kernel-21e4b83380d4419b3d5c2ce01553807b3dcd2321.tar.xz kernel-21e4b83380d4419b3d5c2ce01553807b3dcd2321.zip | |
Linux v4.13-11197-gf007cad159e9
44 files changed, 138 insertions, 3142 deletions
diff --git a/0001-power-supply-max17042_battery-Add-support-for-ACPI-e.patch b/0001-power-supply-max17042_battery-Add-support-for-ACPI-e.patch deleted file mode 100644 index 858cd5a34..000000000 --- a/0001-power-supply-max17042_battery-Add-support-for-ACPI-e.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 075bb90dbb4d894938c5859e3850987238db9cd8 Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Fri, 11 Aug 2017 22:30:55 +0200 -Subject: [PATCH 1/2] power: supply: max17042_battery: Add support for ACPI - enumeration - -Some x86 devices enumerate a max17047 fuel-gauge through a MAX17047 -ACPI firmware-node, add support for this. - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - drivers/power/supply/max17042_battery.c | 22 +++++++++++++++++++++- - 1 file changed, 21 insertions(+), 1 deletion(-) - -diff --git a/drivers/power/supply/max17042_battery.c b/drivers/power/supply/max17042_battery.c -index aecaaa2b0586..b2ddb7eb69c6 100644 ---- a/drivers/power/supply/max17042_battery.c -+++ b/drivers/power/supply/max17042_battery.c -@@ -22,6 +22,7 @@ - * This driver is based on max17040_battery.c - */ - -+#include <linux/acpi.h> - #include <linux/init.h> - #include <linux/module.h> - #include <linux/slab.h> -@@ -982,6 +983,8 @@ static int max17042_probe(struct i2c_client *client, - struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); - const struct power_supply_desc *max17042_desc = &max17042_psy_desc; - struct power_supply_config psy_cfg = {}; -+ const struct acpi_device_id *acpi_id; -+ struct device *dev = &client->dev; - struct max17042_chip *chip; - int ret; - int i; -@@ -995,7 +998,15 @@ static int max17042_probe(struct i2c_client *client, - return -ENOMEM; - - chip->client = client; -- chip->chip_type = id->driver_data; -+ if (id) { -+ chip->chip_type = id->driver_data; -+ } else { -+ acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev); -+ if (!acpi_id) -+ return -ENODEV; -+ -+ chip->chip_type = acpi_id->driver_data; -+ } - chip->regmap = devm_regmap_init_i2c(client, &max17042_regmap_config); - if (IS_ERR(chip->regmap)) { - dev_err(&client->dev, "Failed to initialize regmap\n"); -@@ -1104,6 +1115,14 @@ static int max17042_resume(struct device *dev) - static SIMPLE_DEV_PM_OPS(max17042_pm_ops, max17042_suspend, - max17042_resume); - -+#ifdef CONFIG_ACPI -+static const struct acpi_device_id max17042_acpi_match[] = { -+ { "MAX17047", MAXIM_DEVICE_TYPE_MAX17047 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(acpi, max17042_acpi_match); -+#endif -+ - #ifdef CONFIG_OF - static const struct of_device_id max17042_dt_match[] = { - { .compatible = "maxim,max17042" }, -@@ -1125,6 +1144,7 @@ MODULE_DEVICE_TABLE(i2c, max17042_id); - static struct i2c_driver max17042_i2c_driver = { - .driver = { - .name = "max17042", -+ .acpi_match_table = ACPI_PTR(max17042_acpi_match), - .of_match_table = of_match_ptr(max17042_dt_match), - .pm = &max17042_pm_ops, - }, --- -2.13.4 - diff --git a/0002-power-supply-max17042_battery-Fix-ACPI-interrupt-iss.patch b/0002-power-supply-max17042_battery-Fix-ACPI-interrupt-iss.patch deleted file mode 100644 index 6daecaf4d..000000000 --- a/0002-power-supply-max17042_battery-Fix-ACPI-interrupt-iss.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 27b9d46d25c873b351757c44ce523bf0ede1d08e Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Mon, 14 Aug 2017 11:02:59 +0200 -Subject: [PATCH 2/2] power: supply: max17042_battery: Fix ACPI interrupt - issues - -On some x86/ACPI boards the DSDT defines an ACPI event handler for -the max17047 IRQ, this causes several problems: - -1) We need to share the IRQ to avoid an error getting it - -2) Even of we are willing to share, we may fail to share because some - DSDTs claim it exclusivly - -3) If we are unable to share the IRQ, or the IRQ is only listed as an - ACPI event source and not in the max1704 firmware node, then the - charge threshold IRQ (which is used to give an IRQ every 1 percent - charge change) becomes a problem, the ACPI event handler will not - update this to the next 1 percent threshold, so the IRQ keeps firing - and we get an IRQ storm pegging 1 CPU core. - - This happens despite the max17042 driver not setting the charge - threshold because Windows uses it and leaves it set on reboot. - - So if we are unable to get the IRQ we need to reprogram the - charge threshold to its disabled setting. - -This commit fixes al of the above, while at it it also makes the error -msg when being unable to get the IRQ consistent with other messages. - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - drivers/power/supply/max17042_battery.c | 20 +++++++++++++++----- - 1 file changed, 15 insertions(+), 5 deletions(-) - -diff --git a/drivers/power/supply/max17042_battery.c b/drivers/power/supply/max17042_battery.c -index b2ddb7eb69c6..18a44e4ed6ff 100644 ---- a/drivers/power/supply/max17042_battery.c -+++ b/drivers/power/supply/max17042_battery.c -@@ -1050,11 +1050,18 @@ static int max17042_probe(struct i2c_client *client, - } - - if (client->irq) { -+ unsigned int flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT; -+ -+ /* -+ * On ACPI systems the IRQ may be handled by ACPI-event code, -+ * so we need to share (if the ACPI code is willing to share). -+ */ -+ if (acpi_id) -+ flags |= IRQF_SHARED | IRQF_PROBE_SHARED; -+ - ret = devm_request_threaded_irq(&client->dev, client->irq, - NULL, -- max17042_thread_handler, -- IRQF_TRIGGER_FALLING | -- IRQF_ONESHOT, -+ max17042_thread_handler, flags, - chip->battery->desc->name, - chip); - if (!ret) { -@@ -1064,10 +1071,13 @@ static int max17042_probe(struct i2c_client *client, - max17042_set_soc_threshold(chip, 1); - } else { - client->irq = 0; -- dev_err(&client->dev, "%s(): cannot get IRQ\n", -- __func__); -+ if (ret != -EBUSY) -+ dev_err(&client->dev, "Failed to get IRQ\n"); - } - } -+ /* Not able to update the charge threshold when exceeded? -> disable */ -+ if (!client->irq) -+ regmap_write(chip->regmap, MAX17042_SALRT_Th, 0xff00); - - regmap_read(chip->regmap, MAX17042_STATUS, &val); - if (val & STATUS_POR_BIT) { --- -2.13.4 - diff --git a/0015-i2c-cht-wc-Add-Intel-Cherry-Trail-Whiskey-Cove-SMBUS.patch b/0015-i2c-cht-wc-Add-Intel-Cherry-Trail-Whiskey-Cove-SMBUS.patch deleted file mode 100644 index 5d7497ce1..000000000 --- a/0015-i2c-cht-wc-Add-Intel-Cherry-Trail-Whiskey-Cove-SMBUS.patch +++ /dev/null @@ -1,410 +0,0 @@ -From bd0d7169342e47919f68e75d659968f02b62f84b Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Fri, 3 Mar 2017 23:48:50 +0100 -Subject: [PATCH 15/16] i2c-cht-wc: Add Intel Cherry Trail Whiskey Cove SMBUS - controller driver - -The Intel Cherry Trail Whiskey Cove PMIC does not contain a builtin -battery charger, instead boards with this PMIC use an external TI -bq24292i charger IC, which is connected to a SMBUS controller built into -the PMIC. - -This commit adds an i2c-bus driver for the PMIC's builtin SMBUS -controller. The probe function for this i2c-bus will also register an -i2c-client for the TI bq24292i charger after the i2c-bus has been -registered. - -Note that several device-properties are set on the client-device to -tell the bq24190 power-supply driver to integrate the Whiskey Cove PMIC -and e.g. use the PMIC's BC1.2 detection (through extcon) to determine -the maximum input current. - -Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- -Changes in v2: --Various style (mostly captialization and variable name) fixes --Use device-properties instead of platform_data for the i2c_board_info ---- - drivers/i2c/busses/Kconfig | 8 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-cht-wc.c | 336 ++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 345 insertions(+) - create mode 100644 drivers/i2c/busses/i2c-cht-wc.c - -diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 144cbadc7c72..18c96178b177 100644 ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -187,6 +187,14 @@ config I2C_PIIX4 - This driver can also be built as a module. If so, the module - will be called i2c-piix4. - -+config I2C_CHT_WC -+ tristate "Intel Cherry Trail Whiskey Cove PMIC smbus controller" -+ depends on INTEL_SOC_PMIC_CHTWC -+ help -+ If you say yes to this option, support will be included for the -+ SMBus controller found in the Intel Cherry Trail Whiskey Cove PMIC -+ found on some Intel Cherry Trail systems. -+ - config I2C_NFORCE2 - tristate "Nvidia nForce2, nForce3 and nForce4" - depends on PCI -diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile -index 30b60855fbcd..f6443fa44f61 100644 ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -12,6 +12,7 @@ obj-$(CONFIG_I2C_ALI15X3) += i2c-ali15x3.o - obj-$(CONFIG_I2C_AMD756) += i2c-amd756.o - obj-$(CONFIG_I2C_AMD756_S4882) += i2c-amd756-s4882.o - obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o -+obj-$(CONFIG_I2C_CHT_WC) += i2c-cht-wc.o - obj-$(CONFIG_I2C_I801) += i2c-i801.o - obj-$(CONFIG_I2C_ISCH) += i2c-isch.o - obj-$(CONFIG_I2C_ISMT) += i2c-ismt.o -diff --git a/drivers/i2c/busses/i2c-cht-wc.c b/drivers/i2c/busses/i2c-cht-wc.c -new file mode 100644 -index 000000000000..ccf0785bcb75 ---- /dev/null -+++ b/drivers/i2c/busses/i2c-cht-wc.c -@@ -0,0 +1,336 @@ -+/* -+ * Intel CHT Whiskey Cove PMIC I2C Master driver -+ * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com> -+ * -+ * Based on various non upstream patches to support the CHT Whiskey Cove PMIC: -+ * Copyright (C) 2011 - 2014 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License version -+ * 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include <linux/completion.h> -+#include <linux/delay.h> -+#include <linux/i2c.h> -+#include <linux/interrupt.h> -+#include <linux/irq.h> -+#include <linux/irqdomain.h> -+#include <linux/mfd/intel_soc_pmic.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+#include <linux/slab.h> -+ -+#define CHT_WC_I2C_CTRL 0x5e24 -+#define CHT_WC_I2C_CTRL_WR BIT(0) -+#define CHT_WC_I2C_CTRL_RD BIT(1) -+#define CHT_WC_I2C_CLIENT_ADDR 0x5e25 -+#define CHT_WC_I2C_REG_OFFSET 0x5e26 -+#define CHT_WC_I2C_WRDATA 0x5e27 -+#define CHT_WC_I2C_RDDATA 0x5e28 -+ -+#define CHT_WC_EXTCHGRIRQ 0x6e0a -+#define CHT_WC_EXTCHGRIRQ_CLIENT_IRQ BIT(0) -+#define CHT_WC_EXTCHGRIRQ_WRITE_IRQ BIT(1) -+#define CHT_WC_EXTCHGRIRQ_READ_IRQ BIT(2) -+#define CHT_WC_EXTCHGRIRQ_NACK_IRQ BIT(3) -+#define CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK ((u8)GENMASK(3, 1)) -+#define CHT_WC_EXTCHGRIRQ_MSK 0x6e17 -+ -+struct cht_wc_i2c_adap { -+ struct i2c_adapter adapter; -+ wait_queue_head_t wait; -+ struct irq_chip irqchip; -+ struct mutex irqchip_lock; -+ struct regmap *regmap; -+ struct irq_domain *irq_domain; -+ struct i2c_client *client; -+ int client_irq; -+ u8 irq_mask; -+ u8 old_irq_mask; -+ bool nack; -+ bool done; -+}; -+ -+static irqreturn_t cht_wc_i2c_adap_thread_handler(int id, void *data) -+{ -+ struct cht_wc_i2c_adap *adap = data; -+ int ret, reg; -+ -+ /* Read IRQs */ -+ ret = regmap_read(adap->regmap, CHT_WC_EXTCHGRIRQ, ®); -+ if (ret) { -+ dev_err(&adap->adapter.dev, "Error reading extchgrirq reg\n"); -+ return IRQ_NONE; -+ } -+ -+ reg &= ~adap->irq_mask; -+ -+ /* -+ * Immediately ack IRQs, so that if new IRQs arrives while we're -+ * handling the previous ones our irq will re-trigger when we're done. -+ */ -+ ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, reg); -+ if (ret) -+ dev_err(&adap->adapter.dev, "Error writing extchgrirq reg\n"); -+ -+ /* -+ * Do NOT use handle_nested_irq here, the client irq handler will -+ * likely want to do i2c transfers and the i2c controller uses this -+ * interrupt handler as well, so running the client irq handler from -+ * this thread will cause things to lock up. -+ */ -+ if (reg & CHT_WC_EXTCHGRIRQ_CLIENT_IRQ) { -+ /* -+ * generic_handle_irq expects local IRQs to be disabled -+ * as normally it is called from interrupt context. -+ */ -+ local_irq_disable(); -+ generic_handle_irq(adap->client_irq); -+ local_irq_enable(); -+ } -+ -+ if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) { -+ adap->nack = !!(reg & CHT_WC_EXTCHGRIRQ_NACK_IRQ); -+ adap->done = true; -+ wake_up(&adap->wait); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static u32 cht_wc_i2c_adap_master_func(struct i2c_adapter *adap) -+{ -+ /* This i2c adapter only supports SMBUS byte transfers */ -+ return I2C_FUNC_SMBUS_BYTE_DATA; -+} -+ -+static int cht_wc_i2c_adap_smbus_xfer(struct i2c_adapter *_adap, u16 addr, -+ unsigned short flags, char read_write, -+ u8 command, int size, -+ union i2c_smbus_data *data) -+{ -+ struct cht_wc_i2c_adap *adap = i2c_get_adapdata(_adap); -+ int ret, reg; -+ -+ adap->nack = false; -+ adap->done = false; -+ -+ ret = regmap_write(adap->regmap, CHT_WC_I2C_CLIENT_ADDR, addr); -+ if (ret) -+ return ret; -+ -+ if (read_write == I2C_SMBUS_WRITE) { -+ ret = regmap_write(adap->regmap, CHT_WC_I2C_WRDATA, data->byte); -+ if (ret) -+ return ret; -+ } -+ -+ ret = regmap_write(adap->regmap, CHT_WC_I2C_REG_OFFSET, command); -+ if (ret) -+ return ret; -+ -+ ret = regmap_write(adap->regmap, CHT_WC_I2C_CTRL, -+ (read_write == I2C_SMBUS_WRITE) ? -+ CHT_WC_I2C_CTRL_WR : CHT_WC_I2C_CTRL_RD); -+ if (ret) -+ return ret; -+ -+ /* 3 second timeout, during cable plug the PMIC responds quite slow */ -+ ret = wait_event_timeout(adap->wait, adap->done, 3 * HZ); -+ if (ret == 0) -+ return -ETIMEDOUT; -+ if (adap->nack) -+ return -EIO; -+ -+ if (read_write == I2C_SMBUS_READ) { -+ ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, ®); -+ if (ret) -+ return ret; -+ -+ data->byte = reg; -+ } -+ -+ return 0; -+} -+ -+static const struct i2c_algorithm cht_wc_i2c_adap_algo = { -+ .functionality = cht_wc_i2c_adap_master_func, -+ .smbus_xfer = cht_wc_i2c_adap_smbus_xfer, -+}; -+ -+/**** irqchip for the client connected to the extchgr i2c adapter ****/ -+static void cht_wc_i2c_irq_lock(struct irq_data *data) -+{ -+ struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); -+ -+ mutex_lock(&adap->irqchip_lock); -+} -+ -+static void cht_wc_i2c_irq_sync_unlock(struct irq_data *data) -+{ -+ struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); -+ int ret; -+ -+ if (adap->irq_mask != adap->old_irq_mask) { -+ ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, -+ adap->irq_mask); -+ if (ret == 0) -+ adap->old_irq_mask = adap->irq_mask; -+ else -+ dev_err(&adap->adapter.dev, "Error writing EXTCHGRIRQ_MSK\n"); -+ } -+ -+ mutex_unlock(&adap->irqchip_lock); -+} -+ -+static void cht_wc_i2c_irq_enable(struct irq_data *data) -+{ -+ struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); -+ -+ adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; -+} -+ -+static void cht_wc_i2c_irq_disable(struct irq_data *data) -+{ -+ struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); -+ -+ adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; -+} -+ -+static const struct irq_chip cht_wc_i2c_irq_chip = { -+ .irq_bus_lock = cht_wc_i2c_irq_lock, -+ .irq_bus_sync_unlock = cht_wc_i2c_irq_sync_unlock, -+ .irq_disable = cht_wc_i2c_irq_disable, -+ .irq_enable = cht_wc_i2c_irq_enable, -+ .name = "cht_wc_ext_chrg_irq_chip", -+}; -+ -+static const struct property_entry bq24190_props[] = { -+ PROPERTY_ENTRY_STRING("extcon-name", "cht_wcove_pwrsrc"), -+ PROPERTY_ENTRY_BOOL("omit-battery-class"), -+ PROPERTY_ENTRY_BOOL("disable-reset"), -+ { } -+}; -+ -+static int cht_wc_i2c_adap_i2c_probe(struct platform_device *pdev) -+{ -+ struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent); -+ struct cht_wc_i2c_adap *adap; -+ struct i2c_board_info board_info = { -+ .type = "bq24190", -+ .addr = 0x6b, -+ .properties = bq24190_props, -+ }; -+ int ret, irq; -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ dev_err(&pdev->dev, "Error missing irq resource\n"); -+ return -EINVAL; -+ } -+ -+ adap = devm_kzalloc(&pdev->dev, sizeof(*adap), GFP_KERNEL); -+ if (!adap) -+ return -ENOMEM; -+ -+ init_waitqueue_head(&adap->wait); -+ mutex_init(&adap->irqchip_lock); -+ adap->irqchip = cht_wc_i2c_irq_chip; -+ adap->regmap = pmic->regmap; -+ adap->adapter.owner = THIS_MODULE; -+ adap->adapter.class = I2C_CLASS_HWMON; -+ adap->adapter.algo = &cht_wc_i2c_adap_algo; -+ strlcpy(adap->adapter.name, "PMIC I2C Adapter", -+ sizeof(adap->adapter.name)); -+ adap->adapter.dev.parent = &pdev->dev; -+ -+ /* Clear and activate i2c-adapter interrupts, disable client IRQ */ -+ adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK; -+ ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask); -+ if (ret) -+ return ret; -+ -+ ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask); -+ if (ret) -+ return ret; -+ -+ /* Alloc and register client IRQ */ -+ adap->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 1, -+ &irq_domain_simple_ops, NULL); -+ if (!adap->irq_domain) -+ return -ENOMEM; -+ -+ adap->client_irq = irq_create_mapping(adap->irq_domain, 0); -+ if (!adap->client_irq) { -+ ret = -ENOMEM; -+ goto remove_irq_domain; -+ } -+ -+ irq_set_chip_data(adap->client_irq, adap); -+ irq_set_chip_and_handler(adap->client_irq, &adap->irqchip, -+ handle_simple_irq); -+ -+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, -+ cht_wc_i2c_adap_thread_handler, -+ IRQF_ONESHOT, "PMIC I2C Adapter", adap); -+ if (ret) -+ goto remove_irq_domain; -+ -+ i2c_set_adapdata(&adap->adapter, adap); -+ ret = i2c_add_adapter(&adap->adapter); -+ if (ret) -+ goto remove_irq_domain; -+ -+ board_info.irq = adap->client_irq; -+ adap->client = i2c_new_device(&adap->adapter, &board_info); -+ if (!adap->client) { -+ ret = -ENOMEM; -+ goto del_adapter; -+ } -+ -+ platform_set_drvdata(pdev, adap); -+ return 0; -+ -+del_adapter: -+ i2c_del_adapter(&adap->adapter); -+remove_irq_domain: -+ irq_domain_remove(adap->irq_domain); -+ return ret; -+} -+ -+static int cht_wc_i2c_adap_i2c_remove(struct platform_device *pdev) -+{ -+ struct cht_wc_i2c_adap *adap = platform_get_drvdata(pdev); -+ -+ i2c_unregister_device(adap->client); -+ i2c_del_adapter(&adap->adapter); -+ irq_domain_remove(adap->irq_domain); -+ -+ return 0; -+} -+ -+static struct platform_device_id cht_wc_i2c_adap_id_table[] = { -+ { .name = "cht_wcove_ext_chgr" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(platform, cht_wc_i2c_adap_id_table); -+ -+struct platform_driver cht_wc_i2c_adap_driver = { -+ .probe = cht_wc_i2c_adap_i2c_probe, -+ .remove = cht_wc_i2c_adap_i2c_remove, -+ .driver = { -+ .name = "cht_wcove_ext_chgr", -+ }, -+ .id_table = cht_wc_i2c_adap_id_table, -+}; -+module_platform_driver(cht_wc_i2c_adap_driver); -+ -+MODULE_DESCRIPTION("Intel CHT Whiskey Cove PMIC I2C Master driver"); -+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); -+MODULE_LICENSE("GPL"); --- -2.13.0 - diff --git a/allwinner-net-emac.patch b/allwinner-net-emac.patch index f5d680bde..346c50809 100644 --- a/allwinner-net-emac.patch +++ b/allwinner-net-emac.patch @@ -332,314 +332,6 @@ index 11240a8313c2..d38282b9e5d4 100644 -- 2.13.5 -From 4aba5ca95496899165ee7ceef5d9c60a6e7b15dd Mon Sep 17 00:00:00 2001 -From: Peter Robinson <pbrobinson@gmail.com> -Date: Mon, 4 Sep 2017 13:04:47 +0100 -Subject: [PATCH 3/4] Revert "arm64: dts: allwinner: Revert EMAC changes" - -This reverts commit 87e1f5e8bb4bd584de0a8f3b1e42196dca221d02. ---- - .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++++++++++++++++ - .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 +++++++++++++++ - arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +++++++++++++++++ - .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++++++++++++++++ - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 ++++++++++++++++++++ - .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++ - .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++ - .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +++++++++++++++++ - 8 files changed, 135 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts -index 6872135d7f84..ba2fde2909f9 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts -@@ -51,6 +51,7 @@ - compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - }; -@@ -67,6 +68,14 @@ - }; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ status = "okay"; -+}; -+ - &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; -@@ -77,6 +86,13 @@ - bias-pull-up; - }; - -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts -index f82ccf332c0f..24f1aac366d6 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts -@@ -48,3 +48,18 @@ - - /* TODO: Camera, touchscreen, etc. */ - }; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ status = "okay"; -+}; -+ -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -index 7c533b6d4ba9..827168bc22ed 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -@@ -51,6 +51,7 @@ - compatible = "pine64,pine64", "allwinner,sun50i-a64"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; -@@ -78,6 +79,15 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rmii_pins>; -+ phy-mode = "rmii"; -+ phy-handle = <&ext_rmii_phy1>; -+ status = "okay"; -+ -+}; -+ - &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; -@@ -88,6 +98,13 @@ - bias-pull-up; - }; - -+&mdio { -+ ext_rmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -index d891a1a27f6c..216e3a5dafae 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -@@ -53,6 +53,7 @@ - "allwinner,sun50i-a64"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -76,6 +77,21 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ status = "okay"; -+}; -+ -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index 68aadc9b96dc..bd0f33b77f57 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -449,6 +449,26 @@ - #size-cells = <0>; - }; - -+ emac: ethernet@1c30000 { -+ compatible = "allwinner,sun50i-a64-emac"; -+ syscon = <&syscon>; -+ reg = <0x01c30000 0x10000>; -+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq"; -+ resets = <&ccu RST_BUS_EMAC>; -+ reset-names = "stmmaceth"; -+ clocks = <&ccu CLK_BUS_EMAC>; -+ clock-names = "stmmaceth"; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mdio: mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts -index 1c2387bd5df6..968908761194 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts -@@ -50,6 +50,7 @@ - compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -108,6 +109,22 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&mdio { -+ ext_rgmii_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -index 4f77c8470f6c..a8296feee884 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -@@ -59,6 +59,7 @@ - }; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -136,12 +137,28 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ - &ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; - }; - -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts -index 6be06873e5af..d906b302cbcd 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts -@@ -54,6 +54,7 @@ - compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -143,12 +144,28 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ - &ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; - }; - -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; --- -2.13.5 - From 11190f020b948ccdf15061b6df8cc2836a2afcb1 Mon Sep 17 00:00:00 2001 From: Peter Robinson <pbrobinson@gmail.com> Date: Mon, 4 Sep 2017 13:04:55 +0100 diff --git a/arm-tegra-fix-gpu-iommu.patch b/arm-tegra-fix-gpu-iommu.patch deleted file mode 100644 index c775c88b4..000000000 --- a/arm-tegra-fix-gpu-iommu.patch +++ /dev/null @@ -1,39 +0,0 @@ -From patchwork Sun Jul 9 16:36:14 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: ARM: tegra: Register host1x node with iommu binding on tegra124 -From: Paul Kocialkowski <contact@paulk.fr> -X-Patchwork-Id: 9831825 -Message-Id: <20170709163614.6746-1-contact@paulk.fr> -To: linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, - linux-kernel@vger.kernel.org -Cc: Thierry Reding <thierry.reding@gmail.com>, - Stephen Warren <swarren@wwwdotorg.org>, - Mikko Perttunen <mperttunen@nvidia.com>, - Paul Kocialkowski <contact@paulk.fr>, - Jonathan Hunter <jonathanh@nvidia.com> -Date: Sun, 9 Jul 2017 19:36:14 +0300 - -This registers the host1x node with the SMMU (as HC swgroup) to allow -the host1x code to attach to it. It avoid failing the probe sequence, -which resulted in the tegra drm driver not probing and thus nothing -being displayed on-screen. - -Signed-off-by: Paul Kocialkowski <contact@paulk.fr> ---- - arch/arm/boot/dts/tegra124.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi -index 187a36c6d0fc..b3b89befffeb 100644 ---- a/arch/arm/boot/dts/tegra124.dtsi -+++ b/arch/arm/boot/dts/tegra124.dtsi -@@ -85,6 +85,7 @@ - clocks = <&tegra_car TEGRA124_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; -+ iommus = <&mc TEGRA_SWGROUP_HC>; - - #address-cells = <2>; - #size-cells = <2>; diff --git a/baseconfig/CONFIG_BATTERY_MAX1721X b/baseconfig/CONFIG_BATTERY_MAX1721X new file mode 100644 index 000000000..0f2a78a9b --- /dev/null +++ b/baseconfig/CONFIG_BATTERY_MAX1721X @@ -0,0 +1 @@ +CONFIG_BATTERY_MAX1721X=m diff --git a/baseconfig/CONFIG_QCOM_GLINK_SSR b/baseconfig/CONFIG_QCOM_GLINK_SSR new file mode 100644 index 000000000..1c67b32f7 --- /dev/null +++ b/baseconfig/CONFIG_QCOM_GLINK_SSR @@ -0,0 +1 @@ +# CONFIG_QCOM_GLINK_SSR is not set diff --git a/baseconfig/CONFIG_RESET_HSDK_V1 b/baseconfig/CONFIG_RESET_HSDK_V1 new file mode 100644 index 000000000..4c2b97d79 --- /dev/null +++ b/baseconfig/CONFIG_RESET_HSDK_V1 @@ -0,0 +1 @@ +# CONFIG_RESET_HSDK_V1 is not set diff --git a/baseconfig/CONFIG_RPMSG_QCOM_GLINK_SMEM b/baseconfig/CONFIG_RPMSG_QCOM_GLINK_SMEM new file mode 100644 index 000000000..c2c0a0c78 --- /dev/null +++ b/baseconfig/CONFIG_RPMSG_QCOM_GLINK_SMEM @@ -0,0 +1 @@ +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set diff --git a/baseconfig/CONFIG_STRING_SELFTEST b/baseconfig/CONFIG_STRING_SELFTEST new file mode 100644 index 000000000..dbff6d7fa --- /dev/null +++ b/baseconfig/CONFIG_STRING_SELFTEST @@ -0,0 +1 @@ +# CONFIG_STRING_SELFTEST is not set diff --git a/baseconfig/arm/CONFIG_MESON_GX_SOCINFO b/baseconfig/arm/CONFIG_MESON_GX_SOCINFO new file mode 100644 index 000000000..ce5ba6f4a --- /dev/null +++ b/baseconfig/arm/CONFIG_MESON_GX_SOCINFO @@ -0,0 +1 @@ +CONFIG_MESON_GX_SOCINFO=y diff --git a/baseconfig/arm/armv7/armv7/CONFIG_BATTERY_BQ27XXX_HDQ b/baseconfig/arm/armv7/armv7/CONFIG_BATTERY_BQ27XXX_HDQ new file mode 100644 index 000000000..2be078588 --- /dev/null +++ b/baseconfig/arm/armv7/armv7/CONFIG_BATTERY_BQ27XXX_HDQ @@ -0,0 +1 @@ +CONFIG_BATTERY_BQ27XXX_HDQ=m diff --git a/baseconfig/arm/armv7/armv7/CONFIG_IMX_REMOTEPROC b/baseconfig/arm/armv7/armv7/CONFIG_IMX_REMOTEPROC new file mode 100644 index 000000000..53983d8af --- /dev/null +++ b/baseconfig/arm/armv7/armv7/CONFIG_IMX_REMOTEPROC @@ -0,0 +1 @@ +CONFIG_IMX_REMOTEPROC=m diff --git a/baseconfig/x86/x86_64/CONFIG_DEVICE_PRIVATE b/baseconfig/x86/x86_64/CONFIG_DEVICE_PRIVATE new file mode 100644 index 000000000..ef0a4ad5b --- /dev/null +++ b/baseconfig/x86/x86_64/CONFIG_DEVICE_PRIVATE @@ -0,0 +1 @@ +CONFIG_DEVICE_PRIVATE=y diff --git a/baseconfig/x86/x86_64/CONFIG_DEVICE_PUBLIC b/baseconfig/x86/x86_64/CONFIG_DEVICE_PUBLIC new file mode 100644 index 000000000..c790e941b --- /dev/null +++ b/baseconfig/x86/x86_64/CONFIG_DEVICE_PUBLIC @@ -0,0 +1 @@ +CONFIG_DEVICE_PUBLIC=y diff --git a/baseconfig/x86/x86_64/CONFIG_HMM_MIRROR b/baseconfig/x86/x86_64/CONFIG_HMM_MIRROR new file mode 100644 index 000000000..11dfee6c1 --- /dev/null +++ b/baseconfig/x86/x86_64/CONFIG_HMM_MIRROR @@ -0,0 +1 @@ +CONFIG_HMM_MIRROR=y diff --git a/efi-lockdown.patch b/efi-lockdown.patch index a1a1eb11f..99ac78d89 100644 --- a/efi-lockdown.patch +++ b/efi-lockdown.patch @@ -1021,7 +1021,7 @@ index 43cb680..9be3e08 100644 + return -EPERM; + status = wmi_evaluate_method(ASUS_WMI_MGMT_GUID, - 1, asus->debug.method_id, + 0, asus->debug.method_id, &input, &output); -- 2.7.4 @@ -1 +1 @@ -015a9e66b9b8c1f28097ed09bf9350708e26249a +f007cad159e99fa2acd3b2e9364fbb32ad28b971 diff --git a/kernel-aarch64-debug.config b/kernel-aarch64-debug.config index 5d35fe0b5..d5af292ab 100644 --- a/kernel-aarch64-debug.config +++ b/kernel-aarch64-debug.config @@ -472,6 +472,7 @@ CONFIG_BATTERY_AXP20X=m # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -2950,6 +2951,7 @@ CONFIG_MEMSTICK_TIFM_MS=m CONFIG_MESON_EFUSE=m CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_GXL_PHY=m +CONFIG_MESON_GX_SOCINFO=y CONFIG_MESON_SARADC=m CONFIG_MESON_SM=y # CONFIG_MESON_WATCHDOG is not set @@ -4224,6 +4226,7 @@ CONFIG_QCOM_COINCELL=m CONFIG_QCOM_EMAC=m # CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set CONFIG_QCOM_FALKOR_ERRATUM_1009=y +# CONFIG_QCOM_GLINK_SSR is not set CONFIG_QCOM_GSBI=y CONFIG_QCOM_HIDMA=m CONFIG_QCOM_HIDMA_MGMT=m @@ -4409,6 +4412,7 @@ CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=y CONFIG_RESET_HISI=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SCI is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set @@ -4451,6 +4455,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set CONFIG_RPMSG=m CONFIG_RPMSG_QCOM_GLINK_RPM=m +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPMSG_QCOM_SMD=m CONFIG_RPR0521=m CONFIG_RSI_91X=m @@ -5487,6 +5492,7 @@ CONFIG_STMMAC_ETH=m CONFIG_STMMAC_PLATFORM=m # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_STUB_CLK_HI6220=y diff --git a/kernel-aarch64.config b/kernel-aarch64.config index c53d5553a..22d833528 100644 --- a/kernel-aarch64.config +++ b/kernel-aarch64.config @@ -472,6 +472,7 @@ CONFIG_BATTERY_AXP20X=m # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -2930,6 +2931,7 @@ CONFIG_MEMSTICK_TIFM_MS=m CONFIG_MESON_EFUSE=m CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_GXL_PHY=m +CONFIG_MESON_GX_SOCINFO=y CONFIG_MESON_SARADC=m CONFIG_MESON_SM=y # CONFIG_MESON_WATCHDOG is not set @@ -4202,6 +4204,7 @@ CONFIG_QCOM_COINCELL=m CONFIG_QCOM_EMAC=m # CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set CONFIG_QCOM_FALKOR_ERRATUM_1009=y +# CONFIG_QCOM_GLINK_SSR is not set CONFIG_QCOM_GSBI=y CONFIG_QCOM_HIDMA=m CONFIG_QCOM_HIDMA_MGMT=m @@ -4387,6 +4390,7 @@ CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=y CONFIG_RESET_HISI=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SCI is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set @@ -4429,6 +4433,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set CONFIG_RPMSG=m CONFIG_RPMSG_QCOM_GLINK_RPM=m +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPMSG_QCOM_SMD=m CONFIG_RPR0521=m CONFIG_RSI_91X=m @@ -5464,6 +5469,7 @@ CONFIG_STMMAC_ETH=m CONFIG_STMMAC_PLATFORM=m # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_STUB_CLK_HI6220=y diff --git a/kernel-armv7hl-debug.config b/kernel-armv7hl-debug.config index ab2595d6f..a0111561a 100644 --- a/kernel-armv7hl-debug.config +++ b/kernel-armv7hl-debug.config @@ -502,6 +502,7 @@ CONFIG_BATMAN_ADV_MCAST=y CONFIG_BATMAN_ADV_NC=y CONFIG_BATTERY_AXP20X=m # CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_BATTERY_BQ27XXX_HDQ=m CONFIG_BATTERY_BQ27XXX_I2C=m CONFIG_BATTERY_BQ27XXX=m CONFIG_BATTERY_DA9052=m @@ -513,6 +514,7 @@ CONFIG_BATTERY_DA9052=m # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m CONFIG_BATTERY_RX51=m CONFIG_BATTERY_SBS=m CONFIG_BATTERY_TWL4030_MADC=m @@ -2293,6 +2295,7 @@ CONFIG_IMX7_PM_DOMAINS=y CONFIG_IMX_DMA=m CONFIG_IMX_GPCV2=y CONFIG_IMX_IPUV3_CORE=m +CONFIG_IMX_REMOTEPROC=m CONFIG_IMX_SDMA=m CONFIG_IMX_THERMAL=m CONFIG_IMX_WEIM=y @@ -3148,6 +3151,7 @@ CONFIG_MEMSTICK_TIFM_MS=m CONFIG_MESON_EFUSE=m # CONFIG_MESON_GXBB_WATCHDOG is not set # CONFIG_MESON_GXL_PHY is not set +CONFIG_MESON_GX_SOCINFO=y CONFIG_MESON_SARADC=m CONFIG_MESON_SM=y CONFIG_MESON_WATCHDOG=m @@ -4542,6 +4546,7 @@ CONFIG_QCOM_CLK_SMD_RPM=m CONFIG_QCOM_COINCELL=m # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set CONFIG_QCOM_GSBI=m # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set @@ -4747,6 +4752,7 @@ CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SCI is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set @@ -4789,6 +4795,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set CONFIG_RPMSG=m CONFIG_RPMSG_QCOM_GLINK_RPM=m +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPMSG_QCOM_SMD=m CONFIG_RPR0521=m CONFIG_RSI_91X=m @@ -5964,6 +5971,7 @@ CONFIG_ST_REMOTEPROC=m CONFIG_STRICT_DEVMEM=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_STRICT_MODULE_RWX=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_ST_THERMAL=m diff --git a/kernel-armv7hl-lpae-debug.config b/kernel-armv7hl-lpae-debug.config index 997dc1831..c17711cb0 100644 --- a/kernel-armv7hl-lpae-debug.config +++ b/kernel-armv7hl-lpae-debug.config @@ -492,6 +492,7 @@ CONFIG_BATTERY_AXP20X=m # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m CONFIG_BATTERY_SBS=m CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -3004,6 +3005,7 @@ CONFIG_MEMSTICK_TIFM_MS=m CONFIG_MESON_EFUSE=m # CONFIG_MESON_GXBB_WATCHDOG is not set # CONFIG_MESON_GXL_PHY is not set +CONFIG_MESON_GX_SOCINFO=y CONFIG_MESON_SARADC=m CONFIG_MESON_SM=y CONFIG_MESON_WATCHDOG=m @@ -4286,6 +4288,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QCOM_PM8XXX_XOADC=m @@ -4459,6 +4462,7 @@ CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SCI is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set @@ -4500,6 +4504,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -5570,6 +5575,7 @@ CONFIG_STMMAC_PLATFORM=m CONFIG_STRICT_DEVMEM=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_STRICT_MODULE_RWX=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUN4I_EMAC=m diff --git a/kernel-armv7hl-lpae.config b/kernel-armv7hl-lpae.config index 68cb11f05..0ea4179f6 100644 --- a/kernel-armv7hl-lpae.config +++ b/kernel-armv7hl-lpae.config @@ -491,6 +491,7 @@ CONFIG_BATTERY_AXP20X=m # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m CONFIG_BATTERY_SBS=m CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -2984,6 +2985,7 @@ CONFIG_MEMSTICK_TIFM_MS=m CONFIG_MESON_EFUSE=m # CONFIG_MESON_GXBB_WATCHDOG is not set # CONFIG_MESON_GXL_PHY is not set +CONFIG_MESON_GX_SOCINFO=y CONFIG_MESON_SARADC=m CONFIG_MESON_SM=y CONFIG_MESON_WATCHDOG=m @@ -4264,6 +4266,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QCOM_PM8XXX_XOADC=m @@ -4437,6 +4440,7 @@ CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SCI is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set @@ -4478,6 +4482,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -5547,6 +5552,7 @@ CONFIG_STMMAC_PLATFORM=m CONFIG_STRICT_DEVMEM=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_STRICT_MODULE_RWX=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUN4I_EMAC=m diff --git a/kernel-armv7hl.config b/kernel-armv7hl.config index 24abb66c4..3480c6d15 100644 --- a/kernel-armv7hl.config +++ b/kernel-armv7hl.config @@ -501,6 +501,7 @@ CONFIG_BATMAN_ADV_MCAST=y CONFIG_BATMAN_ADV_NC=y CONFIG_BATTERY_AXP20X=m # CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_BATTERY_BQ27XXX_HDQ=m CONFIG_BATTERY_BQ27XXX_I2C=m CONFIG_BATTERY_BQ27XXX=m CONFIG_BATTERY_DA9052=m @@ -512,6 +513,7 @@ CONFIG_BATTERY_DA9052=m # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m CONFIG_BATTERY_RX51=m CONFIG_BATTERY_SBS=m CONFIG_BATTERY_TWL4030_MADC=m @@ -2276,6 +2278,7 @@ CONFIG_IMX7_PM_DOMAINS=y CONFIG_IMX_DMA=m CONFIG_IMX_GPCV2=y CONFIG_IMX_IPUV3_CORE=m +CONFIG_IMX_REMOTEPROC=m CONFIG_IMX_SDMA=m CONFIG_IMX_THERMAL=m CONFIG_IMX_WEIM=y @@ -3128,6 +3131,7 @@ CONFIG_MEMSTICK_TIFM_MS=m CONFIG_MESON_EFUSE=m # CONFIG_MESON_GXBB_WATCHDOG is not set # CONFIG_MESON_GXL_PHY is not set +CONFIG_MESON_GX_SOCINFO=y CONFIG_MESON_SARADC=m CONFIG_MESON_SM=y CONFIG_MESON_WATCHDOG=m @@ -4520,6 +4524,7 @@ CONFIG_QCOM_CLK_SMD_RPM=m CONFIG_QCOM_COINCELL=m # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set CONFIG_QCOM_GSBI=m # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set @@ -4725,6 +4730,7 @@ CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SCI is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set @@ -4767,6 +4773,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set CONFIG_RPMSG=m CONFIG_RPMSG_QCOM_GLINK_RPM=m +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPMSG_QCOM_SMD=m CONFIG_RPR0521=m CONFIG_RSI_91X=m @@ -5941,6 +5948,7 @@ CONFIG_ST_REMOTEPROC=m CONFIG_STRICT_DEVMEM=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_STRICT_MODULE_RWX=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_ST_THERMAL=m diff --git a/kernel-i686-PAE.config b/kernel-i686-PAE.config index e663c66b9..798bd6292 100644 --- a/kernel-i686-PAE.config +++ b/kernel-i686-PAE.config @@ -390,6 +390,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m CONFIG_BATTERY_OLPC=y # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m @@ -4040,6 +4041,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -4154,6 +4156,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -4182,6 +4185,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -5177,6 +5181,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-i686-PAEdebug.config b/kernel-i686-PAEdebug.config index 6c9e7ad82..b1db7c7fd 100644 --- a/kernel-i686-PAEdebug.config +++ b/kernel-i686-PAEdebug.config @@ -391,6 +391,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m CONFIG_BATTERY_OLPC=y # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m @@ -4061,6 +4062,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -4175,6 +4177,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -4203,6 +4206,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -5199,6 +5203,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-i686-debug.config b/kernel-i686-debug.config index d7e684751..ada04656a 100644 --- a/kernel-i686-debug.config +++ b/kernel-i686-debug.config @@ -391,6 +391,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m CONFIG_BATTERY_OLPC=y # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m @@ -4061,6 +4062,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -4175,6 +4177,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -4203,6 +4206,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -5199,6 +5203,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-i686.config b/kernel-i686.config index 6f20af809..1d2538336 100644 --- a/kernel-i686.config +++ b/kernel-i686.config @@ -390,6 +390,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m CONFIG_BATTERY_OLPC=y # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m @@ -4040,6 +4041,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -4154,6 +4156,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -4182,6 +4185,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -5177,6 +5181,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-ppc64-debug.config b/kernel-ppc64-debug.config index 12fa1da84..4042ba2d5 100644 --- a/kernel-ppc64-debug.config +++ b/kernel-ppc64-debug.config @@ -339,6 +339,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -3875,6 +3876,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -3988,6 +3990,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -4016,6 +4019,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -4985,6 +4989,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-ppc64.config b/kernel-ppc64.config index c35f0c8bf..ac0201de7 100644 --- a/kernel-ppc64.config +++ b/kernel-ppc64.config @@ -338,6 +338,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -3852,6 +3853,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -3965,6 +3967,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -3993,6 +3996,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -4961,6 +4965,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-ppc64le-debug.config b/kernel-ppc64le-debug.config index d8a87d4db..52999a8de 100644 --- a/kernel-ppc64le-debug.config +++ b/kernel-ppc64le-debug.config @@ -333,6 +333,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -3815,6 +3816,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -3928,6 +3930,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -3956,6 +3959,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -4914,6 +4918,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-ppc64le.config b/kernel-ppc64le.config index 99322ee78..17204633b 100644 --- a/kernel-ppc64le.config +++ b/kernel-ppc64le.config @@ -332,6 +332,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -3792,6 +3793,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -3905,6 +3907,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -3933,6 +3936,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -4890,6 +4894,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-ppc64p7-debug.config b/kernel-ppc64p7-debug.config index 765f0f44e..fe9581075 100644 --- a/kernel-ppc64p7-debug.config +++ b/kernel-ppc64p7-debug.config @@ -333,6 +333,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -3814,6 +3815,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -3927,6 +3929,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -3955,6 +3958,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -4913,6 +4917,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-ppc64p7.config b/kernel-ppc64p7.config index 6726e7c9c..c7558a6b8 100644 --- a/kernel-ppc64p7.config +++ b/kernel-ppc64p7.config @@ -332,6 +332,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -3791,6 +3792,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -3904,6 +3906,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -3932,6 +3935,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -4889,6 +4893,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-s390x-debug.config b/kernel-s390x-debug.config index 28c3da678..e3f0f23f2 100644 --- a/kernel-s390x-debug.config +++ b/kernel-s390x-debug.config @@ -334,6 +334,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -3704,6 +3705,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QDIO=m @@ -3821,6 +3823,7 @@ CONFIG_RELAY=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y # CONFIG_RESET_CONTROLLER is not set +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -3849,6 +3852,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -4810,6 +4814,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-s390x.config b/kernel-s390x.config index 00e767b6d..5fa7c8333 100644 --- a/kernel-s390x.config +++ b/kernel-s390x.config @@ -333,6 +333,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -3681,6 +3682,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QDIO=m @@ -3798,6 +3800,7 @@ CONFIG_RELAY=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y # CONFIG_RESET_CONTROLLER is not set +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -3826,6 +3829,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -4786,6 +4790,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-x86_64-debug.config b/kernel-x86_64-debug.config index c0260abe3..f407e4b7c 100644 --- a/kernel-x86_64-debug.config +++ b/kernel-x86_64-debug.config @@ -398,6 +398,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -1087,6 +1088,8 @@ CONFIG_DEV_DAX_PMEM=m CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m # CONFIG_DEVFREQ_GOV_USERSPACE is not set # CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVICE_PRIVATE=y +CONFIG_DEVICE_PUBLIC=y # CONFIG_DEVKMEM is not set CONFIG_DEVMEM=y CONFIG_DEVPORT=y @@ -1867,6 +1870,7 @@ CONFIG_HISAX_W6692=y CONFIG_HIST_TRIGGERS=y # CONFIG_HMC6352 is not set # CONFIG_HMC_DRV is not set +CONFIG_HMM_MIRROR=y CONFIG_HOLTEK_FF=y # CONFIG_HOSTAP is not set CONFIG_HOTPLUG_CPU=y @@ -4099,6 +4103,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -4214,6 +4219,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -4242,6 +4248,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -5247,6 +5254,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel-x86_64.config b/kernel-x86_64.config index 9dd07675c..e1562e1e6 100644 --- a/kernel-x86_64.config +++ b/kernel-x86_64.config @@ -397,6 +397,7 @@ CONFIG_BATMAN_ADV_NC=y # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_MAX17040 is not set CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1721X=m # CONFIG_BATTERY_SBS is not set CONFIG_BAYCOM_EPP=m CONFIG_BAYCOM_PAR=m @@ -1077,6 +1078,8 @@ CONFIG_DEV_DAX_PMEM=m CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m # CONFIG_DEVFREQ_GOV_USERSPACE is not set # CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVICE_PRIVATE=y +CONFIG_DEVICE_PUBLIC=y # CONFIG_DEVKMEM is not set CONFIG_DEVMEM=y CONFIG_DEVPORT=y @@ -1849,6 +1852,7 @@ CONFIG_HISAX_W6692=y CONFIG_HIST_TRIGGERS=y # CONFIG_HMC6352 is not set # CONFIG_HMC_DRV is not set +CONFIG_HMM_MIRROR=y CONFIG_HOLTEK_FF=y # CONFIG_HOSTAP is not set CONFIG_HOTPLUG_CPU=y @@ -4078,6 +4082,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set CONFIG_QEDE=m @@ -4193,6 +4198,7 @@ CONFIG_RELAY=y CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=m CONFIG_RESET_ATTACK_MITIGATION=y +# CONFIG_RESET_HSDK_V1 is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RFD_FTL is not set CONFIG_RFKILL_GPIO=m @@ -4221,6 +4227,7 @@ CONFIG_ROSE=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPR0521=m CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y @@ -5225,6 +5232,7 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STM_SOURCE_CONSOLE is not set CONFIG_STRICT_DEVMEM=y +# CONFIG_STRING_SELFTEST is not set CONFIG_STRIP_ASM_SYMS=y # CONFIG_STRIP is not set CONFIG_SUNDANCE=m diff --git a/kernel.spec b/kernel.spec index 6b0b129c0..392f1a94f 100644 --- a/kernel.spec +++ b/kernel.spec @@ -69,7 +69,7 @@ Summary: The Linux kernel # The rc snapshot level %global rcrev 0 # The git snapshot level -%define gitrev 3 +%define gitrev 4 # Set rpm version accordingly %define rpmversion 4.%{upstream_sublevel}.0 %endif @@ -187,8 +187,10 @@ Summary: The Linux kernel # and debuginfo generation. Currently we rely on the old alldebug setting. %global _build_id_links alldebug -# kernel PAE is only built on i686 and ARMv7. -%ifnarch i686 armv7hl +# kernel PAE is only built on ARMv7 in rawhide. +# Fedora 27 and earlier still support PAE, so change this on rebases. +# %ifnarch i686 armv7hl +%ifnarch armv7hl %define with_pae 0 %endif @@ -605,13 +607,6 @@ Patch310: qcom-msm89xx-fixes.patch # https://patchwork.kernel.org/patch/9831825/ # https://patchwork.kernel.org/patch/9833721/ -Patch311: arm-tegra-fix-gpu-iommu.patch - -# https://www.spinics.net/lists/linux-arm-msm/msg28203.html -Patch312: qcom-display-iommu.patch - -# https://patchwork.kernel.org/patch/9839803/ -Patch313: qcom-Force-host-mode-for-USB-on-apq8016-sbc.patch # http://www.spinics.net/lists/dri-devel/msg132235.html Patch320: bcm283x-vc4-Fix-OOPSes-from-trying-to-cache-a-partially-constructed-BO..patch @@ -636,17 +631,10 @@ Patch601: 0001-Input-gpio_keys-Allow-suppression-of-input-events-fo.patch Patch602: 0002-Input-soc_button_array-Suppress-power-button-presses.patch Patch610: 0010-Input-silead-Add-support-for-capactive-home-button-f.patch Patch611: 0011-Input-goodix-Add-support-for-capacitive-home-button.patch -# These patches are queued for 4.14 and can be dropped on rebase to 4.14-rc1 -Patch603: 0001-power-supply-max17042_battery-Add-support-for-ACPI-e.patch -Patch604: 0002-power-supply-max17042_battery-Fix-ACPI-interrupt-iss.patch -Patch615: 0015-i2c-cht-wc-Add-Intel-Cherry-Trail-Whiskey-Cove-SMBUS.patch # rhbz 1476467 Patch617: Fix-for-module-sig-verification.patch -# rhbz 1485086 -Patch619: pci-mark-amd-stoney-gpu-ats-as-broken.patch - # END OF PATCH DEFINITIONS %endif @@ -2201,6 +2189,9 @@ fi # # %changelog +* Mon Sep 11 2017 Justin M. Forbes <jforbes@fedoraproject.org> - 4.14.0-0.rc0.git4.1 +- Linux v4.13-11197-gf007cad159e9 + * Sat Sep 9 2017 Peter Robinson <pbrobinson@fedoraproject.org> - Only build ParPort support on x86 diff --git a/pci-mark-amd-stoney-gpu-ats-as-broken.patch b/pci-mark-amd-stoney-gpu-ats-as-broken.patch deleted file mode 100644 index 167c40223..000000000 --- a/pci-mark-amd-stoney-gpu-ats-as-broken.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 9b44b0b09decfbe388131a345ba780c57240a7a9 Mon Sep 17 00:00:00 2001 -From: Joerg Roedel <jroedel@suse.de> -Date: Tue, 11 Jul 2017 15:48:00 -0500 -Subject: PCI: Mark AMD Stoney GPU ATS as broken - -ATS is broken on this hardware and causes IOMMU stalls and system failure. -Disable ATS on these devices to make them usable again with IOMMU enabled. - -Note that the commit in the Fixes tag is not buggy; it just uncovers the -problem in the hardware by increasing the ATS flush rate. - -Link: https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020836.html -Link: https://bugzilla.redhat.com/show_bug.cgi?id=1409201 -Fixes: b1516a14657a ("iommu/amd: Implement flush queue") -Signed-off-by: Joerg Roedel <jroedel@suse.de> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> -Acked-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/pci/quirks.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index 6967c6b..15ee4e9 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -4681,3 +4681,18 @@ static void quirk_intel_no_flr(struct pci_dev *dev) - } - DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); - DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); -+ -+#ifdef CONFIG_PCI_ATS -+/* -+ * Some devices have a broken ATS implementation causing IOMMU stalls. -+ * Don't use ATS for those devices. -+ */ -+static void quirk_no_ats(struct pci_dev *pdev) -+{ -+ dev_info(&pdev->dev, "disabling ATS (broken on this device)\n"); -+ pdev->ats_cap = 0; -+} -+ -+/* AMD Stoney platform GPU */ -+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); -+#endif /* CONFIG_PCI_ATS */ --- -cgit v1.1 - diff --git a/qcom-Force-host-mode-for-USB-on-apq8016-sbc.patch b/qcom-Force-host-mode-for-USB-on-apq8016-sbc.patch deleted file mode 100644 index 4932539a3..000000000 --- a/qcom-Force-host-mode-for-USB-on-apq8016-sbc.patch +++ /dev/null @@ -1,93 +0,0 @@ -From patchwork Fri Jul 14 02:20:42 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2] arm64: dts: qcom: Force host mode for USB on apq8016-sbc -From: Stephen Boyd <sboyd@codeaurora.org> -X-Patchwork-Id: 9839803 -Message-Id: <20170714022042.13886-1-sboyd@codeaurora.org> -To: Andy Gross <andy.gross@linaro.org> -Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, Rob Clark <robdclark@gmail.com> -Date: Thu, 13 Jul 2017 19:20:42 -0700 - -Commit ed75d6a96905 ("arm64: dts: qcom: Collapse usb support into -one node") breaks host mode support on apq8016-sbc boards. This -is because the mux driver (tc7usb40mu) hasn't been merged. -Without that driver, we can't toggle the GPIO going to the mux to -route out the D+/D- lines to the USB hub that's on the board. - -One solution would be to totally revert this change, but that -opens us up to other problems when two USB drivers are operating -the same hardware block at the same time. Let's modify the DT so -that the USB controller is always in host mode and connected to -the hub so that things like USB keyboards and mouses work. This -is the mode that most people prefer anyway with these devices. We -also delete the usb-switch node because the binding was never -accepted upstream. - -In the future, we can add muxing support and then update the DT -to support both modes at runtime. Patches to support this are -already on the mailing list. - -Fixes: ed75d6a96905 ("arm64: dts: qcom: Collapse usb support into one node") -Reported-by: Rob Clark <robdclark@gmail.com> -Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> ---- - -I noticed that I accidently removed the vbus notifier part of the phy. -Without it, we'll change settings that shouldn't changed. The thing -that we don't have is the ID pin on this board, not the vbus. That's -the only difference from v1. - - arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 1 + - arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 13 ++++--------- - 2 files changed, 5 insertions(+), 9 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi -index d94640812194..790b7775b901 100644 ---- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi -+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi -@@ -17,6 +17,7 @@ - function = PMIC_GPIO_FUNC_NORMAL; - power-source = <PM8916_GPIO_VPH>; - input-disable; -+ output-high; - }; - }; - -diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi -index bd310ac1967a..bb9e29e6b164 100644 ---- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi -+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi -@@ -213,11 +213,14 @@ - }; - - usb@78d9000 { -- extcon = <&usb_id>, <&usb_id>; -+ extcon = <&usb_id>; - status = "okay"; - adp-disable; - hnp-disable; - srp-disable; -+ dr_mode = "host"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_sw_sel_pm>; - ulpi { - phy { - v1p8-supply = <&pm8916_l7>; -@@ -342,14 +345,6 @@ - pinctrl-0 = <&usb_id_default>; - }; - -- usb-switch { -- compatible = "toshiba,tc7usb40mu"; -- switch-gpios = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>; -- extcon = <&usb_id>; -- pinctrl-names = "default"; -- pinctrl-0 = <&usb_sw_sel_pm>; -- }; -- - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; diff --git a/qcom-display-iommu.patch b/qcom-display-iommu.patch deleted file mode 100644 index 87d4473c8..000000000 --- a/qcom-display-iommu.patch +++ /dev/null @@ -1,1960 +0,0 @@ -From patchwork Thu Jul 13 12:07:44 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [RESEND,1/4] Docs: dt: document qcom iommu bindings -From: Rob Clark <robdclark@gmail.com> -X-Patchwork-Id: 9838369 -Message-Id: <20170713120747.20490-2-robdclark@gmail.com> -To: iommu@lists.linux-foundation.org -Cc: linux-arm-msm@vger.kernel.org, Archit Taneja <architt@codeaurora.org>, - Rob Herring <robh@kernel.org>, Will Deacon <will.deacon@arm.com>, - Sricharan <sricharan@codeaurora.org>, - Mark Rutland <mark.rutland@arm.com>, Robin Murphy <robin.murphy@arm.com>, - Rob Clark <robdclark@gmail.com>, devicetree@vger.kernel.org -Date: Thu, 13 Jul 2017 08:07:44 -0400 - -Cc: devicetree@vger.kernel.org -Signed-off-by: Rob Clark <robdclark@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> ---- - .../devicetree/bindings/iommu/qcom,iommu.txt | 121 +++++++++++++++++++++ - 1 file changed, 121 insertions(+) - create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt - -diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt -new file mode 100644 -index 000000000000..b2641ceb2b40 ---- /dev/null -+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt -@@ -0,0 +1,121 @@ -+* QCOM IOMMU v1 Implementation -+ -+Qualcomm "B" family devices which are not compatible with arm-smmu have -+a similar looking IOMMU but without access to the global register space, -+and optionally requiring additional configuration to route context irqs -+to non-secure vs secure interrupt line. -+ -+** Required properties: -+ -+- compatible : Should be one of: -+ -+ "qcom,msm8916-iommu" -+ -+ Followed by "qcom,msm-iommu-v1". -+ -+- clock-names : Should be a pair of "iface" (required for IOMMUs -+ register group access) and "bus" (required for -+ the IOMMUs underlying bus access). -+ -+- clocks : Phandles for respective clocks described by -+ clock-names. -+ -+- #address-cells : must be 1. -+ -+- #size-cells : must be 1. -+ -+- #iommu-cells : Must be 1. Index identifies the context-bank #. -+ -+- ranges : Base address and size of the iommu context banks. -+ -+- qcom,iommu-secure-id : secure-id. -+ -+- List of sub-nodes, one per translation context bank. Each sub-node -+ has the following required properties: -+ -+ - compatible : Should be one of: -+ - "qcom,msm-iommu-v1-ns" : non-secure context bank -+ - "qcom,msm-iommu-v1-sec" : secure context bank -+ - reg : Base address and size of context bank within the iommu -+ - interrupts : The context fault irq. -+ -+** Optional properties: -+ -+- reg : Base address and size of the SMMU local base, should -+ be only specified if the iommu requires configuration -+ for routing of context bank irq's to secure vs non- -+ secure lines. (Ie. if the iommu contains secure -+ context banks) -+ -+ -+** Examples: -+ -+ apps_iommu: iommu@1e20000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ #iommu-cells = <1>; -+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; -+ ranges = <0 0x1e20000 0x40000>; -+ reg = <0x1ef0000 0x3000>; -+ clocks = <&gcc GCC_SMMU_CFG_CLK>, -+ <&gcc GCC_APSS_TCU_CLK>; -+ clock-names = "iface", "bus"; -+ qcom,iommu-secure-id = <17>; -+ -+ // mdp_0: -+ iommu-ctx@4000 { -+ compatible = "qcom,msm-iommu-v1-ns"; -+ reg = <0x4000 0x1000>; -+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ // venus_ns: -+ iommu-ctx@5000 { -+ compatible = "qcom,msm-iommu-v1-sec"; -+ reg = <0x5000 0x1000>; -+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ }; -+ -+ gpu_iommu: iommu@1f08000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ #iommu-cells = <1>; -+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; -+ ranges = <0 0x1f08000 0x10000>; -+ clocks = <&gcc GCC_SMMU_CFG_CLK>, -+ <&gcc GCC_GFX_TCU_CLK>; -+ clock-names = "iface", "bus"; -+ qcom,iommu-secure-id = <18>; -+ -+ // gfx3d_user: -+ iommu-ctx@1000 { -+ compatible = "qcom,msm-iommu-v1-ns"; -+ reg = <0x1000 0x1000>; -+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ // gfx3d_priv: -+ iommu-ctx@2000 { -+ compatible = "qcom,msm-iommu-v1-ns"; -+ reg = <0x2000 0x1000>; -+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ }; -+ -+ ... -+ -+ venus: video-codec@1d00000 { -+ ... -+ iommus = <&apps_iommu 5>; -+ }; -+ -+ mdp: mdp@1a01000 { -+ ... -+ iommus = <&apps_iommu 4>; -+ }; -+ -+ gpu@01c00000 { -+ ... -+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; -+ }; -From patchwork Thu Jul 13 12:07:45 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [RESEND,2/4] iommu: arm-smmu: split out register defines -From: Rob Clark <robdclark@gmail.com> -X-Patchwork-Id: 9838371 -Message-Id: <20170713120747.20490-3-robdclark@gmail.com> -To: iommu@lists.linux-foundation.org -Cc: linux-arm-msm@vger.kernel.org, Archit Taneja <architt@codeaurora.org>, - Rob Herring <robh@kernel.org>, Will Deacon <will.deacon@arm.com>, - Sricharan <sricharan@codeaurora.org>, - Mark Rutland <mark.rutland@arm.com>, Robin Murphy <robin.murphy@arm.com>, - Rob Clark <robdclark@gmail.com> -Date: Thu, 13 Jul 2017 08:07:45 -0400 - -I want to re-use some of these for qcom_iommu, which has (roughly) the -same context-bank registers. - -Signed-off-by: Rob Clark <robdclark@gmail.com> ---- - drivers/iommu/arm-smmu-regs.h | 227 ++++++++++++++++++++++++++++++++++++++++++ - drivers/iommu/arm-smmu.c | 203 +------------------------------------ - 2 files changed, 228 insertions(+), 202 deletions(-) - create mode 100644 drivers/iommu/arm-smmu-regs.h - -diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h -new file mode 100644 -index 000000000000..87589c863068 ---- /dev/null -+++ b/drivers/iommu/arm-smmu-regs.h -@@ -0,0 +1,227 @@ -+/* -+ * IOMMU API for ARM architected SMMU implementations. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2013 ARM Limited -+ * -+ * Author: Will Deacon <will.deacon@arm.com> -+ */ -+ -+#ifndef _ARM_SMMU_REGS_H -+#define _ARM_SMMU_REGS_H -+ -+/* Configuration registers */ -+#define ARM_SMMU_GR0_sCR0 0x0 -+#define sCR0_CLIENTPD (1 << 0) -+#define sCR0_GFRE (1 << 1) -+#define sCR0_GFIE (1 << 2) -+#define sCR0_EXIDENABLE (1 << 3) -+#define sCR0_GCFGFRE (1 << 4) -+#define sCR0_GCFGFIE (1 << 5) -+#define sCR0_USFCFG (1 << 10) -+#define sCR0_VMIDPNE (1 << 11) -+#define sCR0_PTM (1 << 12) -+#define sCR0_FB (1 << 13) -+#define sCR0_VMID16EN (1 << 31) -+#define sCR0_BSU_SHIFT 14 -+#define sCR0_BSU_MASK 0x3 -+ -+/* Auxiliary Configuration register */ -+#define ARM_SMMU_GR0_sACR 0x10 -+ -+/* Identification registers */ -+#define ARM_SMMU_GR0_ID0 0x20 -+#define ARM_SMMU_GR0_ID1 0x24 -+#define ARM_SMMU_GR0_ID2 0x28 -+#define ARM_SMMU_GR0_ID3 0x2c -+#define ARM_SMMU_GR0_ID4 0x30 -+#define ARM_SMMU_GR0_ID5 0x34 -+#define ARM_SMMU_GR0_ID6 0x38 -+#define ARM_SMMU_GR0_ID7 0x3c -+#define ARM_SMMU_GR0_sGFSR 0x48 -+#define ARM_SMMU_GR0_sGFSYNR0 0x50 -+#define ARM_SMMU_GR0_sGFSYNR1 0x54 -+#define ARM_SMMU_GR0_sGFSYNR2 0x58 -+ -+#define ID0_S1TS (1 << 30) -+#define ID0_S2TS (1 << 29) -+#define ID0_NTS (1 << 28) -+#define ID0_SMS (1 << 27) -+#define ID0_ATOSNS (1 << 26) -+#define ID0_PTFS_NO_AARCH32 (1 << 25) -+#define ID0_PTFS_NO_AARCH32S (1 << 24) -+#define ID0_CTTW (1 << 14) -+#define ID0_NUMIRPT_SHIFT 16 -+#define ID0_NUMIRPT_MASK 0xff -+#define ID0_NUMSIDB_SHIFT 9 -+#define ID0_NUMSIDB_MASK 0xf -+#define ID0_EXIDS (1 << 8) -+#define ID0_NUMSMRG_SHIFT 0 -+#define ID0_NUMSMRG_MASK 0xff -+ -+#define ID1_PAGESIZE (1 << 31) -+#define ID1_NUMPAGENDXB_SHIFT 28 -+#define ID1_NUMPAGENDXB_MASK 7 -+#define ID1_NUMS2CB_SHIFT 16 -+#define ID1_NUMS2CB_MASK 0xff -+#define ID1_NUMCB_SHIFT 0 -+#define ID1_NUMCB_MASK 0xff -+ -+#define ID2_OAS_SHIFT 4 -+#define ID2_OAS_MASK 0xf -+#define ID2_IAS_SHIFT 0 -+#define ID2_IAS_MASK 0xf -+#define ID2_UBS_SHIFT 8 -+#define ID2_UBS_MASK 0xf -+#define ID2_PTFS_4K (1 << 12) -+#define ID2_PTFS_16K (1 << 13) -+#define ID2_PTFS_64K (1 << 14) -+#define ID2_VMID16 (1 << 15) -+ -+#define ID7_MAJOR_SHIFT 4 -+#define ID7_MAJOR_MASK 0xf -+ -+/* Global TLB invalidation */ -+#define ARM_SMMU_GR0_TLBIVMID 0x64 -+#define ARM_SMMU_GR0_TLBIALLNSNH 0x68 -+#define ARM_SMMU_GR0_TLBIALLH 0x6c -+#define ARM_SMMU_GR0_sTLBGSYNC 0x70 -+#define ARM_SMMU_GR0_sTLBGSTATUS 0x74 -+#define sTLBGSTATUS_GSACTIVE (1 << 0) -+#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ -+#define TLB_SPIN_COUNT 10 -+ -+/* Stream mapping registers */ -+#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) -+#define SMR_VALID (1 << 31) -+#define SMR_MASK_SHIFT 16 -+#define SMR_ID_SHIFT 0 -+ -+#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) -+#define S2CR_CBNDX_SHIFT 0 -+#define S2CR_CBNDX_MASK 0xff -+#define S2CR_EXIDVALID (1 << 10) -+#define S2CR_TYPE_SHIFT 16 -+#define S2CR_TYPE_MASK 0x3 -+enum arm_smmu_s2cr_type { -+ S2CR_TYPE_TRANS, -+ S2CR_TYPE_BYPASS, -+ S2CR_TYPE_FAULT, -+}; -+ -+#define S2CR_PRIVCFG_SHIFT 24 -+#define S2CR_PRIVCFG_MASK 0x3 -+enum arm_smmu_s2cr_privcfg { -+ S2CR_PRIVCFG_DEFAULT, -+ S2CR_PRIVCFG_DIPAN, -+ S2CR_PRIVCFG_UNPRIV, -+ S2CR_PRIVCFG_PRIV, -+}; -+ -+/* Context bank attribute registers */ -+#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) -+#define CBAR_VMID_SHIFT 0 -+#define CBAR_VMID_MASK 0xff -+#define CBAR_S1_BPSHCFG_SHIFT 8 -+#define CBAR_S1_BPSHCFG_MASK 3 -+#define CBAR_S1_BPSHCFG_NSH 3 -+#define CBAR_S1_MEMATTR_SHIFT 12 -+#define CBAR_S1_MEMATTR_MASK 0xf -+#define CBAR_S1_MEMATTR_WB 0xf -+#define CBAR_TYPE_SHIFT 16 -+#define CBAR_TYPE_MASK 0x3 -+#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) -+#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) -+#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) -+#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) -+#define CBAR_IRPTNDX_SHIFT 24 -+#define CBAR_IRPTNDX_MASK 0xff -+ -+#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) -+#define CBA2R_RW64_32BIT (0 << 0) -+#define CBA2R_RW64_64BIT (1 << 0) -+#define CBA2R_VMID_SHIFT 16 -+#define CBA2R_VMID_MASK 0xffff -+ -+#define ARM_SMMU_CB_SCTLR 0x0 -+#define ARM_SMMU_CB_ACTLR 0x4 -+#define ARM_SMMU_CB_RESUME 0x8 -+#define ARM_SMMU_CB_TTBCR2 0x10 -+#define ARM_SMMU_CB_TTBR0 0x20 -+#define ARM_SMMU_CB_TTBR1 0x28 -+#define ARM_SMMU_CB_TTBCR 0x30 -+#define ARM_SMMU_CB_CONTEXTIDR 0x34 -+#define ARM_SMMU_CB_S1_MAIR0 0x38 -+#define ARM_SMMU_CB_S1_MAIR1 0x3c -+#define ARM_SMMU_CB_PAR 0x50 -+#define ARM_SMMU_CB_FSR 0x58 -+#define ARM_SMMU_CB_FAR 0x60 -+#define ARM_SMMU_CB_FSYNR0 0x68 -+#define ARM_SMMU_CB_S1_TLBIVA 0x600 -+#define ARM_SMMU_CB_S1_TLBIASID 0x610 -+#define ARM_SMMU_CB_S1_TLBIVAL 0x620 -+#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 -+#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 -+#define ARM_SMMU_CB_TLBSYNC 0x7f0 -+#define ARM_SMMU_CB_TLBSTATUS 0x7f4 -+#define ARM_SMMU_CB_ATS1PR 0x800 -+#define ARM_SMMU_CB_ATSR 0x8f0 -+ -+#define SCTLR_S1_ASIDPNE (1 << 12) -+#define SCTLR_CFCFG (1 << 7) -+#define SCTLR_CFIE (1 << 6) -+#define SCTLR_CFRE (1 << 5) -+#define SCTLR_E (1 << 4) -+#define SCTLR_AFE (1 << 2) -+#define SCTLR_TRE (1 << 1) -+#define SCTLR_M (1 << 0) -+ -+#define ARM_MMU500_ACTLR_CPRE (1 << 1) -+ -+#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26) -+#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8) -+ -+#define CB_PAR_F (1 << 0) -+ -+#define ATSR_ACTIVE (1 << 0) -+ -+#define RESUME_RETRY (0 << 0) -+#define RESUME_TERMINATE (1 << 0) -+ -+#define TTBCR2_SEP_SHIFT 15 -+#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT) -+#define TTBCR2_AS (1 << 4) -+ -+#define TTBRn_ASID_SHIFT 48 -+ -+#define FSR_MULTI (1 << 31) -+#define FSR_SS (1 << 30) -+#define FSR_UUT (1 << 8) -+#define FSR_ASF (1 << 7) -+#define FSR_TLBLKF (1 << 6) -+#define FSR_TLBMCF (1 << 5) -+#define FSR_EF (1 << 4) -+#define FSR_PF (1 << 3) -+#define FSR_AFF (1 << 2) -+#define FSR_TF (1 << 1) -+ -+#define FSR_IGN (FSR_AFF | FSR_ASF | \ -+ FSR_TLBMCF | FSR_TLBLKF) -+#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ -+ FSR_EF | FSR_PF | FSR_TF | FSR_IGN) -+ -+#define FSYNR0_WNR (1 << 4) -+ -+#endif /* _ARM_SMMU_REGS_H */ -diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c -index 7ec30b08b3bd..ca9c20f915a8 100644 ---- a/drivers/iommu/arm-smmu.c -+++ b/drivers/iommu/arm-smmu.c -@@ -54,6 +54,7 @@ - #include <linux/amba/bus.h> - - #include "io-pgtable.h" -+#include "arm-smmu-regs.h" - - /* Maximum number of context banks per SMMU */ - #define ARM_SMMU_MAX_CBS 128 -@@ -83,211 +84,9 @@ - #define smmu_write_atomic_lq writel_relaxed - #endif - --/* Configuration registers */ --#define ARM_SMMU_GR0_sCR0 0x0 --#define sCR0_CLIENTPD (1 << 0) --#define sCR0_GFRE (1 << 1) --#define sCR0_GFIE (1 << 2) --#define sCR0_EXIDENABLE (1 << 3) --#define sCR0_GCFGFRE (1 << 4) --#define sCR0_GCFGFIE (1 << 5) --#define sCR0_USFCFG (1 << 10) --#define sCR0_VMIDPNE (1 << 11) --#define sCR0_PTM (1 << 12) --#define sCR0_FB (1 << 13) --#define sCR0_VMID16EN (1 << 31) --#define sCR0_BSU_SHIFT 14 --#define sCR0_BSU_MASK 0x3 -- --/* Auxiliary Configuration register */ --#define ARM_SMMU_GR0_sACR 0x10 -- --/* Identification registers */ --#define ARM_SMMU_GR0_ID0 0x20 --#define ARM_SMMU_GR0_ID1 0x24 --#define ARM_SMMU_GR0_ID2 0x28 --#define ARM_SMMU_GR0_ID3 0x2c --#define ARM_SMMU_GR0_ID4 0x30 --#define ARM_SMMU_GR0_ID5 0x34 --#define ARM_SMMU_GR0_ID6 0x38 --#define ARM_SMMU_GR0_ID7 0x3c --#define ARM_SMMU_GR0_sGFSR 0x48 --#define ARM_SMMU_GR0_sGFSYNR0 0x50 --#define ARM_SMMU_GR0_sGFSYNR1 0x54 --#define ARM_SMMU_GR0_sGFSYNR2 0x58 -- --#define ID0_S1TS (1 << 30) --#define ID0_S2TS (1 << 29) --#define ID0_NTS (1 << 28) --#define ID0_SMS (1 << 27) --#define ID0_ATOSNS (1 << 26) --#define ID0_PTFS_NO_AARCH32 (1 << 25) --#define ID0_PTFS_NO_AARCH32S (1 << 24) --#define ID0_CTTW (1 << 14) --#define ID0_NUMIRPT_SHIFT 16 --#define ID0_NUMIRPT_MASK 0xff --#define ID0_NUMSIDB_SHIFT 9 --#define ID0_NUMSIDB_MASK 0xf --#define ID0_EXIDS (1 << 8) --#define ID0_NUMSMRG_SHIFT 0 --#define ID0_NUMSMRG_MASK 0xff -- --#define ID1_PAGESIZE (1 << 31) --#define ID1_NUMPAGENDXB_SHIFT 28 --#define ID1_NUMPAGENDXB_MASK 7 --#define ID1_NUMS2CB_SHIFT 16 --#define ID1_NUMS2CB_MASK 0xff --#define ID1_NUMCB_SHIFT 0 --#define ID1_NUMCB_MASK 0xff -- --#define ID2_OAS_SHIFT 4 --#define ID2_OAS_MASK 0xf --#define ID2_IAS_SHIFT 0 --#define ID2_IAS_MASK 0xf --#define ID2_UBS_SHIFT 8 --#define ID2_UBS_MASK 0xf --#define ID2_PTFS_4K (1 << 12) --#define ID2_PTFS_16K (1 << 13) --#define ID2_PTFS_64K (1 << 14) --#define ID2_VMID16 (1 << 15) -- --#define ID7_MAJOR_SHIFT 4 --#define ID7_MAJOR_MASK 0xf -- --/* Global TLB invalidation */ --#define ARM_SMMU_GR0_TLBIVMID 0x64 --#define ARM_SMMU_GR0_TLBIALLNSNH 0x68 --#define ARM_SMMU_GR0_TLBIALLH 0x6c --#define ARM_SMMU_GR0_sTLBGSYNC 0x70 --#define ARM_SMMU_GR0_sTLBGSTATUS 0x74 --#define sTLBGSTATUS_GSACTIVE (1 << 0) --#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ --#define TLB_SPIN_COUNT 10 -- --/* Stream mapping registers */ --#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) --#define SMR_VALID (1 << 31) --#define SMR_MASK_SHIFT 16 --#define SMR_ID_SHIFT 0 -- --#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) --#define S2CR_CBNDX_SHIFT 0 --#define S2CR_CBNDX_MASK 0xff --#define S2CR_EXIDVALID (1 << 10) --#define S2CR_TYPE_SHIFT 16 --#define S2CR_TYPE_MASK 0x3 --enum arm_smmu_s2cr_type { -- S2CR_TYPE_TRANS, -- S2CR_TYPE_BYPASS, -- S2CR_TYPE_FAULT, --}; -- --#define S2CR_PRIVCFG_SHIFT 24 --#define S2CR_PRIVCFG_MASK 0x3 --enum arm_smmu_s2cr_privcfg { -- S2CR_PRIVCFG_DEFAULT, -- S2CR_PRIVCFG_DIPAN, -- S2CR_PRIVCFG_UNPRIV, -- S2CR_PRIVCFG_PRIV, --}; -- --/* Context bank attribute registers */ --#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) --#define CBAR_VMID_SHIFT 0 --#define CBAR_VMID_MASK 0xff --#define CBAR_S1_BPSHCFG_SHIFT 8 --#define CBAR_S1_BPSHCFG_MASK 3 --#define CBAR_S1_BPSHCFG_NSH 3 --#define CBAR_S1_MEMATTR_SHIFT 12 --#define CBAR_S1_MEMATTR_MASK 0xf --#define CBAR_S1_MEMATTR_WB 0xf --#define CBAR_TYPE_SHIFT 16 --#define CBAR_TYPE_MASK 0x3 --#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) --#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) --#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) --#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) --#define CBAR_IRPTNDX_SHIFT 24 --#define CBAR_IRPTNDX_MASK 0xff -- --#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) --#define CBA2R_RW64_32BIT (0 << 0) --#define CBA2R_RW64_64BIT (1 << 0) --#define CBA2R_VMID_SHIFT 16 --#define CBA2R_VMID_MASK 0xffff -- - /* Translation context bank */ - #define ARM_SMMU_CB(smmu, n) ((smmu)->cb_base + ((n) << (smmu)->pgshift)) - --#define ARM_SMMU_CB_SCTLR 0x0 --#define ARM_SMMU_CB_ACTLR 0x4 --#define ARM_SMMU_CB_RESUME 0x8 --#define ARM_SMMU_CB_TTBCR2 0x10 --#define ARM_SMMU_CB_TTBR0 0x20 --#define ARM_SMMU_CB_TTBR1 0x28 --#define ARM_SMMU_CB_TTBCR 0x30 --#define ARM_SMMU_CB_CONTEXTIDR 0x34 --#define ARM_SMMU_CB_S1_MAIR0 0x38 --#define ARM_SMMU_CB_S1_MAIR1 0x3c --#define ARM_SMMU_CB_PAR 0x50 --#define ARM_SMMU_CB_FSR 0x58 --#define ARM_SMMU_CB_FAR 0x60 --#define ARM_SMMU_CB_FSYNR0 0x68 --#define ARM_SMMU_CB_S1_TLBIVA 0x600 --#define ARM_SMMU_CB_S1_TLBIASID 0x610 --#define ARM_SMMU_CB_S1_TLBIVAL 0x620 --#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 --#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 --#define ARM_SMMU_CB_TLBSYNC 0x7f0 --#define ARM_SMMU_CB_TLBSTATUS 0x7f4 --#define ARM_SMMU_CB_ATS1PR 0x800 --#define ARM_SMMU_CB_ATSR 0x8f0 -- --#define SCTLR_S1_ASIDPNE (1 << 12) --#define SCTLR_CFCFG (1 << 7) --#define SCTLR_CFIE (1 << 6) --#define SCTLR_CFRE (1 << 5) --#define SCTLR_E (1 << 4) --#define SCTLR_AFE (1 << 2) --#define SCTLR_TRE (1 << 1) --#define SCTLR_M (1 << 0) -- --#define ARM_MMU500_ACTLR_CPRE (1 << 1) -- --#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26) --#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8) -- --#define CB_PAR_F (1 << 0) -- --#define ATSR_ACTIVE (1 << 0) -- --#define RESUME_RETRY (0 << 0) --#define RESUME_TERMINATE (1 << 0) -- --#define TTBCR2_SEP_SHIFT 15 --#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT) --#define TTBCR2_AS (1 << 4) -- --#define TTBRn_ASID_SHIFT 48 -- --#define FSR_MULTI (1 << 31) --#define FSR_SS (1 << 30) --#define FSR_UUT (1 << 8) --#define FSR_ASF (1 << 7) --#define FSR_TLBLKF (1 << 6) --#define FSR_TLBMCF (1 << 5) --#define FSR_EF (1 << 4) --#define FSR_PF (1 << 3) --#define FSR_AFF (1 << 2) --#define FSR_TF (1 << 1) -- --#define FSR_IGN (FSR_AFF | FSR_ASF | \ -- FSR_TLBMCF | FSR_TLBLKF) --#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ -- FSR_EF | FSR_PF | FSR_TF | FSR_IGN) -- --#define FSYNR0_WNR (1 << 4) -- - #define MSI_IOVA_BASE 0x8000000 - #define MSI_IOVA_LENGTH 0x100000 - -From patchwork Thu Jul 13 12:07:46 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [RESEND,3/4] iommu: add qcom_iommu -From: Rob Clark <robdclark@gmail.com> -X-Patchwork-Id: 9838375 -Message-Id: <20170713120747.20490-4-robdclark@gmail.com> -To: iommu@lists.linux-foundation.org -Cc: linux-arm-msm@vger.kernel.org, Archit Taneja <architt@codeaurora.org>, - Rob Herring <robh@kernel.org>, Will Deacon <will.deacon@arm.com>, - Sricharan <sricharan@codeaurora.org>, - Mark Rutland <mark.rutland@arm.com>, Robin Murphy <robin.murphy@arm.com>, - Rob Clark <robdclark@gmail.com> -Date: Thu, 13 Jul 2017 08:07:46 -0400 - -An iommu driver for Qualcomm "B" family devices which do implement the -ARM SMMU spec, but not in a way that is compatible with how the arm-smmu -driver is designed. It seems SMMU_SCR1.GASRAE=1 so the global register -space is not accessible. This means it needs to get configuration from -devicetree instead of setting it up dynamically. - -In the end, other than register definitions, there is not much code to -share with arm-smmu (other than what has already been refactored out -into the pgtable helpers). - -Signed-off-by: Rob Clark <robdclark@gmail.com> -Tested-by: Riku Voipio <riku.voipio@linaro.org> ---- -v1: original -v2: bindings cleanups and kconfig issues that kbuild robot pointed out -v3: fix issues pointed out by Rob H. and actually make device removal - work -v4: fix WARN_ON() splats reported by Archit -v5: some fixes to build as a module.. note that it cannot actually - be built as a module yet (at minimum a bunch of other iommu syms - that are needed are not exported, but there may be more to it - than that), but at least qcom_iommu is ready should it become - possible to build iommu drivers as modules. -v6: Add additional pm-runtime get/puts around paths that can hit - TLB inv, to avoid unclocked register access if device using the - iommu is not powered on. And pre-emptively clear interrupts - before registering IRQ handler just in case the bootloader has - left us a surpise. -v7: Address review comments from Robin (don't associate iommu_group - with context bank, table lookup instead of list to find context - bank, etc) -v8: Fix silly bug on detach. Actually Robin already pointed it out - but I somehow overlooked that comment when preparing v7. - - drivers/iommu/Kconfig | 10 + - drivers/iommu/Makefile | 1 + - drivers/iommu/qcom_iommu.c | 868 +++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 879 insertions(+) - create mode 100644 drivers/iommu/qcom_iommu.c - -diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig -index 6ee3a25ae731..aa4b62893fe1 100644 ---- a/drivers/iommu/Kconfig -+++ b/drivers/iommu/Kconfig -@@ -367,4 +367,14 @@ config MTK_IOMMU_V1 - - if unsure, say N here. - -+config QCOM_IOMMU -+ # Note: iommu drivers cannot (yet?) be built as modules -+ bool "Qualcomm IOMMU Support" -+ depends on ARCH_QCOM || COMPILE_TEST -+ select IOMMU_API -+ select IOMMU_IO_PGTABLE_LPAE -+ select ARM_DMA_USE_IOMMU -+ help -+ Support for IOMMU on certain Qualcomm SoCs. -+ - endif # IOMMU_SUPPORT -diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile -index 195f7b997d8e..b910aea813a1 100644 ---- a/drivers/iommu/Makefile -+++ b/drivers/iommu/Makefile -@@ -27,3 +27,4 @@ obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o - obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o - obj-$(CONFIG_FSL_PAMU) += fsl_pamu.o fsl_pamu_domain.o - obj-$(CONFIG_S390_IOMMU) += s390-iommu.o -+obj-$(CONFIG_QCOM_IOMMU) += qcom_iommu.o -diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c -new file mode 100644 -index 000000000000..860cad1cb167 ---- /dev/null -+++ b/drivers/iommu/qcom_iommu.c -@@ -0,0 +1,868 @@ -+/* -+ * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. -+ * -+ * Copyright (C) 2013 ARM Limited -+ * Copyright (C) 2017 Red Hat -+ */ -+ -+#include <linux/atomic.h> -+#include <linux/clk.h> -+#include <linux/delay.h> -+#include <linux/dma-iommu.h> -+#include <linux/dma-mapping.h> -+#include <linux/err.h> -+#include <linux/interrupt.h> -+#include <linux/io.h> -+#include <linux/io-64-nonatomic-hi-lo.h> -+#include <linux/iommu.h> -+#include <linux/iopoll.h> -+#include <linux/kconfig.h> -+#include <linux/module.h> -+#include <linux/mutex.h> -+#include <linux/of.h> -+#include <linux/of_address.h> -+#include <linux/of_device.h> -+#include <linux/of_iommu.h> -+#include <linux/platform_device.h> -+#include <linux/pm.h> -+#include <linux/pm_runtime.h> -+#include <linux/qcom_scm.h> -+#include <linux/slab.h> -+#include <linux/spinlock.h> -+ -+#include "io-pgtable.h" -+#include "arm-smmu-regs.h" -+ -+#define SMMU_INTR_SEL_NS 0x2000 -+ -+struct qcom_iommu_ctx; -+ -+struct qcom_iommu_dev { -+ /* IOMMU core code handle */ -+ struct iommu_device iommu; -+ struct device *dev; -+ struct clk *iface_clk; -+ struct clk *bus_clk; -+ void __iomem *local_base; -+ u32 sec_id; -+ u8 num_ctxs; -+ struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid-1 */ -+}; -+ -+struct qcom_iommu_ctx { -+ struct device *dev; -+ void __iomem *base; -+ bool secure_init; -+ u8 asid; /* asid and ctx bank # are 1:1 */ -+}; -+ -+struct qcom_iommu_domain { -+ struct io_pgtable_ops *pgtbl_ops; -+ spinlock_t pgtbl_lock; -+ struct mutex init_mutex; /* Protects iommu pointer */ -+ struct iommu_domain domain; -+ struct qcom_iommu_dev *iommu; -+}; -+ -+static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom) -+{ -+ return container_of(dom, struct qcom_iommu_domain, domain); -+} -+ -+static const struct iommu_ops qcom_iommu_ops; -+ -+static struct qcom_iommu_dev * to_iommu(struct iommu_fwspec *fwspec) -+{ -+ if (!fwspec || fwspec->ops != &qcom_iommu_ops) -+ return NULL; -+ return fwspec->iommu_priv; -+} -+ -+static struct qcom_iommu_ctx * to_ctx(struct iommu_fwspec *fwspec, unsigned asid) -+{ -+ struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec); -+ if (!qcom_iommu) -+ return NULL; -+ return qcom_iommu->ctxs[asid - 1]; -+} -+ -+static inline void -+iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val) -+{ -+ writel_relaxed(val, ctx->base + reg); -+} -+ -+static inline void -+iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val) -+{ -+ writeq_relaxed(val, ctx->base + reg); -+} -+ -+static inline u32 -+iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg) -+{ -+ return readl_relaxed(ctx->base + reg); -+} -+ -+static inline u64 -+iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg) -+{ -+ return readq_relaxed(ctx->base + reg); -+} -+ -+static void qcom_iommu_tlb_sync(void *cookie) -+{ -+ struct iommu_fwspec *fwspec = cookie; -+ unsigned i; -+ -+ for (i = 0; i < fwspec->num_ids; i++) { -+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); -+ unsigned int val, ret; -+ -+ iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0); -+ -+ ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val, -+ (val & 0x1) == 0, 0, 5000000); -+ if (ret) -+ dev_err(ctx->dev, "timeout waiting for TLB SYNC\n"); -+ } -+} -+ -+static void qcom_iommu_tlb_inv_context(void *cookie) -+{ -+ struct iommu_fwspec *fwspec = cookie; -+ unsigned i; -+ -+ for (i = 0; i < fwspec->num_ids; i++) { -+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); -+ iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid); -+ } -+ -+ qcom_iommu_tlb_sync(cookie); -+} -+ -+static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size, -+ size_t granule, bool leaf, void *cookie) -+{ -+ struct iommu_fwspec *fwspec = cookie; -+ unsigned i, reg; -+ -+ reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; -+ -+ for (i = 0; i < fwspec->num_ids; i++) { -+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); -+ size_t s = size; -+ -+ iova &= ~12UL; -+ iova |= ctx->asid; -+ do { -+ iommu_writel(ctx, reg, iova); -+ iova += granule; -+ } while (s -= granule); -+ } -+} -+ -+static const struct iommu_gather_ops qcom_gather_ops = { -+ .tlb_flush_all = qcom_iommu_tlb_inv_context, -+ .tlb_add_flush = qcom_iommu_tlb_inv_range_nosync, -+ .tlb_sync = qcom_iommu_tlb_sync, -+}; -+ -+static irqreturn_t qcom_iommu_fault(int irq, void *dev) -+{ -+ struct qcom_iommu_ctx *ctx = dev; -+ u32 fsr, fsynr; -+ u64 iova; -+ -+ fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR); -+ -+ if (!(fsr & FSR_FAULT)) -+ return IRQ_NONE; -+ -+ fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0); -+ iova = iommu_readq(ctx, ARM_SMMU_CB_FAR); -+ -+ dev_err_ratelimited(ctx->dev, -+ "Unhandled context fault: fsr=0x%x, " -+ "iova=0x%016llx, fsynr=0x%x, cb=%d\n", -+ fsr, iova, fsynr, ctx->asid); -+ -+ iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr); -+ -+ return IRQ_HANDLED; -+} -+ -+static int qcom_iommu_init_domain(struct iommu_domain *domain, -+ struct qcom_iommu_dev *qcom_iommu, -+ struct iommu_fwspec *fwspec) -+{ -+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); -+ struct io_pgtable_ops *pgtbl_ops; -+ struct io_pgtable_cfg pgtbl_cfg; -+ int i, ret = 0; -+ u32 reg; -+ -+ mutex_lock(&qcom_domain->init_mutex); -+ if (qcom_domain->iommu) -+ goto out_unlock; -+ -+ pgtbl_cfg = (struct io_pgtable_cfg) { -+ .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap, -+ .ias = 32, -+ .oas = 40, -+ .tlb = &qcom_gather_ops, -+ .iommu_dev = qcom_iommu->dev, -+ }; -+ -+ qcom_domain->iommu = qcom_iommu; -+ pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, fwspec); -+ if (!pgtbl_ops) { -+ dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n"); -+ ret = -ENOMEM; -+ goto out_clear_iommu; -+ } -+ -+ /* Update the domain's page sizes to reflect the page table format */ -+ domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; -+ domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1; -+ domain->geometry.force_aperture = true; -+ -+ for (i = 0; i < fwspec->num_ids; i++) { -+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); -+ -+ if (!ctx->secure_init) { -+ ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid); -+ if (ret) { -+ dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret); -+ goto out_clear_iommu; -+ } -+ ctx->secure_init = true; -+ } -+ -+ /* TTBRs */ -+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, -+ pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] | -+ ((u64)ctx->asid << TTBRn_ASID_SHIFT)); -+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, -+ pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] | -+ ((u64)ctx->asid << TTBRn_ASID_SHIFT)); -+ -+ /* TTBCR */ -+ iommu_writel(ctx, ARM_SMMU_CB_TTBCR2, -+ (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | -+ TTBCR2_SEP_UPSTREAM); -+ iommu_writel(ctx, ARM_SMMU_CB_TTBCR, -+ pgtbl_cfg.arm_lpae_s1_cfg.tcr); -+ -+ /* MAIRs (stage-1 only) */ -+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, -+ pgtbl_cfg.arm_lpae_s1_cfg.mair[0]); -+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, -+ pgtbl_cfg.arm_lpae_s1_cfg.mair[1]); -+ -+ /* SCTLR */ -+ reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | -+ SCTLR_M | SCTLR_S1_ASIDPNE; -+ -+ if (IS_ENABLED(CONFIG_BIG_ENDIAN)) -+ reg |= SCTLR_E; -+ -+ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg); -+ } -+ -+ mutex_unlock(&qcom_domain->init_mutex); -+ -+ /* Publish page table ops for map/unmap */ -+ qcom_domain->pgtbl_ops = pgtbl_ops; -+ -+ return 0; -+ -+out_clear_iommu: -+ qcom_domain->iommu = NULL; -+out_unlock: -+ mutex_unlock(&qcom_domain->init_mutex); -+ return ret; -+} -+ -+static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type) -+{ -+ struct qcom_iommu_domain *qcom_domain; -+ -+ if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) -+ return NULL; -+ /* -+ * Allocate the domain and initialise some of its data structures. -+ * We can't really do anything meaningful until we've added a -+ * master. -+ */ -+ qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL); -+ if (!qcom_domain) -+ return NULL; -+ -+ if (type == IOMMU_DOMAIN_DMA && -+ iommu_get_dma_cookie(&qcom_domain->domain)) { -+ kfree(qcom_domain); -+ return NULL; -+ } -+ -+ mutex_init(&qcom_domain->init_mutex); -+ spin_lock_init(&qcom_domain->pgtbl_lock); -+ -+ return &qcom_domain->domain; -+} -+ -+static void qcom_iommu_domain_free(struct iommu_domain *domain) -+{ -+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); -+ -+ if (WARN_ON(qcom_domain->iommu)) /* forgot to detach? */ -+ return; -+ -+ iommu_put_dma_cookie(domain); -+ -+ /* NOTE: unmap can be called after client device is powered off, -+ * for example, with GPUs or anything involving dma-buf. So we -+ * cannot rely on the device_link. Make sure the IOMMU is on to -+ * avoid unclocked accesses in the TLB inv path: -+ */ -+ pm_runtime_get_sync(qcom_domain->iommu->dev); -+ -+ free_io_pgtable_ops(qcom_domain->pgtbl_ops); -+ -+ pm_runtime_put_sync(qcom_domain->iommu->dev); -+ -+ kfree(qcom_domain); -+} -+ -+static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) -+{ -+ struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec); -+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); -+ int ret; -+ -+ if (!qcom_iommu) { -+ dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n"); -+ return -ENXIO; -+ } -+ -+ /* Ensure that the domain is finalized */ -+ pm_runtime_get_sync(qcom_iommu->dev); -+ ret = qcom_iommu_init_domain(domain, qcom_iommu, dev->iommu_fwspec); -+ pm_runtime_put_sync(qcom_iommu->dev); -+ if (ret < 0) -+ return ret; -+ -+ /* -+ * Sanity check the domain. We don't support domains across -+ * different IOMMUs. -+ */ -+ if (qcom_domain->iommu != qcom_iommu) { -+ dev_err(dev, "cannot attach to IOMMU %s while already " -+ "attached to domain on IOMMU %s\n", -+ dev_name(qcom_domain->iommu->dev), -+ dev_name(qcom_iommu->dev)); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev) -+{ -+ struct iommu_fwspec *fwspec = dev->iommu_fwspec; -+ struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec); -+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); -+ unsigned i; -+ -+ if (!qcom_domain->iommu) -+ return; -+ -+ pm_runtime_get_sync(qcom_iommu->dev); -+ for (i = 0; i < fwspec->num_ids; i++) { -+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); -+ -+ /* Disable the context bank: */ -+ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); -+ } -+ pm_runtime_put_sync(qcom_iommu->dev); -+ -+ qcom_domain->iommu = NULL; -+} -+ -+static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova, -+ phys_addr_t paddr, size_t size, int prot) -+{ -+ int ret; -+ unsigned long flags; -+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); -+ struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; -+ -+ if (!ops) -+ return -ENODEV; -+ -+ spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); -+ ret = ops->map(ops, iova, paddr, size, prot); -+ spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); -+ return ret; -+} -+ -+static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova, -+ size_t size) -+{ -+ size_t ret; -+ unsigned long flags; -+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); -+ struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; -+ -+ if (!ops) -+ return 0; -+ -+ /* NOTE: unmap can be called after client device is powered off, -+ * for example, with GPUs or anything involving dma-buf. So we -+ * cannot rely on the device_link. Make sure the IOMMU is on to -+ * avoid unclocked accesses in the TLB inv path: -+ */ -+ pm_runtime_get_sync(qcom_domain->iommu->dev); -+ spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); -+ ret = ops->unmap(ops, iova, size); -+ spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); -+ pm_runtime_put_sync(qcom_domain->iommu->dev); -+ -+ return ret; -+} -+ -+static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain, -+ dma_addr_t iova) -+{ -+ phys_addr_t ret; -+ unsigned long flags; -+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); -+ struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; -+ -+ if (!ops) -+ return 0; -+ -+ spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); -+ ret = ops->iova_to_phys(ops, iova); -+ spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); -+ -+ return ret; -+} -+ -+static bool qcom_iommu_capable(enum iommu_cap cap) -+{ -+ switch (cap) { -+ case IOMMU_CAP_CACHE_COHERENCY: -+ /* -+ * Return true here as the SMMU can always send out coherent -+ * requests. -+ */ -+ return true; -+ case IOMMU_CAP_NOEXEC: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static int qcom_iommu_add_device(struct device *dev) -+{ -+ struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec); -+ struct iommu_group *group; -+ struct device_link *link; -+ -+ if (!qcom_iommu) -+ return -ENODEV; -+ -+ /* -+ * Establish the link between iommu and master, so that the -+ * iommu gets runtime enabled/disabled as per the master's -+ * needs. -+ */ -+ link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME); -+ if (!link) { -+ dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n", -+ dev_name(qcom_iommu->dev), dev_name(dev)); -+ return -ENODEV; -+ } -+ -+ group = iommu_group_get_for_dev(dev); -+ if (IS_ERR_OR_NULL(group)) -+ return PTR_ERR_OR_ZERO(group); -+ -+ iommu_group_put(group); -+ iommu_device_link(&qcom_iommu->iommu, dev); -+ -+ return 0; -+} -+ -+static void qcom_iommu_remove_device(struct device *dev) -+{ -+ struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec); -+ -+ if (!qcom_iommu) -+ return; -+ -+ iommu_device_unlink(&qcom_iommu->iommu, dev); -+ iommu_group_remove_device(dev); -+ iommu_fwspec_free(dev); -+} -+ -+static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) -+{ -+ struct qcom_iommu_dev *qcom_iommu; -+ struct platform_device *iommu_pdev; -+ unsigned asid = args->args[0]; -+ -+ if (args->args_count != 1) { -+ dev_err(dev, "incorrect number of iommu params found for %s " -+ "(found %d, expected 1)\n", -+ args->np->full_name, args->args_count); -+ return -EINVAL; -+ } -+ -+ iommu_pdev = of_find_device_by_node(args->np); -+ if (WARN_ON(!iommu_pdev)) -+ return -EINVAL; -+ -+ qcom_iommu = platform_get_drvdata(iommu_pdev); -+ -+ /* make sure the asid specified in dt is valid, so we don't have -+ * to sanity check this elsewhere, since 'asid - 1' is used to -+ * index into qcom_iommu->ctxs: -+ */ -+ if (WARN_ON(asid < 1) || -+ WARN_ON(asid > qcom_iommu->num_ctxs)) -+ return -EINVAL; -+ -+ if (!dev->iommu_fwspec->iommu_priv) { -+ dev->iommu_fwspec->iommu_priv = qcom_iommu; -+ } else { -+ /* make sure devices iommus dt node isn't referring to -+ * multiple different iommu devices. Multiple context -+ * banks are ok, but multiple devices are not: -+ */ -+ if (WARN_ON(qcom_iommu != dev->iommu_fwspec->iommu_priv)) -+ return -EINVAL; -+ } -+ -+ return iommu_fwspec_add_ids(dev, &asid, 1); -+} -+ -+static const struct iommu_ops qcom_iommu_ops = { -+ .capable = qcom_iommu_capable, -+ .domain_alloc = qcom_iommu_domain_alloc, -+ .domain_free = qcom_iommu_domain_free, -+ .attach_dev = qcom_iommu_attach_dev, -+ .detach_dev = qcom_iommu_detach_dev, -+ .map = qcom_iommu_map, -+ .unmap = qcom_iommu_unmap, -+ .map_sg = default_iommu_map_sg, -+ .iova_to_phys = qcom_iommu_iova_to_phys, -+ .add_device = qcom_iommu_add_device, -+ .remove_device = qcom_iommu_remove_device, -+ .device_group = generic_device_group, -+ .of_xlate = qcom_iommu_of_xlate, -+ .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, -+}; -+ -+static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu) -+{ -+ int ret; -+ -+ ret = clk_prepare_enable(qcom_iommu->iface_clk); -+ if (ret) { -+ dev_err(qcom_iommu->dev, "Couldn't enable iface_clk\n"); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(qcom_iommu->bus_clk); -+ if (ret) { -+ dev_err(qcom_iommu->dev, "Couldn't enable bus_clk\n"); -+ clk_disable_unprepare(qcom_iommu->iface_clk); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu) -+{ -+ clk_disable_unprepare(qcom_iommu->bus_clk); -+ clk_disable_unprepare(qcom_iommu->iface_clk); -+} -+ -+static int get_asid(const struct device_node *np) -+{ -+ u32 reg; -+ -+ /* read the "reg" property directly to get the relative address -+ * of the context bank, and calculate the asid from that: -+ */ -+ if (of_property_read_u32_index(np, "reg", 0, ®)) -+ return -ENODEV; -+ -+ return reg / 0x1000; /* context banks are 0x1000 apart */ -+} -+ -+static int qcom_iommu_ctx_probe(struct platform_device *pdev) -+{ -+ struct qcom_iommu_ctx *ctx; -+ struct device *dev = &pdev->dev; -+ struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent); -+ struct resource *res; -+ int ret, irq; -+ -+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); -+ if (!ctx) -+ return -ENOMEM; -+ -+ ctx->dev = dev; -+ platform_set_drvdata(pdev, ctx); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ ctx->base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(ctx->base)) -+ return PTR_ERR(ctx->base); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ dev_err(dev, "failed to get irq\n"); -+ return -ENODEV; -+ } -+ -+ /* clear IRQs before registering fault handler, just in case the -+ * boot-loader left us a surprise: -+ */ -+ iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR)); -+ -+ ret = devm_request_irq(dev, irq, -+ qcom_iommu_fault, -+ IRQF_SHARED, -+ "qcom-iommu-fault", -+ ctx); -+ if (ret) { -+ dev_err(dev, "failed to request IRQ %u\n", irq); -+ return ret; -+ } -+ -+ ret = get_asid(dev->of_node); -+ if (ret < 0) { -+ dev_err(dev, "missing reg property\n"); -+ return ret; -+ } -+ -+ ctx->asid = ret; -+ -+ dev_dbg(dev, "found asid %u\n", ctx->asid); -+ -+ qcom_iommu->ctxs[ctx->asid - 1] = ctx; -+ -+ return 0; -+} -+ -+static int qcom_iommu_ctx_remove(struct platform_device *pdev) -+{ -+ struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent); -+ struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev); -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ qcom_iommu->ctxs[ctx->asid - 1] = NULL; -+ -+ return 0; -+} -+ -+static const struct of_device_id ctx_of_match[] = { -+ { .compatible = "qcom,msm-iommu-v1-ns" }, -+ { .compatible = "qcom,msm-iommu-v1-sec" }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver qcom_iommu_ctx_driver = { -+ .driver = { -+ .name = "qcom-iommu-ctx", -+ .of_match_table = of_match_ptr(ctx_of_match), -+ }, -+ .probe = qcom_iommu_ctx_probe, -+ .remove = qcom_iommu_ctx_remove, -+}; -+ -+static int qcom_iommu_device_probe(struct platform_device *pdev) -+{ -+ struct device_node *child; -+ struct qcom_iommu_dev *qcom_iommu; -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ int ret, sz, max_asid = 0; -+ -+ /* find the max asid (which is 1:1 to ctx bank idx), so we know how -+ * many child ctx devices we have: -+ */ -+ for_each_child_of_node(dev->of_node, child) -+ max_asid = max(max_asid, get_asid(child)); -+ -+ sz = sizeof(*qcom_iommu) + (max_asid * sizeof(qcom_iommu->ctxs[0])); -+ -+ qcom_iommu = devm_kzalloc(dev, sz, GFP_KERNEL); -+ if (!qcom_iommu) -+ return -ENOMEM; -+ qcom_iommu->num_ctxs = max_asid; -+ qcom_iommu->dev = dev; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (res) -+ qcom_iommu->local_base = devm_ioremap_resource(dev, res); -+ -+ qcom_iommu->iface_clk = devm_clk_get(dev, "iface"); -+ if (IS_ERR(qcom_iommu->iface_clk)) { -+ dev_err(dev, "failed to get iface clock\n"); -+ return PTR_ERR(qcom_iommu->iface_clk); -+ } -+ -+ qcom_iommu->bus_clk = devm_clk_get(dev, "bus"); -+ if (IS_ERR(qcom_iommu->bus_clk)) { -+ dev_err(dev, "failed to get bus clock\n"); -+ return PTR_ERR(qcom_iommu->bus_clk); -+ } -+ -+ if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id", -+ &qcom_iommu->sec_id)) { -+ dev_err(dev, "missing qcom,iommu-secure-id property\n"); -+ return -ENODEV; -+ } -+ -+ platform_set_drvdata(pdev, qcom_iommu); -+ -+ pm_runtime_enable(dev); -+ -+ /* register context bank devices, which are child nodes: */ -+ ret = devm_of_platform_populate(dev); -+ if (ret) { -+ dev_err(dev, "Failed to populate iommu contexts\n"); -+ return ret; -+ } -+ -+ ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL, -+ dev_name(dev)); -+ if (ret) { -+ dev_err(dev, "Failed to register iommu in sysfs\n"); -+ return ret; -+ } -+ -+ iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops); -+ iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode); -+ -+ ret = iommu_device_register(&qcom_iommu->iommu); -+ if (ret) { -+ dev_err(dev, "Failed to register iommu\n"); -+ return ret; -+ } -+ -+ bus_set_iommu(&platform_bus_type, &qcom_iommu_ops); -+ -+ if (qcom_iommu->local_base) { -+ pm_runtime_get_sync(dev); -+ writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS); -+ pm_runtime_put_sync(dev); -+ } -+ -+ return 0; -+} -+ -+static int qcom_iommu_device_remove(struct platform_device *pdev) -+{ -+ struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev); -+ -+ bus_set_iommu(&platform_bus_type, NULL); -+ -+ pm_runtime_force_suspend(&pdev->dev); -+ platform_set_drvdata(pdev, NULL); -+ iommu_device_sysfs_remove(&qcom_iommu->iommu); -+ iommu_device_unregister(&qcom_iommu->iommu); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static int qcom_iommu_resume(struct device *dev) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev); -+ -+ return qcom_iommu_enable_clocks(qcom_iommu); -+} -+ -+static int qcom_iommu_suspend(struct device *dev) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev); -+ -+ qcom_iommu_disable_clocks(qcom_iommu); -+ -+ return 0; -+} -+#endif -+ -+static const struct dev_pm_ops qcom_iommu_pm_ops = { -+ SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL) -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) -+}; -+ -+static const struct of_device_id qcom_iommu_of_match[] = { -+ { .compatible = "qcom,msm-iommu-v1" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, qcom_iommu_of_match); -+ -+static struct platform_driver qcom_iommu_driver = { -+ .driver = { -+ .name = "qcom-iommu", -+ .of_match_table = of_match_ptr(qcom_iommu_of_match), -+ .pm = &qcom_iommu_pm_ops, -+ }, -+ .probe = qcom_iommu_device_probe, -+ .remove = qcom_iommu_device_remove, -+}; -+ -+static int __init qcom_iommu_init(void) -+{ -+ int ret; -+ -+ ret = platform_driver_register(&qcom_iommu_ctx_driver); -+ if (ret) -+ return ret; -+ -+ ret = platform_driver_register(&qcom_iommu_driver); -+ if (ret) -+ platform_driver_unregister(&qcom_iommu_ctx_driver); -+ -+ return ret; -+} -+ -+static void __exit qcom_iommu_exit(void) -+{ -+ platform_driver_unregister(&qcom_iommu_driver); -+ platform_driver_unregister(&qcom_iommu_ctx_driver); -+} -+ -+module_init(qcom_iommu_init); -+module_exit(qcom_iommu_exit); -+ -+IOMMU_OF_DECLARE(qcom_iommu_dev, "qcom,msm-iommu-v1", NULL); -+ -+MODULE_DESCRIPTION("IOMMU API for QCOM IOMMU v1 implementations"); -+MODULE_LICENSE("GPL v2"); -From patchwork Thu Jul 13 12:07:47 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [RESEND,4/4] iommu: qcom: initialize secure page table -From: Rob Clark <robdclark@gmail.com> -X-Patchwork-Id: 9838373 -Message-Id: <20170713120747.20490-5-robdclark@gmail.com> -To: iommu@lists.linux-foundation.org -Cc: linux-arm-msm@vger.kernel.org, Archit Taneja <architt@codeaurora.org>, - Rob Herring <robh@kernel.org>, Will Deacon <will.deacon@arm.com>, - Sricharan <sricharan@codeaurora.org>, - Mark Rutland <mark.rutland@arm.com>, Robin Murphy <robin.murphy@arm.com>, - Stanimir Varbanov <stanimir.varbanov@linaro.org>, - Rob Clark <robdclark@gmail.com> -Date: Thu, 13 Jul 2017 08:07:47 -0400 - -From: Stanimir Varbanov <stanimir.varbanov@linaro.org> - -This basically gets the secure page table size, allocates memory for -secure pagetables and passes the physical address to the trusted zone. - -Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> -Signed-off-by: Rob Clark <robdclark@gmail.com> ---- - drivers/iommu/qcom_iommu.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 64 insertions(+) - -diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c -index 860cad1cb167..48b62aa52787 100644 ---- a/drivers/iommu/qcom_iommu.c -+++ b/drivers/iommu/qcom_iommu.c -@@ -604,6 +604,51 @@ static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu) - clk_disable_unprepare(qcom_iommu->iface_clk); - } - -+static int qcom_iommu_sec_ptbl_init(struct device *dev) -+{ -+ size_t psize = 0; -+ unsigned int spare = 0; -+ void *cpu_addr; -+ dma_addr_t paddr; -+ unsigned long attrs; -+ static bool allocated = false; -+ int ret; -+ -+ if (allocated) -+ return 0; -+ -+ ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize); -+ if (ret) { -+ dev_err(dev, "failed to get iommu secure pgtable size (%d)\n", -+ ret); -+ return ret; -+ } -+ -+ dev_info(dev, "iommu sec: pgtable size: %zu\n", psize); -+ -+ attrs = DMA_ATTR_NO_KERNEL_MAPPING; -+ -+ cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs); -+ if (!cpu_addr) { -+ dev_err(dev, "failed to allocate %zu bytes for pgtable\n", -+ psize); -+ return -ENOMEM; -+ } -+ -+ ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare); -+ if (ret) { -+ dev_err(dev, "failed to init iommu pgtable (%d)\n", ret); -+ goto free_mem; -+ } -+ -+ allocated = true; -+ return 0; -+ -+free_mem: -+ dma_free_attrs(dev, psize, cpu_addr, paddr, attrs); -+ return ret; -+} -+ - static int get_asid(const struct device_node *np) - { - u32 reg; -@@ -700,6 +745,17 @@ static struct platform_driver qcom_iommu_ctx_driver = { - .remove = qcom_iommu_ctx_remove, - }; - -+static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu) -+{ -+ struct device_node *child; -+ -+ for_each_child_of_node(qcom_iommu->dev->of_node, child) -+ if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) -+ return true; -+ -+ return false; -+} -+ - static int qcom_iommu_device_probe(struct platform_device *pdev) - { - struct device_node *child; -@@ -744,6 +800,14 @@ static int qcom_iommu_device_probe(struct platform_device *pdev) - return -ENODEV; - } - -+ if (qcom_iommu_has_secure_context(qcom_iommu)) { -+ ret = qcom_iommu_sec_ptbl_init(dev); -+ if (ret) { -+ dev_err(dev, "cannot init secure pg table(%d)\n", ret); -+ return ret; -+ } -+ } -+ - platform_set_drvdata(pdev, qcom_iommu); - - pm_runtime_enable(dev); -From patchwork Mon Jun 12 12:43:15 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [1/3] ARM64: DT: add gpu for msm8916 -From: Rob Clark <robdclark@gmail.com> -X-Patchwork-Id: 9781057 -Message-Id: <20170612124317.29313-1-robdclark@gmail.com> -To: linux-arm-msm@vger.kernel.org -Cc: Stephen Boyd <sboyd@codeaurora.org>, Andy Gross <agross@codeaurora.org>, - Stanimir Varbanov <stanimir.varbanov@linaro.org>, - Rob Clark <robdclark@gmail.com> -Date: Mon, 12 Jun 2017 08:43:15 -0400 - -Signed-off-by: Rob Clark <robdclark@gmail.com> -Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> ---- - arch/arm64/boot/dts/qcom/msm8916.dtsi | 35 +++++++++++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi -index ab30939..24c24ab 100644 ---- a/arch/arm64/boot/dts/qcom/msm8916.dtsi -+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi -@@ -204,6 +204,17 @@ - - }; - -+ gpu_opp_table: opp_table { -+ compatible = "operating-points-v2"; -+ -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ }; -+ opp-19200000 { -+ opp-hz = /bits/ 64 <19200000>; -+ }; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, -@@ -698,6 +709,30 @@ - #thermal-sensor-cells = <1>; - }; - -+ gpu@1c00000 { -+ compatible = "qcom,adreno-306.0", "qcom,adreno"; -+ reg = <0x01c00000 0x20000>; -+ reg-names = "kgsl_3d0_reg_memory"; -+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "kgsl_3d0_irq"; -+ clock-names = -+ "core", -+ "iface", -+ "mem", -+ "mem_iface", -+ "alt_mem_iface", -+ "gfx3d"; -+ clocks = -+ <&gcc GCC_OXILI_GFX3D_CLK>, -+ <&gcc GCC_OXILI_AHB_CLK>, -+ <&gcc GCC_OXILI_GMEM_CLK>, -+ <&gcc GCC_BIMC_GFX_CLK>, -+ <&gcc GCC_BIMC_GPU_CLK>, -+ <&gcc GFX3D_CLK_SRC>; -+ power-domains = <&gcc OXILI_GDSC>; -+ operating-points-v2 = <&gpu_opp_table>; -+ }; -+ - mdss: mdss@1a00000 { - compatible = "qcom,mdss"; - reg = <0x1a00000 0x1000>, -From patchwork Mon Jun 12 12:43:16 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [2/3] ARM64: DT: add video codec devicetree node -From: Rob Clark <robdclark@gmail.com> -X-Patchwork-Id: 9781059 -Message-Id: <20170612124317.29313-2-robdclark@gmail.com> -To: linux-arm-msm@vger.kernel.org -Cc: Stephen Boyd <sboyd@codeaurora.org>, Andy Gross <agross@codeaurora.org>, - Stanimir Varbanov <stanimir.varbanov@linaro.org>, - Rob Clark <robdclark@gmail.com> -Date: Mon, 12 Jun 2017 08:43:16 -0400 - -From: Stanimir Varbanov <stanimir.varbanov@linaro.org> - -Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> -Signed-off-by: Rob Clark <robdclark@gmail.com> -Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> ---- - arch/arm64/boot/dts/qcom/msm8916.dtsi | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi -index 24c24ab..1dcd632 100644 ---- a/arch/arm64/boot/dts/qcom/msm8916.dtsi -+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi -@@ -88,6 +88,13 @@ - no-map; - }; - -+ venus_mem: venus@89900000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x0 0x89900000 0x0 0x800000>; -+ alignment = <0x1000>; -+ no-map; -+ }; -+ - mba_mem: mba@8ea00000 { - no-map; - reg = <0 0x8ea00000 0 0x100000>; -@@ -1214,6 +1221,27 @@ - }; - }; - }; -+ -+ venus: video-codec@1d00000 { -+ compatible = "qcom,msm8916-venus"; -+ reg = <0x01d00000 0xff000>; -+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; -+ power-domains = <&gcc VENUS_GDSC>; -+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, -+ <&gcc GCC_VENUS0_AHB_CLK>, -+ <&gcc GCC_VENUS0_AXI_CLK>; -+ clock-names = "core", "iface", "bus"; -+ memory-region = <&venus_mem>; -+ status = "okay"; -+ -+ video-decoder { -+ compatible = "venus-decoder"; -+ }; -+ -+ video-encoder { -+ compatible = "venus-encoder"; -+ }; -+ }; - }; - - smd { -From patchwork Mon Jun 12 12:43:17 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [3/3] ARM64: DT: add iommu for msm8916 -From: Rob Clark <robdclark@gmail.com> -X-Patchwork-Id: 9781061 -Message-Id: <20170612124317.29313-3-robdclark@gmail.com> -To: linux-arm-msm@vger.kernel.org -Cc: Stephen Boyd <sboyd@codeaurora.org>, Andy Gross <agross@codeaurora.org>, - Stanimir Varbanov <stanimir.varbanov@linaro.org>, - Rob Clark <robdclark@gmail.com> -Date: Mon, 12 Jun 2017 08:43:17 -0400 - -Signed-off-by: Rob Clark <robdclark@gmail.com> -Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> ---- - arch/arm64/boot/dts/qcom/msm8916.dtsi | 57 +++++++++++++++++++++++++++++++++++ - 1 file changed, 57 insertions(+) - -diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi -index 1dcd632..9a1d7ef 100644 ---- a/arch/arm64/boot/dts/qcom/msm8916.dtsi -+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi -@@ -716,6 +716,59 @@ - #thermal-sensor-cells = <1>; - }; - -+ apps_iommu: iommu@1ef0000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ #iommu-cells = <1>; -+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; -+ ranges = <0 0x1e20000 0x40000>; -+ reg = <0x1ef0000 0x3000>; -+ clocks = <&gcc GCC_SMMU_CFG_CLK>, -+ <&gcc GCC_APSS_TCU_CLK>; -+ clock-names = "iface", "bus"; -+ qcom,iommu-secure-id = <17>; -+ -+ // mdp_0: -+ iommu-ctx@4000 { -+ compatible = "qcom,msm-iommu-v1-ns"; -+ reg = <0x4000 0x1000>; -+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ // venus_ns: -+ iommu-ctx@5000 { -+ compatible = "qcom,msm-iommu-v1-sec"; -+ reg = <0x5000 0x1000>; -+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ }; -+ -+ gpu_iommu: iommu@1f08000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ #iommu-cells = <1>; -+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; -+ ranges = <0 0x1f08000 0x10000>; -+ clocks = <&gcc GCC_SMMU_CFG_CLK>, -+ <&gcc GCC_GFX_TCU_CLK>; -+ clock-names = "iface", "bus"; -+ qcom,iommu-secure-id = <18>; -+ -+ // gfx3d_user: -+ iommu-ctx@1000 { -+ compatible = "qcom,msm-iommu-v1-ns"; -+ reg = <0x1000 0x1000>; -+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ // gfx3d_priv: -+ iommu-ctx@2000 { -+ compatible = "qcom,msm-iommu-v1-ns"; -+ reg = <0x2000 0x1000>; -+ interrupts = <GIC_SPI 242 0>; -+ }; -+ }; -+ - gpu@1c00000 { - compatible = "qcom,adreno-306.0", "qcom,adreno"; - reg = <0x01c00000 0x20000>; -@@ -738,6 +791,7 @@ - <&gcc GFX3D_CLK_SRC>; - power-domains = <&gcc OXILI_GDSC>; - operating-points-v2 = <&gpu_opp_table>; -+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; - }; - - mdss: mdss@1a00000 { -@@ -781,6 +835,8 @@ - "core_clk", - "vsync_clk"; - -+ iommus = <&apps_iommu 4>; -+ - ports { - #address-cells = <1>; - #size-cells = <0>; -@@ -1231,6 +1287,7 @@ - <&gcc GCC_VENUS0_AHB_CLK>, - <&gcc GCC_VENUS0_AXI_CLK>; - clock-names = "core", "iface", "bus"; -+ iommus = <&apps_iommu 5>; - memory-region = <&venus_mem>; - status = "okay"; - diff --git a/qcom-msm89xx-fixes.patch b/qcom-msm89xx-fixes.patch index 4b5db8422..f7ac2815c 100644 --- a/qcom-msm89xx-fixes.patch +++ b/qcom-msm89xx-fixes.patch @@ -1,81 +1,3 @@ -From 283d0e00a18b294ec56f1fb904896a546704faaf Mon Sep 17 00:00:00 2001 -From: Rob Clark <robdclark@gmail.com> -Date: Fri, 30 Jun 2017 11:47:21 -0400 -Subject: [PATCH 3/6] soc: qcom: smsm: fix of_node refcnting problem - -of_find_node_with_property() drops the reference to the 'from' node, -which eventually (after enough -EPROBE_DEFERs) drops the last reference -to the node causing all sorts of fun problems, and this nice splat. - - BUG: sleeping function called from invalid context at ../kernel/locking/mutex.c:747 - in_atomic(): 1, irqs_disabled(): 128, pid: 33, name: kworker/0:1 - 4 locks held by kworker/0:1/33: - #0: ("events"){.+.+.+}, at: [<ffff0000080fa91c>] process_one_work+0x1a4/0x728 - #1: (deferred_probe_work){+.+.+.}, at: [<ffff0000080fa91c>] process_one_work+0x1a4/0x728 - #2: (&dev->mutex){......}, at: [<ffff000008676078>] __device_attach+0x30/0x168 - #3: (devtree_lock){......}, at: [<ffff000008828fd0>] of_find_node_with_property+0x30/0xe0 - irq event stamp: 18976 - hardirqs last enabled at (18975): [<ffff00000815794c>] __down_trylock_console_sem+0x74/0xb8 - hardirqs last disabled at (18976): [<ffff0000089e26d4>] _raw_spin_lock_irqsave+0x2c/0x78 - softirqs last enabled at (16880): [<ffff0000080e0f00>] __do_softirq+0x580/0x640 - softirqs last disabled at (16871): [<ffff0000080e13a4>] irq_exit+0xe4/0x138 - CPU: 0 PID: 33 Comm: kworker/0:1 Tainted: G E 4.12.0-rc5+ #1455 - Hardware name: qualcomm dragonboard410c/dragonboard410c, BIOS 2017.07-rc1-00234-g22fa70a-dirty 06/26/2017 - Workqueue: events deferred_probe_work_func - Call trace: - [<ffff000008089ee0>] dump_backtrace+0x0/0x230 - [<ffff00000808a134>] show_stack+0x24/0x30 - [<ffff0000084e1944>] dump_stack+0xac/0xe8 - [<ffff00000810d7e0>] ___might_sleep+0x150/0x230 - [<ffff00000810d918>] __might_sleep+0x58/0x90 - [<ffff0000089dde18>] __mutex_lock+0x50/0x870 - [<ffff0000089de674>] mutex_lock_nested+0x3c/0x50 - [<ffff000008388ae0>] kernfs_remove+0x30/0x50 - [<ffff00000838b720>] sysfs_remove_dir+0x58/0x70 - [<ffff0000084e393c>] kobject_del+0x1c/0x58 - [<ffff0000084e374c>] kobject_put+0xb4/0x208 - [<ffff00000882c364>] of_node_put+0x24/0x30 - [<ffff000008829018>] of_find_node_with_property+0x78/0xe0 - [<ffff000000aff5f4>] qcom_smsm_probe+0x194/0x720 [smsm] - [<ffff0000086793b4>] platform_drv_probe+0x74/0x110 - [<ffff0000086765bc>] driver_probe_device+0x2b4/0x420 - [<ffff000008676920>] __device_attach_driver+0xd0/0x150 - [<ffff000008673e78>] bus_for_each_drv+0x68/0xa8 - [<ffff00000867611c>] __device_attach+0xd4/0x168 - [<ffff000008676a1c>] device_initial_probe+0x24/0x30 - [<ffff000008675380>] bus_probe_device+0xa0/0xa8 - [<ffff000008675948>] deferred_probe_work_func+0xb8/0xf8 - [<ffff0000080fa9d4>] process_one_work+0x25c/0x728 - [<ffff0000080faef4>] worker_thread+0x54/0x3d8 - [<ffff0000081031d8>] kthread+0x110/0x140 - [<ffff000008082d90>] ret_from_fork+0x10/0x40 - OF: ERROR: Bad of_node_put() on /smsm - CPU: 0 PID: 33 Comm: kworker/0:1 Tainted: G W E 4.12.0-rc5+ #1455 - Hardware name: qualcomm dragonboard410c/dragonboard410c, BIOS 2017.07-rc1-00234-g22fa70a-dirty 06/26/2017 - Workqueue: events deferred_probe_work_func - -Signed-off-by: Rob Clark <robdclark@gmail.com> ---- - drivers/soc/qcom/smsm.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c -index d0337b2a71c8..a64ecd597a22 100644 ---- a/drivers/soc/qcom/smsm.c -+++ b/drivers/soc/qcom/smsm.c -@@ -495,7 +495,8 @@ static int qcom_smsm_probe(struct platform_device *pdev) - if (!smsm->hosts) - return -ENOMEM; - -- local_node = of_find_node_with_property(pdev->dev.of_node, "#qcom,smem-state-cells"); -+ local_node = of_find_node_with_property(of_node_get(pdev->dev.of_node), -+ "#qcom,smem-state-cells"); - if (!local_node) { - dev_err(&pdev->dev, "no state entry\n"); - return -EINVAL; --- -2.13.0 - From 40cb129048e5d2456da8d9d6468f292da3071b91 Mon Sep 17 00:00:00 2001 From: Rob Clark <robdclark@gmail.com> Date: Fri, 30 Jun 2017 16:40:23 -0400 @@ -107,32 +29,3 @@ index b1449ad67fc0..22ad37c9808c 100644 -- 2.13.0 - -From ae9b4fa55748cc9ce3c8ac039e46feab7257eff9 Mon Sep 17 00:00:00 2001 -From: Rob Clark <robdclark@gmail.com> -Date: Sun, 2 Jul 2017 09:23:36 -0400 -Subject: [PATCH 5/6] soc: qcom: wcnss_ctrl: add missing MODULE_DEVICE_TABLE() - -This fixes a problem of wifi module not loading on db410c. - -Signed-off-by: Rob Clark <robdclark@gmail.com> -Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> ---- - drivers/soc/qcom/wcnss_ctrl.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/soc/qcom/wcnss_ctrl.c b/drivers/soc/qcom/wcnss_ctrl.c -index b9069184df19..d008e5b82db4 100644 ---- a/drivers/soc/qcom/wcnss_ctrl.c -+++ b/drivers/soc/qcom/wcnss_ctrl.c -@@ -347,6 +347,7 @@ static const struct of_device_id wcnss_ctrl_of_match[] = { - { .compatible = "qcom,wcnss", }, - {} - }; -+MODULE_DEVICE_TABLE(of, wcnss_ctrl_of_match); - - static struct rpmsg_driver wcnss_ctrl_driver = { - .probe = wcnss_ctrl_probe, --- -2.13.0 - @@ -1,3 +1,3 @@ SHA512 (linux-4.13.tar.xz) = a557c2f0303ae618910b7106ff63d9978afddf470f03cb72aa748213e099a0ecd5f3119aea6cbd7b61df30ca6ef3ec57044d524b7babbaabddf8b08b8bafa7d2 SHA512 (perf-man-4.13.tar.gz) = 9bcc2cd8e56ec583ed2d8e0b0c88e7a94035a1915e40b3177bb02d6c0f10ddd4df9b097b1f5af59efc624226b613e240ddba8ddc2156f3682f992d5455fc5c03 -SHA512 (patch-4.13-git3.xz) = ca51994da2a499037f331d554450ace9409c62ac799f1296775ec2466d22660927b9299a65657e8843ee452626cc7da85c691570308c10e847a5a6632ad30a99 +SHA512 (patch-4.13-git4.xz) = 7047893f6d929a03c0ed7c40286c349442d4ec3039876d90750e3f27e4b29413869cb379b8b6e4ec98dc4e41258fdea231c0650fa24a632a715507e979e141cb |