Fixes for Tegra Jetson TX1/TX2 series via max77620

3 files changed, 776 insertions, 0 deletions

diff --git a/gpio-max77620-Use-correct-unit-for-debounce-times.patch b/gpio-max77620-Use-correct-unit-for-debounce-times.patch
new file mode 100644
index 000000000..bcf575fb8
--- /dev/null
+++ b/gpio-max77620-Use-correct-unit-for-debounce-times.patch
@@ -0,0 +1,586 @@
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+ Wed, 02 Oct 2019 05:28:26 -0700 (PDT)
+From: Thierry Reding <thierry.reding@gmail.com>
+To: Linus Walleij <linus.walleij@linaro.org>,
+ Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Cc: Timo Alho <talho@nvidia.com>, linux-gpio@vger.kernel.org,
+ linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH 1/3] gpio: max77620: Use correct unit for debounce times
+Date: Wed,  2 Oct 2019 14:28:23 +0200
+Message-Id: <20191002122825.3948322-1-thierry.reding@gmail.com>
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+From: Thierry Reding <treding@nvidia.com>
+
+The gpiod_set_debounce() function takes the debounce time in
+microseconds. Adjust the switch/case values in the MAX77620 GPIO to use
+the correct unit.
+
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+---
+ drivers/gpio/gpio-max77620.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
+index 47d05e357e61..faf86ea9c51a 100644
+--- a/drivers/gpio/gpio-max77620.c
++++ b/drivers/gpio/gpio-max77620.c
+@@ -192,13 +192,13 @@ static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio,
+ 	case 0:
+ 		val = MAX77620_CNFG_GPIO_DBNC_None;
+ 		break;
+-	case 1 ... 8:
++	case 1000 ... 8000:
+ 		val = MAX77620_CNFG_GPIO_DBNC_8ms;
+ 		break;
+-	case 9 ... 16:
++	case 9000 ... 16000:
+ 		val = MAX77620_CNFG_GPIO_DBNC_16ms;
+ 		break;
+-	case 17 ... 32:
++	case 17000 ... 32000:
+ 		val = MAX77620_CNFG_GPIO_DBNC_32ms;
+ 		break;
+ 	default:
+
+From patchwork Wed Oct  2 12:28:24 2019
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+From: Thierry Reding <thierry.reding@gmail.com>
+To: Linus Walleij <linus.walleij@linaro.org>,
+ Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Cc: Timo Alho <talho@nvidia.com>, linux-gpio@vger.kernel.org,
+ linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH 2/3] gpio: max77620: Do not allocate IRQs upfront
+Date: Wed,  2 Oct 2019 14:28:24 +0200
+Message-Id: <20191002122825.3948322-2-thierry.reding@gmail.com>
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+From: Thierry Reding <treding@nvidia.com>
+
+regmap_add_irq_chip() will try to allocate all of the IRQ descriptors
+upfront if passed a non-zero irq_base parameter. However, the intention
+is to allocate IRQ descriptors on an as-needed basis if possible. Pass 0
+instead of -1 to fix that use-case.
+
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+---
+ drivers/gpio/gpio-max77620.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
+index faf86ea9c51a..c58b56e5291e 100644
+--- a/drivers/gpio/gpio-max77620.c
++++ b/drivers/gpio/gpio-max77620.c
+@@ -304,7 +304,7 @@ static int max77620_gpio_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	ret = devm_regmap_add_irq_chip(&pdev->dev, chip->rmap, gpio_irq,
+-				       IRQF_ONESHOT, -1,
++				       IRQF_ONESHOT, 0,
+ 				       &max77620_gpio_irq_chip,
+ 				       &chip->gpio_irq_data);
+ 	if (ret < 0) {
+
+From patchwork Wed Oct  2 12:28:25 2019
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+ Wed, 02 Oct 2019 05:28:30 -0700 (PDT)
+From: Thierry Reding <thierry.reding@gmail.com>
+To: Linus Walleij <linus.walleij@linaro.org>,
+ Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Cc: Timo Alho <talho@nvidia.com>, linux-gpio@vger.kernel.org,
+ linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH 3/3] gpio: max77620: Fix interrupt handling
+Date: Wed,  2 Oct 2019 14:28:25 +0200
+Message-Id: <20191002122825.3948322-3-thierry.reding@gmail.com>
+X-Mailer: git-send-email 2.23.0
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+
+From: Timo Alho <talho@nvidia.com>
+
+The interrupt-related register fields on the MAX77620 GPIO controller
+share registers with GPIO related fields. If the IRQ chip is implemented
+with regmap-irq, this causes the IRQ controller code to overwrite fields
+previously configured by the GPIO controller code.
+
+Two examples where this causes problems are the NVIDIA Jetson TX1 and
+Jetson TX2 boards, where some of the GPIOs are used to enable vital
+power regulators. The MAX77620 GPIO controller also provides the USB OTG
+ID pin. If configured as an interrupt, this causes some of the
+regulators to be powered off.
+
+Signed-off-by: Timo Alho <talho@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+---
+ drivers/gpio/gpio-max77620.c | 231 ++++++++++++++++++-----------------
+ 1 file changed, 117 insertions(+), 114 deletions(-)
+
+diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
+index c58b56e5291e..c5b64a4ac172 100644
+--- a/drivers/gpio/gpio-max77620.c
++++ b/drivers/gpio/gpio-max77620.c
+@@ -18,109 +18,115 @@ struct max77620_gpio {
+ 	struct gpio_chip	gpio_chip;
+ 	struct regmap		*rmap;
+ 	struct device		*dev;
++	struct mutex		buslock; /* irq_bus_lock */
++	unsigned int		irq_type[8];
++	bool			irq_enabled[8];
+ };
+ 
+-static const struct regmap_irq max77620_gpio_irqs[] = {
+-	[0] = {
+-		.reg_offset = 0,
+-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
+-		.type = {
+-			.type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
+-			.type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
+-			.type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
+-			.type_reg_offset = 0,
+-			.types_supported = IRQ_TYPE_EDGE_BOTH,
+-		},
+-	},
+-	[1] = {
+-		.reg_offset = 0,
+-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
+-		.type = {
+-			.type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
+-			.type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
+-			.type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
+-			.type_reg_offset = 1,
+-			.types_supported = IRQ_TYPE_EDGE_BOTH,
+-		},
+-	},
+-	[2] = {
+-		.reg_offset = 0,
+-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
+-		.type = {
+-			.type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
+-			.type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
+-			.type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
+-			.type_reg_offset = 2,
+-			.types_supported = IRQ_TYPE_EDGE_BOTH,
+-		},
+-	},
+-	[3] = {
+-		.reg_offset = 0,
+-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
+-		.type = {
+-			.type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
+-			.type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
+-			.type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
+-			.type_reg_offset = 3,
+-			.types_supported = IRQ_TYPE_EDGE_BOTH,
+-		},
+-	},
+-	[4] = {
+-		.reg_offset = 0,
+-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
+-		.type = {
+-			.type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
+-			.type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
+-			.type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
+-			.type_reg_offset = 4,
+-			.types_supported = IRQ_TYPE_EDGE_BOTH,
+-		},
+-	},
+-	[5] = {
+-		.reg_offset = 0,
+-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
+-		.type = {
+-			.type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
+-			.type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
+-			.type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
+-			.type_reg_offset = 5,
+-			.types_supported = IRQ_TYPE_EDGE_BOTH,
+-		},
+-	},
+-	[6] = {
+-		.reg_offset = 0,
+-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
+-		.type = {
+-			.type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
+-			.type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
+-			.type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
+-			.type_reg_offset = 6,
+-			.types_supported = IRQ_TYPE_EDGE_BOTH,
+-		},
+-	},
+-	[7] = {
+-		.reg_offset = 0,
+-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
+-		.type = {
+-			.type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
+-			.type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
+-			.type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
+-			.type_reg_offset = 7,
+-			.types_supported = IRQ_TYPE_EDGE_BOTH,
+-		},
+-	},
+-};
++static irqreturn_t max77620_gpio_irqhandler(int irq, void *data)
++{
++	struct max77620_gpio *gpio = data;
++	unsigned int value, offset;
++	unsigned long pending;
++	int err;
++
++	err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value);
++	if (err < 0) {
++		dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err);
++		return IRQ_NONE;
++	}
++
++	pending = value;
++
++	for_each_set_bit(offset, &pending, 8) {
++		unsigned int virq;
++
++		virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset);
++		handle_nested_irq(virq);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static void max77620_gpio_irq_mask(struct irq_data *data)
++{
++	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
++	struct max77620_gpio *gpio = gpiochip_get_data(chip);
++
++	gpio->irq_enabled[data->hwirq] = false;
++}
+ 
+-static const struct regmap_irq_chip max77620_gpio_irq_chip = {
+-	.name = "max77620-gpio",
+-	.irqs = max77620_gpio_irqs,
+-	.num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
+-	.num_regs = 1,
+-	.num_type_reg = 8,
+-	.irq_reg_stride = 1,
+-	.type_reg_stride = 1,
+-	.status_base = MAX77620_REG_IRQ_LVL2_GPIO,
+-	.type_base = MAX77620_REG_GPIO0,
++static void max77620_gpio_irq_unmask(struct irq_data *data)
++{
++	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
++	struct max77620_gpio *gpio = gpiochip_get_data(chip);
++
++	gpio->irq_enabled[data->hwirq] = true;
++}
++
++static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type)
++{
++	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
++	struct max77620_gpio *gpio = gpiochip_get_data(chip);
++	unsigned int irq_type;
++
++	switch (type) {
++	case IRQ_TYPE_EDGE_RISING:
++		irq_type = MAX77620_CNFG_GPIO_INT_RISING;
++		break;
++
++	case IRQ_TYPE_EDGE_FALLING:
++		irq_type = MAX77620_CNFG_GPIO_INT_FALLING;
++		break;
++
++	case IRQ_TYPE_EDGE_BOTH:
++		irq_type = MAX77620_CNFG_GPIO_INT_RISING |
++			   MAX77620_CNFG_GPIO_INT_FALLING;
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	gpio->irq_type[data->hwirq] = irq_type;
++
++	return 0;
++}
++
++static void max77620_gpio_bus_lock(struct irq_data *data)
++{
++	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
++	struct max77620_gpio *gpio = gpiochip_get_data(chip);
++
++	mutex_lock(&gpio->buslock);
++}
++
++static void max77620_gpio_bus_sync_unlock(struct irq_data *data)
++{
++	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
++	struct max77620_gpio *gpio = gpiochip_get_data(chip);
++	unsigned int value, offset = data->hwirq;
++	int err;
++
++	value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0;
++
++	err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset),
++				 MAX77620_CNFG_GPIO_INT_MASK, value);
++	if (err < 0)
++		dev_err(chip->parent, "failed to update interrupt mask: %d\n",
++			err);
++
++	mutex_unlock(&gpio->buslock);
++}
++
++static struct irq_chip max77620_gpio_irqchip = {
++	.name		= "max77620-gpio",
++	.irq_mask	= max77620_gpio_irq_mask,
++	.irq_unmask	= max77620_gpio_irq_unmask,
++	.irq_set_type	= max77620_gpio_set_irq_type,
++	.irq_bus_lock	= max77620_gpio_bus_lock,
++	.irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock,
++	.flags		= IRQCHIP_MASK_ON_SUSPEND,
+ };
+ 
+ static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
+@@ -254,14 +260,6 @@ static int max77620_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
+ 	return -ENOTSUPP;
+ }
+ 
+-static int max77620_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
+-{
+-	struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+-	struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
+-
+-	return regmap_irq_get_virq(chip->gpio_irq_data, offset);
+-}
+-
+ static int max77620_gpio_probe(struct platform_device *pdev)
+ {
+ 	struct max77620_chip *chip =  dev_get_drvdata(pdev->dev.parent);
+@@ -287,7 +285,6 @@ static int max77620_gpio_probe(struct platform_device *pdev)
+ 	mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
+ 	mgpio->gpio_chip.set = max77620_gpio_set;
+ 	mgpio->gpio_chip.set_config = max77620_gpio_set_config;
+-	mgpio->gpio_chip.to_irq = max77620_gpio_to_irq;
+ 	mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
+ 	mgpio->gpio_chip.can_sleep = 1;
+ 	mgpio->gpio_chip.base = -1;
+@@ -303,15 +300,21 @@ static int max77620_gpio_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
+-	ret = devm_regmap_add_irq_chip(&pdev->dev, chip->rmap, gpio_irq,
+-				       IRQF_ONESHOT, 0,
+-				       &max77620_gpio_irq_chip,
+-				       &chip->gpio_irq_data);
++	mutex_init(&mgpio->buslock);
++
++	gpiochip_irqchip_add_nested(&mgpio->gpio_chip, &max77620_gpio_irqchip,
++				    0, handle_edge_irq, IRQ_TYPE_NONE);
++
++	ret = request_threaded_irq(gpio_irq, NULL, max77620_gpio_irqhandler,
++				   IRQF_ONESHOT, "max77620-gpio", mgpio);
+ 	if (ret < 0) {
+-		dev_err(&pdev->dev, "Failed to add gpio irq_chip %d\n", ret);
++		dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
+ 		return ret;
+ 	}
+ 
++	gpiochip_set_nested_irqchip(&mgpio->gpio_chip, &max77620_gpio_irqchip,
++				    gpio_irq);
++
+ 	return 0;
+ }
+ 
diff --git a/kernel.spec b/kernel.spec
index bb0be106a..5ce145554 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -538,6 +538,10 @@ Patch308: arm64-dts-rockchip-fix-Rockpro64-RK808-interrupt-line.patch
 Patch320: arm64-tegra-jetson-tx1-fixes.patch
 # https://www.spinics.net/lists/linux-tegra/msg43110.html
 Patch321: arm64-tegra-Jetson-TX2-Allow-bootloader-to-configure.patch
+# https://patchwork.kernel.org/patch/11171225/
+Patch322: mfd-max77620-Do-not-allocate-IRQs-upfront.patch
+# https://patchwork.ozlabs.org/patch/1170631/
+Patch323: gpio-max77620-Use-correct-unit-for-debounce-times.patch
 
 # 400 - IBM (ppc/s390x) patches
 
@@ -1757,6 +1761,9 @@ fi
 #
 #
 %changelog
+* Sun Oct  6 2019 Peter Robinson <pbrobinson@fedoraproject.org>
+- Fixes for Jetson TX1/TX2 series of devices
+
 * Fri Oct 04 2019 Jeremy Cline <jcline@redhat.com> - 5.4.0-0.rc1.git1.1
 - Linux v5.4-rc1-14-gcc3a7bfe62b9
 
diff --git a/mfd-max77620-Do-not-allocate-IRQs-upfront.patch b/mfd-max77620-Do-not-allocate-IRQs-upfront.patch
new file mode 100644
index 000000000..0b4820ad7
--- /dev/null
+++ b/mfd-max77620-Do-not-allocate-IRQs-upfront.patch
@@ -0,0 +1,183 @@
+From patchwork Wed Oct  2 14:43:18 2019
+Content-Type: text/plain; charset="utf-8"
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+Subject: [PATCH] mfd: max77620: Do not allocate IRQs upfront
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+
+From: Thierry Reding <treding@nvidia.com>
+
+regmap_add_irq_chip() will try to allocate all of the IRQ descriptors
+upfront if passed a non-zero irq_base parameter. However, the intention
+is to allocate IRQ descriptors on an as-needed basis if possible. Pass 0
+instead of -1 to fix that use-case.
+
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+---
+ drivers/mfd/max77620.c       | 5 ++---
+ include/linux/mfd/max77620.h | 1 -
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
+index a851ff473a44..c7ed5c353553 100644
+--- a/drivers/mfd/max77620.c
++++ b/drivers/mfd/max77620.c
+@@ -507,7 +507,6 @@ static int max77620_probe(struct i2c_client *client,
+ 
+ 	i2c_set_clientdata(client, chip);
+ 	chip->dev = &client->dev;
+-	chip->irq_base = -1;
+ 	chip->chip_irq = client->irq;
+ 	chip->chip_id = (enum max77620_chip_id)id->driver_data;
+ 
+@@ -545,8 +544,8 @@ static int max77620_probe(struct i2c_client *client,
+ 
+ 	max77620_top_irq_chip.irq_drv_data = chip;
+ 	ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
+-				       IRQF_ONESHOT | IRQF_SHARED,
+-				       chip->irq_base, &max77620_top_irq_chip,
++				       IRQF_ONESHOT | IRQF_SHARED, 0,
++				       &max77620_top_irq_chip,
+ 				       &chip->top_irq_data);
+ 	if (ret < 0) {
+ 		dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
+diff --git a/include/linux/mfd/max77620.h b/include/linux/mfd/max77620.h
+index 12ba157cb83f..f552ef5b1100 100644
+--- a/include/linux/mfd/max77620.h
++++ b/include/linux/mfd/max77620.h
+@@ -329,7 +329,6 @@ struct max77620_chip {
+ 	struct regmap *rmap;
+ 
+ 	int chip_irq;
+-	int irq_base;
+ 
+ 	/* chip id */
+ 	enum max77620_chip_id chip_id;