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authorPeter Robinson <pbrobinson@gmail.com>2018-08-11 09:00:07 +0100
committerPeter Robinson <pbrobinson@gmail.com>2018-08-11 09:00:07 +0100
commitdbed74a4b8ee13718008fb4266b9d8b5339ba2fd (patch)
treed07cd2b372ae4779214c90cf5ad52c4918ec094f
parentd187f6fb2c01c8c69fbcb6da33c572a2e407bb6c (diff)
downloadkernel-dbed74a4b8ee13718008fb4266b9d8b5339ba2fd.tar.gz
kernel-dbed74a4b8ee13718008fb4266b9d8b5339ba2fd.tar.xz
kernel-dbed74a4b8ee13718008fb4266b9d8b5339ba2fd.zip
Add ZYNQMP clock and firmware driver
-rw-r--r--arm64-ZynqMP-firmware-clock-drivers-core.patch5481
-rw-r--r--kernel-aarch64-debug.config3
-rw-r--r--kernel-aarch64.config3
-rw-r--r--kernel-armv7hl-debug.config1
-rw-r--r--kernel-armv7hl-lpae-debug.config1
-rw-r--r--kernel-armv7hl-lpae.config1
-rw-r--r--kernel-armv7hl.config1
-rw-r--r--kernel-i686-PAE.config1
-rw-r--r--kernel-i686-PAEdebug.config1
-rw-r--r--kernel-i686-debug.config1
-rw-r--r--kernel-i686.config1
-rw-r--r--kernel-ppc64-debug.config1
-rw-r--r--kernel-ppc64.config1
-rw-r--r--kernel-ppc64le-debug.config1
-rw-r--r--kernel-ppc64le.config1
-rw-r--r--kernel-s390x-debug.config1
-rw-r--r--kernel-s390x.config1
-rw-r--r--kernel-x86_64-debug.config1
-rw-r--r--kernel-x86_64.config1
-rw-r--r--kernel.spec6
20 files changed, 5509 insertions, 0 deletions
diff --git a/arm64-ZynqMP-firmware-clock-drivers-core.patch b/arm64-ZynqMP-firmware-clock-drivers-core.patch
new file mode 100644
index 000000000..f8824e505
--- /dev/null
+++ b/arm64-ZynqMP-firmware-clock-drivers-core.patch
@@ -0,0 +1,5481 @@
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+From: Jolly Shah <jolly.shah@xilinx.com>
+To: <ard.biesheuvel@linaro.org>, <mingo@kernel.org>,
+ <gregkh@linuxfoundation.org>, <matt@codeblueprint.co.uk>,
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+Subject: [PATCH v11 01/11] dt-bindings: firmware: Add bindings for ZynqMP
+ firmware
+Date: Fri, 3 Aug 2018 10:53:18 -0700
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+From: Rajan Vaja <rajanv@xilinx.com>
+
+Add documentation to describe Xilinx ZynqMP firmware driver
+bindings. Firmware driver provides an interface to firmware
+APIs. Interface APIs can be used by any driver to communicate
+to PMUFW (Platform Management Unit).
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+---
+ .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 29 ++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+
+diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+new file mode 100644
+index 0000000..1b431d9
+--- /dev/null
++++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+@@ -0,0 +1,29 @@
++-----------------------------------------------------------------
++Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
++-----------------------------------------------------------------
++
++The zynqmp-firmware node describes the interface to platform firmware.
++ZynqMP has an interface to communicate with secure firmware. Firmware
++driver provides an interface to firmware APIs. Interface APIs can be
++used by any driver to communicate to PMUFW(Platform Management Unit).
++These requests include clock management, pin control, device control,
++power management service, FPGA service and other platform management
++services.
++
++Required properties:
++ - compatible: Must contain: "xlnx,zynqmp-firmware"
++ - method: The method of calling the PM-API firmware layer.
++ Permitted values are:
++ - "smc" : SMC #0, following the SMCCC
++ - "hvc" : HVC #0, following the SMCCC
++
++-------
++Example
++-------
++
++firmware {
++ zynqmp_firmware: zynqmp-firmware {
++ compatible = "xlnx,zynqmp-firmware";
++ method = "smc";
++ };
++};
+
+From patchwork Fri Aug 3 17:53:19 2018
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+X-Patchwork-Id: 10555401
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+From: Jolly Shah <jolly.shah@xilinx.com>
+To: <ard.biesheuvel@linaro.org>, <mingo@kernel.org>,
+ <gregkh@linuxfoundation.org>, <matt@codeblueprint.co.uk>,
+ <sudeep.holla@arm.com>, <hkallweit1@gmail.com>, <keescook@chromium.org>,
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+Subject: [PATCH v11 02/11] firmware: xilinx: Add Zynqmp firmware driver
+Date: Fri, 3 Aug 2018 10:53:19 -0700
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+Cc: devicetree@vger.kernel.org, rajanv@xilinx.com,
+ linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, Jolly Shah <jollys@xilinx.com>
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+From: Rajan Vaja <rajanv@xilinx.com>
+
+This patch is adding communication layer with firmware.
+Firmware driver provides an interface to firmware APIs.
+Interface APIs can be used by any driver to communicate to
+PMUFW(Platform Management Unit). All requests go through ATF.
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+---
+ arch/arm64/Kconfig.platforms | 1 +
+ drivers/firmware/Kconfig | 1 +
+ drivers/firmware/Makefile | 1 +
+ drivers/firmware/xilinx/Kconfig | 16 ++
+ drivers/firmware/xilinx/Makefile | 4 +
+ drivers/firmware/xilinx/zynqmp.c | 337 +++++++++++++++++++++++++++++++++++
+ include/linux/firmware/xlnx-zynqmp.h | 63 +++++++
+ 7 files changed, 423 insertions(+)
+ create mode 100644 drivers/firmware/xilinx/Kconfig
+ create mode 100644 drivers/firmware/xilinx/Makefile
+ create mode 100644 drivers/firmware/xilinx/zynqmp.c
+ create mode 100644 include/linux/firmware/xlnx-zynqmp.h
+
+diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
+index fbedbd8..6454458 100644
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -274,6 +274,7 @@ config ARCH_ZX
+
+ config ARCH_ZYNQMP
+ bool "Xilinx ZynqMP Family"
++ select ZYNQMP_FIRMWARE
+ help
+ This enables support for Xilinx ZynqMP Family
+
+diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
+index b7c7482..f41eb0d 100644
+--- a/drivers/firmware/Kconfig
++++ b/drivers/firmware/Kconfig
+@@ -257,5 +257,6 @@ source "drivers/firmware/google/Kconfig"
+ source "drivers/firmware/efi/Kconfig"
+ source "drivers/firmware/meson/Kconfig"
+ source "drivers/firmware/tegra/Kconfig"
++source "drivers/firmware/xilinx/Kconfig"
+
+ endmenu
+diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
+index b248238..f90363e 100644
+--- a/drivers/firmware/Makefile
++++ b/drivers/firmware/Makefile
+@@ -31,3 +31,4 @@ obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
+ obj-$(CONFIG_EFI) += efi/
+ obj-$(CONFIG_UEFI_CPER) += efi/
+ obj-y += tegra/
++obj-y += xilinx/
+diff --git a/drivers/firmware/xilinx/Kconfig b/drivers/firmware/xilinx/Kconfig
+new file mode 100644
+index 0000000..64d976e
+--- /dev/null
++++ b/drivers/firmware/xilinx/Kconfig
+@@ -0,0 +1,16 @@
++# SPDX-License-Identifier: GPL-2.0
++# Kconfig for Xilinx firmwares
++
++menu "Zynq MPSoC Firmware Drivers"
++ depends on ARCH_ZYNQMP
++
++config ZYNQMP_FIRMWARE
++ bool "Enable Xilinx Zynq MPSoC firmware interface"
++ help
++ Firmware interface driver is used by different
++ drivers to communicate with the firmware for
++ various platform management services.
++ Say yes to enable ZynqMP firmware interface driver.
++ If in doubt, say N.
++
++endmenu
+diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile
+new file mode 100644
+index 0000000..29f7bf2
+--- /dev/null
++++ b/drivers/firmware/xilinx/Makefile
+@@ -0,0 +1,4 @@
++# SPDX-License-Identifier: GPL-2.0
++# Makefile for Xilinx firmwares
++
++obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o
+diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
+new file mode 100644
+index 0000000..edbb84e
+--- /dev/null
++++ b/drivers/firmware/xilinx/zynqmp.c
+@@ -0,0 +1,337 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Xilinx Zynq MPSoC Firmware layer
++ *
++ * Copyright (C) 2014-2018 Xilinx, Inc.
++ *
++ * Michal Simek <michal.simek@xilinx.com>
++ * Davorin Mista <davorin.mista@aggios.com>
++ * Jolly Shah <jollys@xilinx.com>
++ * Rajan Vaja <rajanv@xilinx.com>
++ */
++
++#include <linux/arm-smccc.h>
++#include <linux/compiler.h>
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/slab.h>
++#include <linux/uaccess.h>
++
++#include <linux/firmware/xlnx-zynqmp.h>
++
++/**
++ * zynqmp_pm_ret_code() - Convert PMU-FW error codes to Linux error codes
++ * @ret_status: PMUFW return code
++ *
++ * Return: corresponding Linux error code
++ */
++static int zynqmp_pm_ret_code(u32 ret_status)
++{
++ switch (ret_status) {
++ case XST_PM_SUCCESS:
++ case XST_PM_DOUBLE_REQ:
++ return 0;
++ case XST_PM_NO_ACCESS:
++ return -EACCES;
++ case XST_PM_ABORT_SUSPEND:
++ return -ECANCELED;
++ case XST_PM_INTERNAL:
++ case XST_PM_CONFLICT:
++ case XST_PM_INVALID_NODE:
++ default:
++ return -EINVAL;
++ }
++}
++
++static noinline int do_fw_call_fail(u64 arg0, u64 arg1, u64 arg2,
++ u32 *ret_payload)
++{
++ return -ENODEV;
++}
++
++/*
++ * PM function call wrapper
++ * Invoke do_fw_call_smc or do_fw_call_hvc, depending on the configuration
++ */
++static int (*do_fw_call)(u64, u64, u64, u32 *ret_payload) = do_fw_call_fail;
++
++/**
++ * do_fw_call_smc() - Call system-level platform management layer (SMC)
++ * @arg0: Argument 0 to SMC call
++ * @arg1: Argument 1 to SMC call
++ * @arg2: Argument 2 to SMC call
++ * @ret_payload: Returned value array
++ *
++ * Invoke platform management function via SMC call (no hypervisor present).
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static noinline int do_fw_call_smc(u64 arg0, u64 arg1, u64 arg2,
++ u32 *ret_payload)
++{
++ struct arm_smccc_res res;
++
++ arm_smccc_smc(arg0, arg1, arg2, 0, 0, 0, 0, 0, &res);
++
++ if (ret_payload) {
++ ret_payload[0] = lower_32_bits(res.a0);
++ ret_payload[1] = upper_32_bits(res.a0);
++ ret_payload[2] = lower_32_bits(res.a1);
++ ret_payload[3] = upper_32_bits(res.a1);
++ }
++
++ return zynqmp_pm_ret_code((enum pm_ret_status)res.a0);
++}
++
++/**
++ * do_fw_call_hvc() - Call system-level platform management layer (HVC)
++ * @arg0: Argument 0 to HVC call
++ * @arg1: Argument 1 to HVC call
++ * @arg2: Argument 2 to HVC call
++ * @ret_payload: Returned value array
++ *
++ * Invoke platform management function via HVC
++ * HVC-based for communication through hypervisor
++ * (no direct communication with ATF).
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static noinline int do_fw_call_hvc(u64 arg0, u64 arg1, u64 arg2,
++ u32 *ret_payload)
++{
++ struct arm_smccc_res res;
++
++ arm_smccc_hvc(arg0, arg1, arg2, 0, 0, 0, 0, 0, &res);
++
++ if (ret_payload) {
++ ret_payload[0] = lower_32_bits(res.a0);
++ ret_payload[1] = upper_32_bits(res.a0);
++ ret_payload[2] = lower_32_bits(res.a1);
++ ret_payload[3] = upper_32_bits(res.a1);
++ }
++
++ return zynqmp_pm_ret_code((enum pm_ret_status)res.a0);
++}
++
++/**
++ * zynqmp_pm_invoke_fn() - Invoke the system-level platform management layer
++ * caller function depending on the configuration
++ * @pm_api_id: Requested PM-API call
++ * @arg0: Argument 0 to requested PM-API call
++ * @arg1: Argument 1 to requested PM-API call
++ * @arg2: Argument 2 to requested PM-API call
++ * @arg3: Argument 3 to requested PM-API call
++ * @ret_payload: Returned value array
++ *
++ * Invoke platform management function for SMC or HVC call, depending on
++ * configuration.
++ * Following SMC Calling Convention (SMCCC) for SMC64:
++ * Pm Function Identifier,
++ * PM_SIP_SVC + PM_API_ID =
++ * ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT)
++ * ((SMC_64) << FUNCID_CC_SHIFT)
++ * ((SIP_START) << FUNCID_OEN_SHIFT)
++ * ((PM_API_ID) & FUNCID_NUM_MASK))
++ *
++ * PM_SIP_SVC - Registered ZynqMP SIP Service Call.
++ * PM_API_ID - Platform Management API ID.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
++ u32 arg2, u32 arg3, u32 *ret_payload)
++{
++ /*
++ * Added SIP service call Function Identifier
++ * Make sure to stay in x0 register
++ */
++ u64 smc_arg[4];
++
++ smc_arg[0] = PM_SIP_SVC | pm_api_id;
++ smc_arg[1] = ((u64)arg1 << 32) | arg0;
++ smc_arg[2] = ((u64)arg3 << 32) | arg2;
++
++ return do_fw_call(smc_arg[0], smc_arg[1], smc_arg[2], ret_payload);
++}
++
++static u32 pm_api_version;
++static u32 pm_tz_version;
++
++/**
++ * zynqmp_pm_get_api_version() - Get version number of PMU PM firmware
++ * @version: Returned version value
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_get_api_version(u32 *version)
++{
++ u32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ if (!version)
++ return -EINVAL;
++
++ /* Check is PM API version already verified */
++ if (pm_api_version > 0) {
++ *version = pm_api_version;
++ return 0;
++ }
++ ret = zynqmp_pm_invoke_fn(PM_GET_API_VERSION, 0, 0, 0, 0, ret_payload);
++ *version = ret_payload[1];
++
++ return ret;
++}
++
++/**
++ * zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version
++ * @version: Returned version value
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_get_trustzone_version(u32 *version)
++{
++ u32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ if (!version)
++ return -EINVAL;
++
++ /* Check is PM trustzone version already verified */
++ if (pm_tz_version > 0) {
++ *version = pm_tz_version;
++ return 0;
++ }
++ ret = zynqmp_pm_invoke_fn(PM_GET_TRUSTZONE_VERSION, 0, 0,
++ 0, 0, ret_payload);
++ *version = ret_payload[1];
++
++ return ret;
++}
++
++/**
++ * get_set_conduit_method() - Choose SMC or HVC based communication
++ * @np: Pointer to the device_node structure
++ *
++ * Use SMC or HVC-based functions to communicate with EL2/EL3.
++ *
++ * Return: Returns 0 on success or error code
++ */
++static int get_set_conduit_method(struct device_node *np)
++{
++ const char *method;
++
++ if (of_property_read_string(np, "method", &method)) {
++ pr_warn("%s missing \"method\" property\n", __func__);
++ return -ENXIO;
++ }
++
++ if (!strcmp("hvc", method)) {
++ do_fw_call = do_fw_call_hvc;
++ } else if (!strcmp("smc", method)) {
++ do_fw_call = do_fw_call_smc;
++ } else {
++ pr_warn("%s Invalid \"method\" property: %s\n",
++ __func__, method);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static const struct zynqmp_eemi_ops eemi_ops = {
++ .get_api_version = zynqmp_pm_get_api_version,
++};
++
++/**
++ * zynqmp_pm_get_eemi_ops - Get eemi ops functions
++ *
++ * Return: Pointer of eemi_ops structure
++ */
++const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
++{
++ return &eemi_ops;
++}
++EXPORT_SYMBOL_GPL(zynqmp_pm_get_eemi_ops);
++
++static int zynqmp_firmware_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++
++ return of_platform_populate(dev->of_node, NULL, NULL, dev);
++}
++
++static const struct of_device_id zynqmp_firmware_of_match[] = {
++ {.compatible = "xlnx,zynqmp-firmware"},
++ {},
++};
++MODULE_DEVICE_TABLE(of, zynqmp_firmware_of_match);
++
++static struct platform_driver zynqmp_firmware_driver = {
++ .driver = {
++ .name = "zynqmp_firmware",
++ .of_match_table = zynqmp_firmware_of_match,
++ },
++ .probe = zynqmp_firmware_probe,
++};
++module_platform_driver(zynqmp_firmware_driver);
++
++static int __init zynqmp_plat_init(void)
++{
++ int ret;
++ struct device_node *np;
++
++ np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp");
++ if (!np)
++ return 0;
++ of_node_put(np);
++
++ /*
++ * We're running on a ZynqMP machine,
++ * the zynqmp-firmware node is mandatory.
++ */
++ np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp-firmware");
++ if (!np) {
++ pr_warn("%s: zynqmp-firmware node not found\n", __func__);
++ return -ENXIO;
++ }
++
++ ret = get_set_conduit_method(np);
++ if (ret) {
++ of_node_put(np);
++ return ret;
++ }
++
++ /* Check PM API version number */
++ zynqmp_pm_get_api_version(&pm_api_version);
++ if (pm_api_version < ZYNQMP_PM_VERSION) {
++ panic("%s Platform Management API version error. Expected: v%d.%d - Found: v%d.%d\n",
++ __func__,
++ ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR,
++ pm_api_version >> 16, pm_api_version & 0xFFFF);
++ }
++
++ pr_info("%s Platform Management API v%d.%d\n", __func__,
++ pm_api_version >> 16, pm_api_version & 0xFFFF);
++
++ /* Check trustzone version number */
++ ret = zynqmp_pm_get_trustzone_version(&pm_tz_version);
++ if (ret)
++ panic("Legacy trustzone found without version support\n");
++
++ if (pm_tz_version < ZYNQMP_TZ_VERSION)
++ panic("%s Trustzone version error. Expected: v%d.%d - Found: v%d.%d\n",
++ __func__,
++ ZYNQMP_TZ_VERSION_MAJOR, ZYNQMP_TZ_VERSION_MINOR,
++ pm_tz_version >> 16, pm_tz_version & 0xFFFF);
++
++ pr_info("%s Trustzone version v%d.%d\n", __func__,
++ pm_tz_version >> 16, pm_tz_version & 0xFFFF);
++
++ of_node_put(np);
++
++ return ret;
++}
++early_initcall(zynqmp_plat_init);
+diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
+new file mode 100644
+index 0000000..cb63bed
+--- /dev/null
++++ b/include/linux/firmware/xlnx-zynqmp.h
+@@ -0,0 +1,63 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Xilinx Zynq MPSoC Firmware layer
++ *
++ * Copyright (C) 2014-2018 Xilinx
++ *
++ * Michal Simek <michal.simek@xilinx.com>
++ * Davorin Mista <davorin.mista@aggios.com>
++ * Jolly Shah <jollys@xilinx.com>
++ * Rajan Vaja <rajanv@xilinx.com>
++ */
++
++#ifndef __FIRMWARE_ZYNQMP_H__
++#define __FIRMWARE_ZYNQMP_H__
++
++#define ZYNQMP_PM_VERSION_MAJOR 1
++#define ZYNQMP_PM_VERSION_MINOR 0
++
++#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
++ ZYNQMP_PM_VERSION_MINOR)
++
++#define ZYNQMP_TZ_VERSION_MAJOR 1
++#define ZYNQMP_TZ_VERSION_MINOR 0
++
++#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
++ ZYNQMP_TZ_VERSION_MINOR)
++
++/* SMC SIP service Call Function Identifier Prefix */
++#define PM_SIP_SVC 0xC2000000
++#define PM_GET_TRUSTZONE_VERSION 0xa03
++
++/* Number of 32bits values in payload */
++#define PAYLOAD_ARG_CNT 4U
++
++enum pm_api_id {
++ PM_GET_API_VERSION = 1,
++};
++
++/* PMU-FW return status codes */
++enum pm_ret_status {
++ XST_PM_SUCCESS = 0,
++ XST_PM_INTERNAL = 2000,
++ XST_PM_CONFLICT,
++ XST_PM_NO_ACCESS,
++ XST_PM_INVALID_NODE,
++ XST_PM_DOUBLE_REQ,
++ XST_PM_ABORT_SUSPEND,
++};
++
++struct zynqmp_eemi_ops {
++ int (*get_api_version)(u32 *version);
++};
++
++#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
++const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
++#else
++static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
++{
++ return NULL;
++}
++#endif
++
++#endif /* __FIRMWARE_ZYNQMP_H__ */
+
+From patchwork Fri Aug 3 17:53:20 2018
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+ id 1fleGl-0007bh-9X; Fri, 03 Aug 2018 10:53:43 -0700
+From: Jolly Shah <jolly.shah@xilinx.com>
+To: <ard.biesheuvel@linaro.org>, <mingo@kernel.org>,
+ <gregkh@linuxfoundation.org>, <matt@codeblueprint.co.uk>,
+ <sudeep.holla@arm.com>, <hkallweit1@gmail.com>, <keescook@chromium.org>,
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+ <mark.rutland@arm.com>, <linux-clk@vger.kernel.org>
+Subject: [PATCH v11 03/11] firmware: xilinx: Add zynqmp IOCTL API for device
+ control
+Date: Fri, 3 Aug 2018 10:53:20 -0700
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+Cc: devicetree@vger.kernel.org, rajanv@xilinx.com,
+ linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, Jolly Shah <jollys@xilinx.com>
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+From: Rajan Vaja <rajanv@xilinx.com>
+
+Add ZynqMP firmware IOCTL API to control and configure
+devices like PLLs, SD, Gem, etc.
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+---
+ drivers/firmware/xilinx/zynqmp.c | 20 ++++++++++++++++++++
+ include/linux/firmware/xlnx-zynqmp.h | 2 ++
+ 2 files changed, 22 insertions(+)
+
+diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
+index edbb84e..24cfd9e 100644
+--- a/drivers/firmware/xilinx/zynqmp.c
++++ b/drivers/firmware/xilinx/zynqmp.c
+@@ -241,8 +241,28 @@ static int get_set_conduit_method(struct device_node *np)
+ return 0;
+ }
+
++/**
++ * zynqmp_pm_ioctl() - PM IOCTL API for device control and configs
++ * @node_id: Node ID of the device
++ * @ioctl_id: ID of the requested IOCTL
++ * @arg1: Argument 1 to requested IOCTL call
++ * @arg2: Argument 2 to requested IOCTL call
++ * @out: Returned output value
++ *
++ * This function calls IOCTL to firmware for device control and configuration.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2,
++ u32 *out)
++{
++ return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, ioctl_id,
++ arg1, arg2, out);
++}
++
+ static const struct zynqmp_eemi_ops eemi_ops = {
+ .get_api_version = zynqmp_pm_get_api_version,
++ .ioctl = zynqmp_pm_ioctl,
+ };
+
+ /**
+diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
+index cb63bed..2eec6e7 100644
+--- a/include/linux/firmware/xlnx-zynqmp.h
++++ b/include/linux/firmware/xlnx-zynqmp.h
+@@ -34,6 +34,7 @@
+
+ enum pm_api_id {
+ PM_GET_API_VERSION = 1,
++ PM_IOCTL = 34,
+ };
+
+ /* PMU-FW return status codes */
+@@ -49,6 +50,7 @@ enum pm_ret_status {
+
+ struct zynqmp_eemi_ops {
+ int (*get_api_version)(u32 *version);
++ int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
+ };
+
+ #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
+
+From patchwork Fri Aug 3 17:53:21 2018
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+From: Jolly Shah <jolly.shah@xilinx.com>
+To: <ard.biesheuvel@linaro.org>, <mingo@kernel.org>,
+ <gregkh@linuxfoundation.org>, <matt@codeblueprint.co.uk>,
+ <sudeep.holla@arm.com>, <hkallweit1@gmail.com>, <keescook@chromium.org>,
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+Subject: [PATCH v11 04/11] firmware: xilinx: Add query data API
+Date: Fri, 3 Aug 2018 10:53:21 -0700
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+From: Rajan Vaja <rajanv@xilinx.com>
+
+Add ZynqMP firmware query data API to query platform
+specific information(clocks, pins) from firmware.
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+---
+ drivers/firmware/xilinx/zynqmp.c | 14 ++++++++++++++
+ include/linux/firmware/xlnx-zynqmp.h | 20 ++++++++++++++++++++
+ 2 files changed, 34 insertions(+)
+
+diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
+index 24cfd9e..8ec5682 100644
+--- a/drivers/firmware/xilinx/zynqmp.c
++++ b/drivers/firmware/xilinx/zynqmp.c
+@@ -260,9 +260,23 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2,
+ arg1, arg2, out);
+ }
+
++/**
++ * zynqmp_pm_query_data() - Get query data from firmware
++ * @qdata: Variable to the zynqmp_pm_query_data structure
++ * @out: Returned output value
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out)
++{
++ return zynqmp_pm_invoke_fn(PM_QUERY_DATA, qdata.qid, qdata.arg1,
++ qdata.arg2, qdata.arg3, out);
++}
++
+ static const struct zynqmp_eemi_ops eemi_ops = {
+ .get_api_version = zynqmp_pm_get_api_version,
+ .ioctl = zynqmp_pm_ioctl,
++ .query_data = zynqmp_pm_query_data,
+ };
+
+ /**
+diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
+index 2eec6e7..55ed2ba 100644
+--- a/include/linux/firmware/xlnx-zynqmp.h
++++ b/include/linux/firmware/xlnx-zynqmp.h
+@@ -35,6 +35,7 @@
+ enum pm_api_id {
+ PM_GET_API_VERSION = 1,
+ PM_IOCTL = 34,
++ PM_QUERY_DATA,
+ };
+
+ /* PMU-FW return status codes */
+@@ -48,9 +49,28 @@ enum pm_ret_status {
+ XST_PM_ABORT_SUSPEND,
+ };
+
++enum pm_query_id {
++ PM_QID_INVALID,
++};
++
++/**
++ * struct zynqmp_pm_query_data - PM query data
++ * @qid: query ID
++ * @arg1: Argument 1 of query data
++ * @arg2: Argument 2 of query data
++ * @arg3: Argument 3 of query data
++ */
++struct zynqmp_pm_query_data {
++ u32 qid;
++ u32 arg1;
++ u32 arg2;
++ u32 arg3;
++};
++
+ struct zynqmp_eemi_ops {
+ int (*get_api_version)(u32 *version);
+ int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
++ int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
+ };
+
+ #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
+
+From patchwork Fri Aug 3 17:53:22 2018
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+From: Jolly Shah <jolly.shah@xilinx.com>
+To: <ard.biesheuvel@linaro.org>, <mingo@kernel.org>,
+ <gregkh@linuxfoundation.org>, <matt@codeblueprint.co.uk>,
+ <sudeep.holla@arm.com>, <hkallweit1@gmail.com>, <keescook@chromium.org>,
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+Subject: [PATCH v11 05/11] firmware: xilinx: Add clock APIs
+Date: Fri, 3 Aug 2018 10:53:22 -0700
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+From: Rajan Vaja <rajanv@xilinx.com>
+
+Add clock APIs to control clocks through firmware
+interface.
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+---
+ drivers/firmware/xilinx/zynqmp.c | 186 ++++++++++++++++++++++++++++++++++-
+ include/linux/firmware/xlnx-zynqmp.h | 30 ++++++
+ 2 files changed, 214 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
+index 8ec5682..41ed800 100644
+--- a/drivers/firmware/xilinx/zynqmp.c
++++ b/drivers/firmware/xilinx/zynqmp.c
+@@ -269,14 +269,196 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2,
+ */
+ static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out)
+ {
+- return zynqmp_pm_invoke_fn(PM_QUERY_DATA, qdata.qid, qdata.arg1,
+- qdata.arg2, qdata.arg3, out);
++ int ret;
++
++ ret = zynqmp_pm_invoke_fn(PM_QUERY_DATA, qdata.qid, qdata.arg1,
++ qdata.arg2, qdata.arg3, out);
++
++ /*
++ * For clock name query, all bytes in SMC response are clock name
++ * characters and return code is always success. For invalid clocks,
++ * clock name bytes would be zeros.
++ */
++ return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : ret;
++}
++
++/**
++ * zynqmp_pm_clock_enable() - Enable the clock for given id
++ * @clock_id: ID of the clock to be enabled
++ *
++ * This function is used by master to enable the clock
++ * including peripherals and PLL clocks.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_clock_enable(u32 clock_id)
++{
++ return zynqmp_pm_invoke_fn(PM_CLOCK_ENABLE, clock_id, 0, 0, 0, NULL);
++}
++
++/**
++ * zynqmp_pm_clock_disable() - Disable the clock for given id
++ * @clock_id: ID of the clock to be disable
++ *
++ * This function is used by master to disable the clock
++ * including peripherals and PLL clocks.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_clock_disable(u32 clock_id)
++{
++ return zynqmp_pm_invoke_fn(PM_CLOCK_DISABLE, clock_id, 0, 0, 0, NULL);
++}
++
++/**
++ * zynqmp_pm_clock_getstate() - Get the clock state for given id
++ * @clock_id: ID of the clock to be queried
++ * @state: 1/0 (Enabled/Disabled)
++ *
++ * This function is used by master to get the state of clock
++ * including peripherals and PLL clocks.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
++{
++ u32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETSTATE, clock_id, 0,
++ 0, 0, ret_payload);
++ *state = ret_payload[1];
++
++ return ret;
++}
++
++/**
++ * zynqmp_pm_clock_setdivider() - Set the clock divider for given id
++ * @clock_id: ID of the clock
++ * @divider: divider value
++ *
++ * This function is used by master to set divider for any clock
++ * to achieve desired rate.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
++{
++ return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, clock_id, divider,
++ 0, 0, NULL);
++}
++
++/**
++ * zynqmp_pm_clock_getdivider() - Get the clock divider for given id
++ * @clock_id: ID of the clock
++ * @divider: divider value
++ *
++ * This function is used by master to get divider values
++ * for any clock.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
++{
++ u32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETDIVIDER, clock_id, 0,
++ 0, 0, ret_payload);
++ *divider = ret_payload[1];
++
++ return ret;
++}
++
++/**
++ * zynqmp_pm_clock_setrate() - Set the clock rate for given id
++ * @clock_id: ID of the clock
++ * @rate: rate value in hz
++ *
++ * This function is used by master to set rate for any clock.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
++{
++ return zynqmp_pm_invoke_fn(PM_CLOCK_SETRATE, clock_id,
++ lower_32_bits(rate),
++ upper_32_bits(rate),
++ 0, NULL);
++}
++
++/**
++ * zynqmp_pm_clock_getrate() - Get the clock rate for given id
++ * @clock_id: ID of the clock
++ * @rate: rate value in hz
++ *
++ * This function is used by master to get rate
++ * for any clock.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
++{
++ u32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETRATE, clock_id, 0,
++ 0, 0, ret_payload);
++ *rate = ((u64)ret_payload[2] << 32) | ret_payload[1];
++
++ return ret;
++}
++
++/**
++ * zynqmp_pm_clock_setparent() - Set the clock parent for given id
++ * @clock_id: ID of the clock
++ * @parent_id: parent id
++ *
++ * This function is used by master to set parent for any clock.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
++{
++ return zynqmp_pm_invoke_fn(PM_CLOCK_SETPARENT, clock_id,
++ parent_id, 0, 0, NULL);
++}
++
++/**
++ * zynqmp_pm_clock_getparent() - Get the clock parent for given id
++ * @clock_id: ID of the clock
++ * @parent_id: parent id
++ *
++ * This function is used by master to get parent index
++ * for any clock.
++ *
++ * Return: Returns status, either success or error+reason
++ */
++static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
++{
++ u32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETPARENT, clock_id, 0,
++ 0, 0, ret_payload);
++ *parent_id = ret_payload[1];
++
++ return ret;
+ }
+
+ static const struct zynqmp_eemi_ops eemi_ops = {
+ .get_api_version = zynqmp_pm_get_api_version,
+ .ioctl = zynqmp_pm_ioctl,
+ .query_data = zynqmp_pm_query_data,
++ .clock_enable = zynqmp_pm_clock_enable,
++ .clock_disable = zynqmp_pm_clock_disable,
++ .clock_getstate = zynqmp_pm_clock_getstate,
++ .clock_setdivider = zynqmp_pm_clock_setdivider,
++ .clock_getdivider = zynqmp_pm_clock_getdivider,
++ .clock_setrate = zynqmp_pm_clock_setrate,
++ .clock_getrate = zynqmp_pm_clock_getrate,
++ .clock_setparent = zynqmp_pm_clock_setparent,
++ .clock_getparent = zynqmp_pm_clock_getparent,
+ };
+
+ /**
+diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
+index 55ed2ba..58a7478 100644
+--- a/include/linux/firmware/xlnx-zynqmp.h
++++ b/include/linux/firmware/xlnx-zynqmp.h
+@@ -36,6 +36,15 @@ enum pm_api_id {
+ PM_GET_API_VERSION = 1,
+ PM_IOCTL = 34,
+ PM_QUERY_DATA,
++ PM_CLOCK_ENABLE,
++ PM_CLOCK_DISABLE,
++ PM_CLOCK_GETSTATE,
++ PM_CLOCK_SETDIVIDER,
++ PM_CLOCK_GETDIVIDER,
++ PM_CLOCK_SETRATE,
++ PM_CLOCK_GETRATE,
++ PM_CLOCK_SETPARENT,
++ PM_CLOCK_GETPARENT,
+ };
+
+ /* PMU-FW return status codes */
+@@ -49,8 +58,20 @@ enum pm_ret_status {
+ XST_PM_ABORT_SUSPEND,
+ };
+
++enum pm_ioctl_id {
++ IOCTL_SET_PLL_FRAC_MODE = 8,
++ IOCTL_GET_PLL_FRAC_MODE,
++ IOCTL_SET_PLL_FRAC_DATA,
++ IOCTL_GET_PLL_FRAC_DATA,
++};
++
+ enum pm_query_id {
+ PM_QID_INVALID,
++ PM_QID_CLOCK_GET_NAME,
++ PM_QID_CLOCK_GET_TOPOLOGY,
++ PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
++ PM_QID_CLOCK_GET_PARENTS,
++ PM_QID_CLOCK_GET_ATTRIBUTES,
+ };
+
+ /**
+@@ -71,6 +92,15 @@ struct zynqmp_eemi_ops {
+ int (*get_api_version)(u32 *version);
+ int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
+ int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
++ int (*clock_enable)(u32 clock_id);
++ int (*clock_disable)(u32 clock_id);
++ int (*clock_getstate)(u32 clock_id, u32 *state);
++ int (*clock_setdivider)(u32 clock_id, u32 divider);
++ int (*clock_getdivider)(u32 clock_id, u32 *divider);
++ int (*clock_setrate)(u32 clock_id, u64 rate);
++ int (*clock_getrate)(u32 clock_id, u64 *rate);
++ int (*clock_setparent)(u32 clock_id, u32 parent_id);
++ int (*clock_getparent)(u32 clock_id, u32 *parent_id);
+ };
+
+ #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
+
+From patchwork Fri Aug 3 17:53:23 2018
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+Subject: [PATCH v11 06/11] firmware: xilinx: Add debugfs interface
+Date: Fri, 3 Aug 2018 10:53:23 -0700
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+Cc: devicetree@vger.kernel.org, rajanv@xilinx.com,
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+From: Rajan Vaja <rajanv@xilinx.com>
+
+Firmware-debug provides debugfs interface to all APIs.
+Debugfs can be used to call firmware APIs with required
+parameters.
+
+Usage:
+* Calling firmware API through debugfs:
+ # echo "<api-name> <arg1> .. <argn>" > /sys/.../zynqmp-firmware/pm
+
+* Read output of last called firmware API:
+ # cat /sys/.../zynqmp-firmware/pm
+
+Refer ug1200 for more information on these APIs:
+ * https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf
+
+Add basic debugfs file to get API version.
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+---
+ drivers/firmware/xilinx/Kconfig | 7 ++
+ drivers/firmware/xilinx/Makefile | 1 +
+ drivers/firmware/xilinx/zynqmp-debug.c | 212 +++++++++++++++++++++++++++++++++
+ drivers/firmware/xilinx/zynqmp-debug.h | 22 ++++
+ drivers/firmware/xilinx/zynqmp.c | 9 ++
+ 5 files changed, 251 insertions(+)
+ create mode 100644 drivers/firmware/xilinx/zynqmp-debug.c
+ create mode 100644 drivers/firmware/xilinx/zynqmp-debug.h
+
+diff --git a/drivers/firmware/xilinx/Kconfig b/drivers/firmware/xilinx/Kconfig
+index 64d976e..8f44b9c 100644
+--- a/drivers/firmware/xilinx/Kconfig
++++ b/drivers/firmware/xilinx/Kconfig
+@@ -13,4 +13,11 @@ config ZYNQMP_FIRMWARE
+ Say yes to enable ZynqMP firmware interface driver.
+ If in doubt, say N.
+
++config ZYNQMP_FIRMWARE_DEBUG
++ bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
++ depends on ZYNQMP_FIRMWARE && DEBUG_FS
++ help
++ Say yes to enable ZynqMP firmware interface debug APIs.
++ If in doubt, say N.
++
+ endmenu
+diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile
+index 29f7bf2..875a537 100644
+--- a/drivers/firmware/xilinx/Makefile
++++ b/drivers/firmware/xilinx/Makefile
+@@ -2,3 +2,4 @@
+ # Makefile for Xilinx firmwares
+
+ obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o
++obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) += zynqmp-debug.o
+diff --git a/drivers/firmware/xilinx/zynqmp-debug.c b/drivers/firmware/xilinx/zynqmp-debug.c
+new file mode 100644
+index 0000000..fcbdd6e
+--- /dev/null
++++ b/drivers/firmware/xilinx/zynqmp-debug.c
+@@ -0,0 +1,212 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Xilinx Zynq MPSoC Firmware layer for debugfs APIs
++ *
++ * Copyright (C) 2014-2018 Xilinx, Inc.
++ *
++ * Michal Simek <michal.simek@xilinx.com>
++ * Davorin Mista <davorin.mista@aggios.com>
++ * Jolly Shah <jollys@xilinx.com>
++ * Rajan Vaja <rajanv@xilinx.com>
++ */
++
++#include <linux/compiler.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/uaccess.h>
++
++#include <linux/firmware/xlnx-zynqmp.h>
++#include "zynqmp-debug.h"
++
++#define PM_API_NAME_LEN 50
++
++struct pm_api_info {
++ u32 api_id;
++ char api_name[PM_API_NAME_LEN];
++ char api_name_len;
++};
++
++static char debugfs_buf[PAGE_SIZE];
++
++#define PM_API(id) {id, #id, strlen(#id)}
++static struct pm_api_info pm_api_list[] = {
++ PM_API(PM_GET_API_VERSION),
++};
++
++/**
++ * zynqmp_pm_argument_value() - Extract argument value from a PM-API request
++ * @arg: Entered PM-API argument in string format
++ *
++ * Return: Argument value in unsigned integer format on success
++ * 0 otherwise
++ */
++static u64 zynqmp_pm_argument_value(char *arg)
++{
++ u64 value;
++
++ if (!arg)
++ return 0;
++
++ if (!kstrtou64(arg, 0, &value))
++ return value;
++
++ return 0;
++}
++
++/**
++ * get_pm_api_id() - Extract API-ID from a PM-API request
++ * @pm_api_req: Entered PM-API argument in string format
++ * @pm_id: API-ID
++ *
++ * Return: 0 on success else error code
++ */
++static int get_pm_api_id(char *pm_api_req, u32 *pm_id)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(pm_api_list) ; i++) {
++ if (!strncasecmp(pm_api_req, pm_api_list[i].api_name,
++ pm_api_list[i].api_name_len)) {
++ *pm_id = pm_api_list[i].api_id;
++ break;
++ }
++ }
++
++ /* If no name was entered look for PM-API ID instead */
++ if (i == ARRAY_SIZE(pm_api_list) && kstrtouint(pm_api_req, 10, pm_id))
++ return -EINVAL;
++
++ return 0;
++}
++
++static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret)
++{
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++ u32 pm_api_version;
++ int ret;
++
++ if (!eemi_ops)
++ return -ENXIO;
++
++ switch (pm_id) {
++ case PM_GET_API_VERSION:
++ ret = eemi_ops->get_api_version(&pm_api_version);
++ sprintf(debugfs_buf, "PM-API Version = %d.%d\n",
++ pm_api_version >> 16, pm_api_version & 0xffff);
++ break;
++ default:
++ sprintf(debugfs_buf, "Unsupported PM-API request\n");
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++/**
++ * zynqmp_pm_debugfs_api_write() - debugfs write function
++ * @file: User file
++ * @ptr: User entered PM-API string
++ * @len: Length of the userspace buffer
++ * @off: Offset within the file
++ *
++ * Used for triggering pm api functions by writing
++ * echo <pm_api_id> > /sys/kernel/debug/zynqmp_pm/power or
++ * echo <pm_api_name> > /sys/kernel/debug/zynqmp_pm/power
++ *
++ * Return: Number of bytes copied if PM-API request succeeds,
++ * the corresponding error code otherwise
++ */
++static ssize_t zynqmp_pm_debugfs_api_write(struct file *file,
++ const char __user *ptr, size_t len,
++ loff_t *off)
++{
++ char *kern_buff, *tmp_buff;
++ char *pm_api_req;
++ u32 pm_id = 0;
++ u64 pm_api_arg[4] = {0, 0, 0, 0};
++ /* Return values from PM APIs calls */
++ u32 pm_api_ret[4] = {0, 0, 0, 0};
++
++ int ret;
++ int i = 0;
++
++ strcpy(debugfs_buf, "");
++
++ if (*off != 0 || len == 0)
++ return -EINVAL;
++
++ kern_buff = kzalloc(len, GFP_KERNEL);
++ if (!kern_buff)
++ return -ENOMEM;
++
++ tmp_buff = kern_buff;
++
++ ret = strncpy_from_user(kern_buff, ptr, len);
++ if (ret < 0) {
++ ret = -EFAULT;
++ goto err;
++ }
++
++ /* Read the API name from a user request */
++ pm_api_req = strsep(&kern_buff, " ");
++
++ ret = get_pm_api_id(pm_api_req, &pm_id);
++ if (ret < 0)
++ goto err;
++
++ /* Read node_id and arguments from the PM-API request */
++ pm_api_req = strsep(&kern_buff, " ");
++ while ((i < ARRAY_SIZE(pm_api_arg)) && pm_api_req) {
++ pm_api_arg[i++] = zynqmp_pm_argument_value(pm_api_req);
++ pm_api_req = strsep(&kern_buff, " ");
++ }
++
++ ret = process_api_request(pm_id, pm_api_arg, pm_api_ret);
++
++err:
++ kfree(tmp_buff);
++ if (ret)
++ return ret;
++
++ return len;
++}
++
++/**
++ * zynqmp_pm_debugfs_api_read() - debugfs read function
++ * @file: User file
++ * @ptr: Requested pm_api_version string
++ * @len: Length of the userspace buffer
++ * @off: Offset within the file
++ *
++ * Return: Length of the version string on success
++ * else error code
++ */
++static ssize_t zynqmp_pm_debugfs_api_read(struct file *file, char __user *ptr,
++ size_t len, loff_t *off)
++{
++ return simple_read_from_buffer(ptr, len, off, debugfs_buf,
++ strlen(debugfs_buf));
++}
++
++/* Setup debugfs fops */
++static const struct file_operations fops_zynqmp_pm_dbgfs = {
++ .owner = THIS_MODULE,
++ .write = zynqmp_pm_debugfs_api_write,
++ .read = zynqmp_pm_debugfs_api_read,
++};
++
++/**
++ * zynqmp_pm_api_debugfs_init - Initialize debugfs interface
++ *
++ * Return: None
++ */
++void zynqmp_pm_api_debugfs_init(void)
++{
++ struct dentry *root_dir;
++
++ /* Initialize debugfs interface */
++ root_dir = debugfs_create_dir("zynqmp-firmware", NULL);
++ debugfs_create_file("pm", 0660, root_dir, NULL,
++ &fops_zynqmp_pm_dbgfs);
++}
+diff --git a/drivers/firmware/xilinx/zynqmp-debug.h b/drivers/firmware/xilinx/zynqmp-debug.h
+new file mode 100644
+index 0000000..3303b37
+--- /dev/null
++++ b/drivers/firmware/xilinx/zynqmp-debug.h
+@@ -0,0 +1,22 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Xilinx Zynq MPSoC Firmware layer
++ *
++ * Copyright (C) 2014-2018 Xilinx
++ *
++ * Michal Simek <michal.simek@xilinx.com>
++ * Davorin Mista <davorin.mista@aggios.com>
++ * Jolly Shah <jollys@xilinx.com>
++ * Rajan Vaja <rajanv@xilinx.com>
++ */
++
++#ifndef __FIRMWARE_ZYNQMP_DEBUG_H__
++#define __FIRMWARE_ZYNQMP_DEBUG_H__
++
++#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE_DEBUG)
++void zynqmp_pm_api_debugfs_init(void);
++#else
++static inline void zynqmp_pm_api_debugfs_init(void) { }
++#endif
++
++#endif /* __FIRMWARE_ZYNQMP_DEBUG_H__ */
+diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
+index 41ed800..7ccedf0 100644
+--- a/drivers/firmware/xilinx/zynqmp.c
++++ b/drivers/firmware/xilinx/zynqmp.c
+@@ -21,6 +21,7 @@
+ #include <linux/uaccess.h>
+
+ #include <linux/firmware/xlnx-zynqmp.h>
++#include "zynqmp-debug.h"
+
+ /**
+ * zynqmp_pm_ret_code() - Convert PMU-FW error codes to Linux error codes
+@@ -551,3 +552,11 @@ static int __init zynqmp_plat_init(void)
+ return ret;
+ }
+ early_initcall(zynqmp_plat_init);
++
++static int zynqmp_firmware_init(void)
++{
++ zynqmp_pm_api_debugfs_init();
++
++ return 0;
++}
++device_initcall(zynqmp_firmware_init);
+
+From patchwork Fri Aug 3 17:53:24 2018
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+Subject: [PATCH v11 07/11] firmware: xilinx: Add debugfs for IOCTL API
+Date: Fri, 3 Aug 2018 10:53:24 -0700
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+From: Rajan Vaja <rajanv@xilinx.com>
+
+Add debugfs file to set/get IOCTL using debugfs interface.
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+---
+ drivers/firmware/xilinx/zynqmp-debug.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/firmware/xilinx/zynqmp-debug.c b/drivers/firmware/xilinx/zynqmp-debug.c
+index fcbdd6e..fc11db9 100644
+--- a/drivers/firmware/xilinx/zynqmp-debug.c
++++ b/drivers/firmware/xilinx/zynqmp-debug.c
+@@ -32,6 +32,7 @@ static char debugfs_buf[PAGE_SIZE];
+ #define PM_API(id) {id, #id, strlen(#id)}
+ static struct pm_api_info pm_api_list[] = {
+ PM_API(PM_GET_API_VERSION),
++ PM_API(PM_IOCTL),
+ };
+
+ /**
+@@ -95,6 +96,15 @@ static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret)
+ sprintf(debugfs_buf, "PM-API Version = %d.%d\n",
+ pm_api_version >> 16, pm_api_version & 0xffff);
+ break;
++ case PM_IOCTL:
++ ret = eemi_ops->ioctl(pm_api_arg[0], pm_api_arg[1],
++ pm_api_arg[2], pm_api_arg[3],
++ &pm_api_ret[0]);
++ if (!ret && (pm_api_arg[1] == IOCTL_GET_PLL_FRAC_MODE ||
++ pm_api_arg[1] == IOCTL_GET_PLL_FRAC_DATA))
++ sprintf(debugfs_buf, "IOCTL return value: %u\n",
++ pm_api_ret[1]);
++ break;
+ default:
+ sprintf(debugfs_buf, "Unsupported PM-API request\n");
+ ret = -EINVAL;
+
+From patchwork Fri Aug 3 17:53:25 2018
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+From: Jolly Shah <jolly.shah@xilinx.com>
+To: <ard.biesheuvel@linaro.org>, <mingo@kernel.org>,
+ <gregkh@linuxfoundation.org>, <matt@codeblueprint.co.uk>,
+ <sudeep.holla@arm.com>, <hkallweit1@gmail.com>, <keescook@chromium.org>,
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+Subject: [PATCH v11 08/11] firmware: xilinx: Add debugfs for query data API
+Date: Fri, 3 Aug 2018 10:53:25 -0700
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+ linux-arm-kernel@lists.infradead.org, Jolly Shah <jollys@xilinx.com>
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+From: Rajan Vaja <rajanv@xilinx.com>
+
+Add debugfs file to query platform specific data from firmware
+using debugfs interface.
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+---
+ drivers/firmware/xilinx/zynqmp-debug.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/drivers/firmware/xilinx/zynqmp-debug.c b/drivers/firmware/xilinx/zynqmp-debug.c
+index fc11db9..4532bd0 100644
+--- a/drivers/firmware/xilinx/zynqmp-debug.c
++++ b/drivers/firmware/xilinx/zynqmp-debug.c
+@@ -33,6 +33,7 @@ static char debugfs_buf[PAGE_SIZE];
+ static struct pm_api_info pm_api_list[] = {
+ PM_API(PM_GET_API_VERSION),
+ PM_API(PM_IOCTL),
++ PM_API(PM_QUERY_DATA),
+ };
+
+ /**
+@@ -105,6 +106,32 @@ static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret)
+ sprintf(debugfs_buf, "IOCTL return value: %u\n",
+ pm_api_ret[1]);
+ break;
++ case PM_QUERY_DATA:
++ {
++ struct zynqmp_pm_query_data qdata = {0};
++
++ qdata.qid = pm_api_arg[0];
++ qdata.arg1 = pm_api_arg[1];
++ qdata.arg2 = pm_api_arg[2];
++ qdata.arg3 = pm_api_arg[3];
++
++ ret = eemi_ops->query_data(qdata, pm_api_ret);
++ if (ret)
++ break;
++
++ if (qdata.qid == PM_QID_CLOCK_GET_NAME)
++ sprintf(debugfs_buf, "Clock name = %s\n",
++ (char *)pm_api_ret);
++ else if (qdata.qid == PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS)
++ sprintf(debugfs_buf, "Multiplier = %d, Divider = %d\n",
++ pm_api_ret[1], pm_api_ret[2]);
++ else
++ sprintf(debugfs_buf,
++ "data[0] = 0x%08x\ndata[1] = 0x%08x\n data[2] = 0x%08x\ndata[3] = 0x%08x\n",
++ pm_api_ret[0], pm_api_ret[1],
++ pm_api_ret[2], pm_api_ret[3]);
++ break;
++ }
+ default:
+ sprintf(debugfs_buf, "Unsupported PM-API request\n");
+ ret = -EINVAL;
+
+From patchwork Fri Aug 3 17:53:26 2018
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+From: Jolly Shah <jolly.shah@xilinx.com>
+To: <ard.biesheuvel@linaro.org>, <mingo@kernel.org>,
+ <gregkh@linuxfoundation.org>, <matt@codeblueprint.co.uk>,
+ <sudeep.holla@arm.com>, <hkallweit1@gmail.com>, <keescook@chromium.org>,
+ <dmitry.torokhov@gmail.com>, <mturquette@baylibre.com>,
+ <sboyd@codeaurora.org>, <michal.simek@xilinx.com>, <robh+dt@kernel.org>,
+ <mark.rutland@arm.com>, <linux-clk@vger.kernel.org>
+Subject: [PATCH v11 09/11] dt-bindings: clock: Add bindings for ZynqMP clock
+ driver
+Date: Fri, 3 Aug 2018 10:53:26 -0700
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+From: Rajan Vaja <rajanv@xilinx.com>
+
+Add documentation to describe Xilinx ZynqMP clock driver
+bindings.
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 53 ++++++++++
+ include/dt-bindings/clock/xlnx,zynqmp-clk.h | 116 +++++++++++++++++++++
+ 2 files changed, 169 insertions(+)
+ create mode 100644 include/dt-bindings/clock/xlnx,zynqmp-clk.h
+
+diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+index 1b431d9..d215d15 100644
+--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
++++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+@@ -17,6 +17,53 @@ Required properties:
+ - "smc" : SMC #0, following the SMCCC
+ - "hvc" : HVC #0, following the SMCCC
+
++--------------------------------------------------------------------------
++Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
++Zynq MPSoC firmware interface
++--------------------------------------------------------------------------
++The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
++tree. It reads required input clock frequencies from the devicetree and acts
++as clock provider for all clock consumers of PS clocks.
++
++See clock_bindings.txt for more information on the generic clock bindings.
++
++Required properties:
++ - #clock-cells: Must be 1
++ - compatible: Must contain: "xlnx,zynqmp-clk"
++ - clocks: List of clock specifiers which are external input
++ clocks to the given clock controller. Please refer
++ the next section to find the input clocks for a
++ given controller.
++ - clock-names: List of clock names which are exteral input clocks
++ to the given clock controller. Please refer to the
++ clock bindings for more details.
++
++Input clocks for zynqmp Ultrascale+ clock controller:
++
++The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
++inputs. These required clock inputs are:
++ - pss_ref_clk (PS reference clock)
++ - video_clk (reference clock for video system )
++ - pss_alt_ref_clk (alternative PS reference clock)
++ - aux_ref_clk
++ - gt_crx_ref_clk (transceiver reference clock)
++
++The following strings are optional parameters to the 'clock-names' property in
++order to provide an optional (E)MIO clock source:
++ - swdt0_ext_clk
++ - swdt1_ext_clk
++ - gem0_emio_clk
++ - gem1_emio_clk
++ - gem2_emio_clk
++ - gem3_emio_clk
++ - mio_clk_XX # with XX = 00..77
++ - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
++
++
++Output clocks are registered based on clock information received
++from firmware. Output clocks indexes are mentioned in
++include/dt-bindings/clock/xlnx,zynqmp-clk.h.
++
+ -------
+ Example
+ -------
+@@ -25,5 +72,11 @@ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
++ zynqmp_clk : clock-controller {
++ #clock-cells = <1>;
++ compatible = "xlnx,zynqmp-clk";
++ clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
++ clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
++ };
+ };
+ };
+diff --git a/include/dt-bindings/clock/xlnx,zynqmp-clk.h b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
+new file mode 100644
+index 0000000..4aebe6e
+--- /dev/null
++++ b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
+@@ -0,0 +1,116 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Xilinx Zynq MPSoC Firmware layer
++ *
++ * Copyright (C) 2014-2018 Xilinx, Inc.
++ *
++ */
++
++#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
++#define _DT_BINDINGS_CLK_ZYNQMP_H
++
++#define IOPLL 0
++#define RPLL 1
++#define APLL 2
++#define DPLL 3
++#define VPLL 4
++#define IOPLL_TO_FPD 5
++#define RPLL_TO_FPD 6
++#define APLL_TO_LPD 7
++#define DPLL_TO_LPD 8
++#define VPLL_TO_LPD 9
++#define ACPU 10
++#define ACPU_HALF 11
++#define DBF_FPD 12
++#define DBF_LPD 13
++#define DBG_TRACE 14
++#define DBG_TSTMP 15
++#define DP_VIDEO_REF 16
++#define DP_AUDIO_REF 17
++#define DP_STC_REF 18
++#define GDMA_REF 19
++#define DPDMA_REF 20
++#define DDR_REF 21
++#define SATA_REF 22
++#define PCIE_REF 23
++#define GPU_REF 24
++#define GPU_PP0_REF 25
++#define GPU_PP1_REF 26
++#define TOPSW_MAIN 27
++#define TOPSW_LSBUS 28
++#define GTGREF0_REF 29
++#define LPD_SWITCH 30
++#define LPD_LSBUS 31
++#define USB0_BUS_REF 32
++#define USB1_BUS_REF 33
++#define USB3_DUAL_REF 34
++#define USB0 35
++#define USB1 36
++#define CPU_R5 37
++#define CPU_R5_CORE 38
++#define CSU_SPB 39
++#define CSU_PLL 40
++#define PCAP 41
++#define IOU_SWITCH 42
++#define GEM_TSU_REF 43
++#define GEM_TSU 44
++#define GEM0_REF 45
++#define GEM1_REF 46
++#define GEM2_REF 47
++#define GEM3_REF 48
++#define GEM0_TX 49
++#define GEM1_TX 50
++#define GEM2_TX 51
++#define GEM3_TX 52
++#define QSPI_REF 53
++#define SDIO0_REF 54
++#define SDIO1_REF 55
++#define UART0_REF 56
++#define UART1_REF 57
++#define SPI0_REF 58
++#define SPI1_REF 59
++#define NAND_REF 60
++#define I2C0_REF 61
++#define I2C1_REF 62
++#define CAN0_REF 63
++#define CAN1_REF 64
++#define CAN0 65
++#define CAN1 66
++#define DLL_REF 67
++#define ADMA_REF 68
++#define TIMESTAMP_REF 69
++#define AMS_REF 70
++#define PL0_REF 71
++#define PL1_REF 72
++#define PL2_REF 73
++#define PL3_REF 74
++#define WDT 75
++#define IOPLL_INT 76
++#define IOPLL_PRE_SRC 77
++#define IOPLL_HALF 78
++#define IOPLL_INT_MUX 79
++#define IOPLL_POST_SRC 80
++#define RPLL_INT 81
++#define RPLL_PRE_SRC 82
++#define RPLL_HALF 83
++#define RPLL_INT_MUX 84
++#define RPLL_POST_SRC 85
++#define APLL_INT 86
++#define APLL_PRE_SRC 87
++#define APLL_HALF 88
++#define APLL_INT_MUX 89
++#define APLL_POST_SRC 90
++#define DPLL_INT 91
++#define DPLL_PRE_SRC 92
++#define DPLL_HALF 93
++#define DPLL_INT_MUX 94
++#define DPLL_POST_SRC 95
++#define VPLL_INT 96
++#define VPLL_PRE_SRC 97
++#define VPLL_HALF 98
++#define VPLL_INT_MUX 99
++#define VPLL_POST_SRC 100
++#define CAN0_MIO 101
++#define CAN1_MIO 102
++
++#endif
+
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+Subject: [PATCH v11 10/11] drivers: clk: Add ZynqMP clock driver
+Date: Fri, 3 Aug 2018 10:53:27 -0700
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+Cc: devicetree@vger.kernel.org, Tejas Patel <tejasp@xilinx.com>,
+ Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>,
+ linux-kernel@vger.kernel.org, Jolly Shah <jollys@xilinx.com>,
+ rajanv@xilinx.com, Jolly Shah <jolly.shah@xilinx.com>,
+ linux-arm-kernel@lists.infradead.org
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+From: Jolly Shah <jolly.shah@xilinx.com>
+
+This patch adds CCF compliant clock driver for ZynqMP.
+Clock driver queries supported clock information from
+firmware and regiters pll and output clocks with CCF.
+
+Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
+Signed-off-by: Tejas Patel <tejasp@xilinx.com>
+Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+---
+ drivers/clk/Kconfig | 1 +
+ drivers/clk/Makefile | 1 +
+ drivers/clk/zynqmp/Kconfig | 10 +
+ drivers/clk/zynqmp/Makefile | 4 +
+ drivers/clk/zynqmp/clk-gate-zynqmp.c | 144 +++++++
+ drivers/clk/zynqmp/clk-mux-zynqmp.c | 141 +++++++
+ drivers/clk/zynqmp/clk-zynqmp.h | 68 ++++
+ drivers/clk/zynqmp/clkc.c | 716 +++++++++++++++++++++++++++++++++++
+ drivers/clk/zynqmp/divider.c | 217 +++++++++++
+ drivers/clk/zynqmp/pll.c | 335 ++++++++++++++++
+ include/linux/firmware/xlnx-zynqmp.h | 1 +
+ 11 files changed, 1638 insertions(+)
+ create mode 100644 drivers/clk/zynqmp/Kconfig
+ create mode 100644 drivers/clk/zynqmp/Makefile
+ create mode 100644 drivers/clk/zynqmp/clk-gate-zynqmp.c
+ create mode 100644 drivers/clk/zynqmp/clk-mux-zynqmp.c
+ create mode 100644 drivers/clk/zynqmp/clk-zynqmp.h
+ create mode 100644 drivers/clk/zynqmp/clkc.c
+ create mode 100644 drivers/clk/zynqmp/divider.c
+ create mode 100644 drivers/clk/zynqmp/pll.c
+
+diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
+index 98ce9fc..ab2ea76 100644
+--- a/drivers/clk/Kconfig
++++ b/drivers/clk/Kconfig
+@@ -253,5 +253,6 @@ source "drivers/clk/sunxi-ng/Kconfig"
+ source "drivers/clk/tegra/Kconfig"
+ source "drivers/clk/ti/Kconfig"
+ source "drivers/clk/uniphier/Kconfig"
++source "drivers/clk/zynqmp/Kconfig"
+
+ endmenu
+diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
+index 71ec41e..b6ac0d2 100644
+--- a/drivers/clk/Makefile
++++ b/drivers/clk/Makefile
+@@ -100,3 +100,4 @@ obj-$(CONFIG_X86) += x86/
+ endif
+ obj-$(CONFIG_ARCH_ZX) += zte/
+ obj-$(CONFIG_ARCH_ZYNQ) += zynq/
++obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
+diff --git a/drivers/clk/zynqmp/Kconfig b/drivers/clk/zynqmp/Kconfig
+new file mode 100644
+index 0000000..1708605
+--- /dev/null
++++ b/drivers/clk/zynqmp/Kconfig
+@@ -0,0 +1,10 @@
++# SPDX-License-Identifier: GPL-2.0
++
++config COMMON_CLK_ZYNQMP
++ bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
++ depends on ARCH_ZYNQMP || COMPILE_TEST
++ depends on ZYNQMP_FIRMWARE
++ help
++ Support for the Zynqmp Ultrascale clock controller.
++ It has a dependency on the PMU firmware.
++ Say Y if you want to include clock support.
+diff --git a/drivers/clk/zynqmp/Makefile b/drivers/clk/zynqmp/Makefile
+new file mode 100644
+index 0000000..0ec24bf
+--- /dev/null
++++ b/drivers/clk/zynqmp/Makefile
+@@ -0,0 +1,4 @@
++# SPDX-License-Identifier: GPL-2.0
++# Zynq Ultrascale+ MPSoC clock specific Makefile
++
++obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o
+diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c
+new file mode 100644
+index 0000000..83b236f
+--- /dev/null
++++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c
+@@ -0,0 +1,144 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Zynq UltraScale+ MPSoC clock controller
++ *
++ * Copyright (C) 2016-2018 Xilinx
++ *
++ * Gated clock implementation
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/slab.h>
++#include "clk-zynqmp.h"
++
++/**
++ * struct clk_gate - gating clock
++ * @hw: handle between common and hardware-specific interfaces
++ * @flags: hardware-specific flags
++ * @clk_id: Id of clock
++ */
++struct zynqmp_clk_gate {
++ struct clk_hw hw;
++ u8 flags;
++ u32 clk_id;
++};
++
++#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw)
++
++/**
++ * zynqmp_clk_gate_enable() - Enable clock
++ * @hw: handle between common and hardware-specific interfaces
++ *
++ * Return: 0 on success else error code
++ */
++static int zynqmp_clk_gate_enable(struct clk_hw *hw)
++{
++ struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = gate->clk_id;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ ret = eemi_ops->clock_enable(clk_id);
++
++ if (ret)
++ pr_warn_once("%s() clock enabled failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ return ret;
++}
++
++/*
++ * zynqmp_clk_gate_disable() - Disable clock
++ * @hw: handle between common and hardware-specific interfaces
++ */
++static void zynqmp_clk_gate_disable(struct clk_hw *hw)
++{
++ struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = gate->clk_id;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ ret = eemi_ops->clock_disable(clk_id);
++
++ if (ret)
++ pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++}
++
++/**
++ * zynqmp_clk_gate_is_enable() - Check clock state
++ * @hw: handle between common and hardware-specific interfaces
++ *
++ * Return: 1 if enabled, 0 if disabled else error code
++ */
++static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
++{
++ struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = gate->clk_id;
++ int state, ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ ret = eemi_ops->clock_getstate(clk_id, &state);
++ if (ret) {
++ pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++ return -EIO;
++ }
++
++ return state ? 1 : 0;
++}
++
++static const struct clk_ops zynqmp_clk_gate_ops = {
++ .enable = zynqmp_clk_gate_enable,
++ .disable = zynqmp_clk_gate_disable,
++ .is_enabled = zynqmp_clk_gate_is_enabled,
++};
++
++/**
++ * zynqmp_clk_register_gate() - Register a gate clock with the clock framework
++ * @name: Name of this clock
++ * @clk_id: Id of this clock
++ * @parents: Name of this clock's parents
++ * @num_parents: Number of parents
++ * @nodes: Clock topology node
++ *
++ * Return: clock hardware of the registered clock gate
++ */
++struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes)
++{
++ struct zynqmp_clk_gate *gate;
++ struct clk_hw *hw;
++ int ret;
++ struct clk_init_data init;
++
++ /* allocate the gate */
++ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
++ if (!gate)
++ return ERR_PTR(-ENOMEM);
++
++ init.name = name;
++ init.ops = &zynqmp_clk_gate_ops;
++ init.flags = nodes->flag;
++ init.parent_names = parents;
++ init.num_parents = 1;
++
++ /* struct clk_gate assignments */
++ gate->flags = nodes->type_flag;
++ gate->hw.init = &init;
++ gate->clk_id = clk_id;
++
++ hw = &gate->hw;
++ ret = clk_hw_register(NULL, hw);
++ if (ret) {
++ kfree(gate);
++ hw = ERR_PTR(ret);
++ }
++
++ return hw;
++}
+diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
+new file mode 100644
+index 0000000..4143f56
+--- /dev/null
++++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
+@@ -0,0 +1,141 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Zynq UltraScale+ MPSoC mux
++ *
++ * Copyright (C) 2016-2018 Xilinx
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/slab.h>
++#include "clk-zynqmp.h"
++
++/*
++ * DOC: basic adjustable multiplexer clock that cannot gate
++ *
++ * Traits of this clock:
++ * prepare - clk_prepare only ensures that parents are prepared
++ * enable - clk_enable only ensures that parents are enabled
++ * rate - rate is only affected by parent switching. No clk_set_rate support
++ * parent - parent is adjustable through clk_set_parent
++ */
++
++/**
++ * struct zynqmp_clk_mux - multiplexer clock
++ *
++ * @hw: handle between common and hardware-specific interfaces
++ * @flags: hardware-specific flags
++ * @clk_id: Id of clock
++ */
++struct zynqmp_clk_mux {
++ struct clk_hw hw;
++ u8 flags;
++ u32 clk_id;
++};
++
++#define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw)
++
++/**
++ * zynqmp_clk_mux_get_parent() - Get parent of clock
++ * @hw: handle between common and hardware-specific interfaces
++ *
++ * Return: Parent index
++ */
++static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw)
++{
++ struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = mux->clk_id;
++ u32 val;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ ret = eemi_ops->clock_getparent(clk_id, &val);
++
++ if (ret)
++ pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ return val;
++}
++
++/**
++ * zynqmp_clk_mux_set_parent() - Set parent of clock
++ * @hw: handle between common and hardware-specific interfaces
++ * @index: Parent index
++ *
++ * Return: 0 on success else error+reason
++ */
++static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
++{
++ struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = mux->clk_id;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ ret = eemi_ops->clock_setparent(clk_id, index);
++
++ if (ret)
++ pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ return ret;
++}
++
++static const struct clk_ops zynqmp_clk_mux_ops = {
++ .get_parent = zynqmp_clk_mux_get_parent,
++ .set_parent = zynqmp_clk_mux_set_parent,
++ .determine_rate = __clk_mux_determine_rate,
++};
++
++static const struct clk_ops zynqmp_clk_mux_ro_ops = {
++ .get_parent = zynqmp_clk_mux_get_parent,
++};
++
++/**
++ * zynqmp_clk_register_mux() - Register a mux table with the clock
++ * framework
++ * @name: Name of this clock
++ * @clk_id: Id of this clock
++ * @parents: Name of this clock's parents
++ * @num_parents: Number of parents
++ * @nodes: Clock topology node
++ *
++ * Return: clock hardware of the registered clock mux
++ */
++struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes)
++{
++ struct zynqmp_clk_mux *mux;
++ struct clk_hw *hw;
++ struct clk_init_data init;
++ int ret;
++
++ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
++ if (!mux)
++ return ERR_PTR(-ENOMEM);
++
++ init.name = name;
++ if (nodes->type_flag & CLK_MUX_READ_ONLY)
++ init.ops = &zynqmp_clk_mux_ro_ops;
++ else
++ init.ops = &zynqmp_clk_mux_ops;
++ init.flags = nodes->flag;
++ init.parent_names = parents;
++ init.num_parents = num_parents;
++ mux->flags = nodes->type_flag;
++ mux->hw.init = &init;
++ mux->clk_id = clk_id;
++
++ hw = &mux->hw;
++ ret = clk_hw_register(NULL, hw);
++ if (ret) {
++ kfree(hw);
++ hw = ERR_PTR(ret);
++ }
++
++ return hw;
++}
++EXPORT_SYMBOL_GPL(zynqmp_clk_register_mux);
+diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
+new file mode 100644
+index 0000000..7ab163b
+--- /dev/null
++++ b/drivers/clk/zynqmp/clk-zynqmp.h
+@@ -0,0 +1,68 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2016-2018 Xilinx
++ */
++
++#ifndef __LINUX_CLK_ZYNQMP_H_
++#define __LINUX_CLK_ZYNQMP_H_
++
++#include <linux/spinlock.h>
++
++#include <linux/firmware/xlnx-zynqmp.h>
++
++/* Clock APIs payload parameters */
++#define CLK_GET_NAME_RESP_LEN 16
++#define CLK_GET_TOPOLOGY_RESP_WORDS 3
++#define CLK_GET_PARENTS_RESP_WORDS 3
++#define CLK_GET_ATTR_RESP_WORDS 1
++
++enum topology_type {
++ TYPE_INVALID,
++ TYPE_MUX,
++ TYPE_PLL,
++ TYPE_FIXEDFACTOR,
++ TYPE_DIV1,
++ TYPE_DIV2,
++ TYPE_GATE,
++};
++
++/**
++ * struct clock_topology - Clock topology
++ * @type: Type of topology
++ * @flag: Topology flags
++ * @type_flag: Topology type specific flag
++ */
++struct clock_topology {
++ u32 type;
++ u32 flag;
++ u32 type_flag;
++};
++
++struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes);
++
++struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes);
++
++struct clk_hw *zynqmp_clk_register_divider(const char *name,
++ u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes);
++
++struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes);
++
++struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
++ u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes);
++
++#endif
+diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
+new file mode 100644
+index 0000000..1b07d77
+--- /dev/null
++++ b/drivers/clk/zynqmp/clkc.c
+@@ -0,0 +1,716 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Zynq UltraScale+ MPSoC clock controller
++ *
++ * Copyright (C) 2016-2018 Xilinx
++ *
++ * Based on drivers/clk/zynq/clkc.c
++ */
++
++#include <linux/bitfield.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++
++#include "clk-zynqmp.h"
++
++#define MAX_PARENT 100
++#define MAX_NODES 6
++#define MAX_NAME_LEN 50
++
++#define CLK_TYPE_SHIFT 2
++
++#define PM_API_PAYLOAD_LEN 3
++
++#define NA_PARENT 0xFFFFFFFF
++#define DUMMY_PARENT 0xFFFFFFFE
++
++#define CLK_TYPE_FIELD_LEN 4
++#define CLK_TOPOLOGY_NODE_OFFSET 16
++#define NODES_PER_RESP 3
++
++#define CLK_TYPE_FIELD_MASK 0xF
++#define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
++#define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
++
++#define CLK_PARENTS_ID_LEN 16
++#define CLK_PARENTS_ID_MASK 0xFFFF
++
++/* Flags for parents */
++#define PARENT_CLK_SELF 0
++#define PARENT_CLK_NODE1 1
++#define PARENT_CLK_NODE2 2
++#define PARENT_CLK_NODE3 3
++#define PARENT_CLK_NODE4 4
++#define PARENT_CLK_EXTERNAL 5
++
++#define END_OF_CLK_NAME "END_OF_CLK"
++#define END_OF_TOPOLOGY_NODE 1
++#define END_OF_PARENTS 1
++#define RESERVED_CLK_NAME ""
++
++#define CLK_VALID_MASK 0x1
++
++enum clk_type {
++ CLK_TYPE_OUTPUT,
++ CLK_TYPE_EXTERNAL,
++};
++
++/**
++ * struct clock_parent - Clock parent
++ * @name: Parent name
++ * @id: Parent clock ID
++ * @flag: Parent flags
++ */
++struct clock_parent {
++ char name[MAX_NAME_LEN];
++ int id;
++ u32 flag;
++};
++
++/**
++ * struct zynqmp_clock - Clock
++ * @clk_name: Clock name
++ * @valid: Validity flag of clock
++ * @type: Clock type (Output/External)
++ * @node: Clock topology nodes
++ * @num_nodes: Number of nodes present in topology
++ * @parent: Parent of clock
++ * @num_parents: Number of parents of clock
++ */
++struct zynqmp_clock {
++ char clk_name[MAX_NAME_LEN];
++ u32 valid;
++ enum clk_type type;
++ struct clock_topology node[MAX_NODES];
++ u32 num_nodes;
++ struct clock_parent parent[MAX_PARENT];
++ u32 num_parents;
++};
++
++static const char clk_type_postfix[][10] = {
++ [TYPE_INVALID] = "",
++ [TYPE_MUX] = "_mux",
++ [TYPE_GATE] = "",
++ [TYPE_DIV1] = "_div1",
++ [TYPE_DIV2] = "_div2",
++ [TYPE_FIXEDFACTOR] = "_ff",
++ [TYPE_PLL] = ""
++};
++
++static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes)
++ = {
++ [TYPE_INVALID] = NULL,
++ [TYPE_MUX] = zynqmp_clk_register_mux,
++ [TYPE_PLL] = zynqmp_clk_register_pll,
++ [TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor,
++ [TYPE_DIV1] = zynqmp_clk_register_divider,
++ [TYPE_DIV2] = zynqmp_clk_register_divider,
++ [TYPE_GATE] = zynqmp_clk_register_gate
++};
++
++static struct zynqmp_clock *clock;
++static struct clk_hw_onecell_data *zynqmp_data;
++static unsigned int clock_max_idx;
++static const struct zynqmp_eemi_ops *eemi_ops;
++
++/**
++ * zynqmp_is_valid_clock() - Check whether clock is valid or not
++ * @clk_id: Clock index
++ *
++ * Return: 1 if clock is valid, 0 if clock is invalid else error code
++ */
++static inline int zynqmp_is_valid_clock(u32 clk_id)
++{
++ if (clk_id > clock_max_idx)
++ return -ENODEV;
++
++ return clock[clk_id].valid;
++}
++
++/**
++ * zynqmp_get_clock_name() - Get name of clock from Clock index
++ * @clk_id: Clock index
++ * @clk_name: Name of clock
++ *
++ * Return: 0 on success else error code
++ */
++static int zynqmp_get_clock_name(u32 clk_id, char *clk_name)
++{
++ int ret;
++
++ ret = zynqmp_is_valid_clock(clk_id);
++ if (ret == 1) {
++ strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
++ return 0;
++ }
++
++ return ret == 0 ? -EINVAL : ret;
++}
++
++/**
++ * zynqmp_get_clock_type() - Get type of clock
++ * @clk_id: Clock index
++ * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL
++ *
++ * Return: 0 on success else error code
++ */
++static int zynqmp_get_clock_type(u32 clk_id, u32 *type)
++{
++ int ret;
++
++ ret = zynqmp_is_valid_clock(clk_id);
++ if (ret == 1) {
++ *type = clock[clk_id].type;
++ return 0;
++ }
++
++ return ret == 0 ? -EINVAL : ret;
++}
++
++/**
++ * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
++ * @nclocks: Number of clocks in system/board.
++ *
++ * Call firmware API to get number of clocks.
++ *
++ * Return: 0 on success else error code.
++ */
++static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks)
++{
++ struct zynqmp_pm_query_data qdata = {0};
++ __le32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
++
++ ret = eemi_ops->query_data(qdata, ret_payload);
++ *nclocks = ret_payload[1];
++
++ return ret;
++}
++
++/**
++ * zynqmp_pm_clock_get_name() - Get the name of clock for given id
++ * @clock_id: ID of the clock to be queried
++ * @name: Name of given clock
++ *
++ * This function is used to get name of clock specified by given
++ * clock ID.
++ *
++ * Return: Returns 0, in case of error name would be 0
++ */
++static int zynqmp_pm_clock_get_name(u32 clock_id, char *name)
++{
++ struct zynqmp_pm_query_data qdata = {0};
++ __le32 ret_payload[PAYLOAD_ARG_CNT];
++
++ qdata.qid = PM_QID_CLOCK_GET_NAME;
++ qdata.arg1 = clock_id;
++
++ eemi_ops->query_data(qdata, ret_payload);
++ memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
++
++ return 0;
++}
++
++/**
++ * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
++ * @clock_id: ID of the clock to be queried
++ * @index: Node index of clock topology
++ * @topology: Buffer to store nodes in topology and flags
++ *
++ * This function is used to get topology information for the clock
++ * specified by given clock ID.
++ *
++ * This API will return 3 node of topology with a single response. To get
++ * other nodes, master should call same API in loop with new
++ * index till error is returned. E.g First call should have
++ * index 0 which will return nodes 0,1 and 2. Next call, index
++ * should be 3 which will return nodes 3,4 and 5 and so on.
++ *
++ * Return: 0 on success else error+reason
++ */
++static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
++{
++ struct zynqmp_pm_query_data qdata = {0};
++ __le32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
++ qdata.arg1 = clock_id;
++ qdata.arg2 = index;
++
++ ret = eemi_ops->query_data(qdata, ret_payload);
++ memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
++
++ return ret;
++}
++
++/**
++ * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
++ * clock framework
++ * @name: Name of this clock
++ * @clk_id: Clock ID
++ * @parents: Name of this clock's parents
++ * @num_parents: Number of parents
++ * @nodes: Clock topology node
++ *
++ * Return: clock hardware to the registered clock
++ */
++struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes)
++{
++ u32 mult, div;
++ struct clk_hw *hw;
++ struct zynqmp_pm_query_data qdata = {0};
++ __le32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
++ qdata.arg1 = clk_id;
++
++ ret = eemi_ops->query_data(qdata, ret_payload);
++ mult = ret_payload[1];
++ div = ret_payload[2];
++
++ hw = clk_hw_register_fixed_factor(NULL, name,
++ parents[0],
++ nodes->flag, mult,
++ div);
++
++ return hw;
++}
++
++/**
++ * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
++ * @clock_id: Clock ID
++ * @index: Parent index
++ * @parents: 3 parents of the given clock
++ *
++ * This function is used to get 3 parents for the clock specified by
++ * given clock ID.
++ *
++ * This API will return 3 parents with a single response. To get
++ * other parents, master should call same API in loop with new
++ * parent index till error is returned. E.g First call should have
++ * index 0 which will return parents 0,1 and 2. Next call, index
++ * should be 3 which will return parent 3,4 and 5 and so on.
++ *
++ * Return: 0 on success else error+reason
++ */
++static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
++{
++ struct zynqmp_pm_query_data qdata = {0};
++ __le32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ qdata.qid = PM_QID_CLOCK_GET_PARENTS;
++ qdata.arg1 = clock_id;
++ qdata.arg2 = index;
++
++ ret = eemi_ops->query_data(qdata, ret_payload);
++ memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
++
++ return ret;
++}
++
++/**
++ * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
++ * @clock_id: Clock ID
++ * @attr: Clock attributes
++ *
++ * This function is used to get clock's attributes(e.g. valid, clock type, etc).
++ *
++ * Return: 0 on success else error+reason
++ */
++static int zynqmp_pm_clock_get_attributes(u32 clock_id, u32 *attr)
++{
++ struct zynqmp_pm_query_data qdata = {0};
++ __le32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++
++ qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
++ qdata.arg1 = clock_id;
++
++ ret = eemi_ops->query_data(qdata, ret_payload);
++ memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
++
++ return ret;
++}
++
++/**
++ * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
++ * response data
++ * @topology: Clock topology
++ * @data: Clock topology data received from firmware
++ * @nnodes: Number of nodes
++ *
++ * Return: 0 on success else error+reason
++ */
++static int __zynqmp_clock_get_topology(struct clock_topology *topology,
++ u32 *data, u32 *nnodes)
++{
++ int i;
++
++ for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
++ if (!(data[i] & CLK_TYPE_FIELD_MASK))
++ return END_OF_TOPOLOGY_NODE;
++ topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
++ topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
++ data[i]);
++ topology[*nnodes].type_flag =
++ FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
++ (*nnodes)++;
++ }
++
++ return 0;
++}
++
++/**
++ * zynqmp_clock_get_topology() - Get topology of clock from firmware using
++ * PM_API
++ * @clk_id: Clock index
++ * @topology: Clock topology
++ * @num_nodes: Number of nodes
++ *
++ * Return: 0 on success else error+reason
++ */
++static int zynqmp_clock_get_topology(u32 clk_id,
++ struct clock_topology *topology,
++ u32 *num_nodes)
++{
++ int j, ret;
++ u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
++
++ *num_nodes = 0;
++ for (j = 0; j <= MAX_NODES; j += 3) {
++ ret = zynqmp_pm_clock_get_topology(clk_id, j, pm_resp);
++ if (ret)
++ return ret;
++ ret = __zynqmp_clock_get_topology(topology, pm_resp, num_nodes);
++ if (ret == END_OF_TOPOLOGY_NODE)
++ return 0;
++ }
++
++ return 0;
++}
++
++/**
++ * __zynqmp_clock_get_topology() - Get parents info of clock from firmware
++ * response data
++ * @parents: Clock parents
++ * @data: Clock parents data received from firmware
++ * @nparent: Number of parent
++ *
++ * Return: 0 on success else error+reason
++ */
++static int __zynqmp_clock_get_parents(struct clock_parent *parents, u32 *data,
++ u32 *nparent)
++{
++ int i;
++ struct clock_parent *parent;
++
++ for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
++ if (data[i] == NA_PARENT)
++ return END_OF_PARENTS;
++
++ parent = &parents[i];
++ parent->id = data[i] & CLK_PARENTS_ID_MASK;
++ if (data[i] == DUMMY_PARENT) {
++ strcpy(parent->name, "dummy_name");
++ parent->flag = 0;
++ } else {
++ parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
++ if (zynqmp_get_clock_name(parent->id, parent->name))
++ continue;
++ }
++ *nparent += 1;
++ }
++
++ return 0;
++}
++
++/**
++ * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
++ * @clk_id: Clock index
++ * @parents: Clock parents
++ * @num_parents: Total number of parents
++ *
++ * Return: 0 on success else error+reason
++ */
++static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents,
++ u32 *num_parents)
++{
++ int j = 0, ret;
++ u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
++
++ *num_parents = 0;
++ do {
++ /* Get parents from firmware */
++ ret = zynqmp_pm_clock_get_parents(clk_id, j, pm_resp);
++ if (ret)
++ return ret;
++
++ ret = __zynqmp_clock_get_parents(&parents[j], pm_resp,
++ num_parents);
++ if (ret == END_OF_PARENTS)
++ return 0;
++ j += PM_API_PAYLOAD_LEN;
++ } while (*num_parents <= MAX_PARENT);
++
++ return 0;
++}
++
++/**
++ * zynqmp_get_parent_list() - Create list of parents name
++ * @np: Device node
++ * @clk_id: Clock index
++ * @parent_list: List of parent's name
++ * @num_parents: Total number of parents
++ *
++ * Return: 0 on success else error+reason
++ */
++static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id,
++ const char **parent_list, u32 *num_parents)
++{
++ int i = 0, ret;
++ u32 total_parents = clock[clk_id].num_parents;
++ struct clock_topology *clk_nodes;
++ struct clock_parent *parents;
++
++ clk_nodes = clock[clk_id].node;
++ parents = clock[clk_id].parent;
++
++ for (i = 0; i < total_parents; i++) {
++ if (!parents[i].flag) {
++ parent_list[i] = parents[i].name;
++ } else if (parents[i].flag == PARENT_CLK_EXTERNAL) {
++ ret = of_property_match_string(np, "clock-names",
++ parents[i].name);
++ if (ret < 0)
++ strcpy(parents[i].name, "dummy_name");
++ parent_list[i] = parents[i].name;
++ } else {
++ strcat(parents[i].name,
++ clk_type_postfix[clk_nodes[parents[i].flag - 1].
++ type]);
++ parent_list[i] = parents[i].name;
++ }
++ }
++
++ *num_parents = total_parents;
++ return 0;
++}
++
++/**
++ * zynqmp_register_clk_topology() - Register clock topology
++ * @clk_id: Clock index
++ * @clk_name: Clock Name
++ * @num_parents: Total number of parents
++ * @parent_names: List of parents name
++ *
++ * Return: Returns either clock hardware or error+reason
++ */
++static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
++ int num_parents,
++ const char **parent_names)
++{
++ int j;
++ u32 num_nodes;
++ char *clk_out = NULL;
++ struct clock_topology *nodes;
++ struct clk_hw *hw = NULL;
++
++ nodes = clock[clk_id].node;
++ num_nodes = clock[clk_id].num_nodes;
++
++ for (j = 0; j < num_nodes; j++) {
++ /*
++ * Clock name received from firmware is output clock name.
++ * Intermediate clock names are postfixed with type of clock.
++ */
++ if (j != (num_nodes - 1)) {
++ clk_out = kasprintf(GFP_KERNEL, "%s%s", clk_name,
++ clk_type_postfix[nodes[j].type]);
++ } else {
++ clk_out = kasprintf(GFP_KERNEL, "%s", clk_name);
++ }
++
++ if (!clk_topology[nodes[j].type])
++ continue;
++
++ hw = (*clk_topology[nodes[j].type])(clk_out, clk_id,
++ parent_names,
++ num_parents,
++ &nodes[j]);
++ if (IS_ERR(hw))
++ pr_warn_once("%s() %s register fail with %ld\n",
++ __func__, clk_name, PTR_ERR(hw));
++
++ parent_names[0] = clk_out;
++ }
++ kfree(clk_out);
++ return hw;
++}
++
++/**
++ * zynqmp_register_clocks() - Register clocks
++ * @np: Device node
++ *
++ * Return: 0 on success else error code
++ */
++static int zynqmp_register_clocks(struct device_node *np)
++{
++ int ret;
++ u32 i, total_parents = 0, type = 0;
++ const char *parent_names[MAX_PARENT];
++
++ for (i = 0; i < clock_max_idx; i++) {
++ char clk_name[MAX_NAME_LEN];
++
++ /* get clock name, continue to next clock if name not found */
++ if (zynqmp_get_clock_name(i, clk_name))
++ continue;
++
++ /* Check if clock is valid and output clock.
++ * Do not register invalid or external clock.
++ */
++ ret = zynqmp_get_clock_type(i, &type);
++ if (ret || type != CLK_TYPE_OUTPUT)
++ continue;
++
++ /* Get parents of clock*/
++ if (zynqmp_get_parent_list(np, i, parent_names,
++ &total_parents)) {
++ WARN_ONCE(1, "No parents found for %s\n",
++ clock[i].clk_name);
++ continue;
++ }
++
++ zynqmp_data->hws[i] =
++ zynqmp_register_clk_topology(i, clk_name,
++ total_parents,
++ parent_names);
++ }
++
++ for (i = 0; i < clock_max_idx; i++) {
++ if (IS_ERR(zynqmp_data->hws[i])) {
++ pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n",
++ clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));
++ WARN_ON(1);
++ }
++ }
++ return 0;
++}
++
++/**
++ * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
++ */
++static void zynqmp_get_clock_info(void)
++{
++ int i, ret;
++ u32 attr, type = 0;
++
++ for (i = 0; i < clock_max_idx; i++) {
++ zynqmp_pm_clock_get_name(i, clock[i].clk_name);
++ if (!strcmp(clock[i].clk_name, RESERVED_CLK_NAME))
++ continue;
++
++ ret = zynqmp_pm_clock_get_attributes(i, &attr);
++ if (ret)
++ continue;
++
++ clock[i].valid = attr & CLK_VALID_MASK;
++ clock[i].type = attr >> CLK_TYPE_SHIFT ? CLK_TYPE_EXTERNAL :
++ CLK_TYPE_OUTPUT;
++ }
++
++ /* Get topology of all clock */
++ for (i = 0; i < clock_max_idx; i++) {
++ ret = zynqmp_get_clock_type(i, &type);
++ if (ret || type != CLK_TYPE_OUTPUT)
++ continue;
++
++ ret = zynqmp_clock_get_topology(i, clock[i].node,
++ &clock[i].num_nodes);
++ if (ret)
++ continue;
++
++ ret = zynqmp_clock_get_parents(i, clock[i].parent,
++ &clock[i].num_parents);
++ if (ret)
++ continue;
++ }
++}
++
++/**
++ * zynqmp_clk_setup() - Setup the clock framework and register clocks
++ * @np: Device node
++ *
++ * Return: 0 on success else error code
++ */
++static int zynqmp_clk_setup(struct device_node *np)
++{
++ int ret;
++
++ ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx);
++ if (ret)
++ return ret;
++
++ zynqmp_data = kzalloc(sizeof(*zynqmp_data) + sizeof(*zynqmp_data) *
++ clock_max_idx, GFP_KERNEL);
++ if (!zynqmp_data)
++ return -ENOMEM;
++
++ clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL);
++ if (!clock) {
++ kfree(zynqmp_data);
++ return -ENOMEM;
++ }
++
++ zynqmp_get_clock_info();
++ zynqmp_register_clocks(np);
++
++ zynqmp_data->num = clock_max_idx;
++ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data);
++
++ return 0;
++}
++
++static int zynqmp_clock_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct device *dev = &pdev->dev;
++
++ eemi_ops = zynqmp_pm_get_eemi_ops();
++ if (!eemi_ops)
++ return -ENXIO;
++
++ ret = zynqmp_clk_setup(dev->of_node);
++
++ return ret;
++}
++
++static const struct of_device_id zynqmp_clock_of_match[] = {
++ {.compatible = "xlnx,zynqmp-clk"},
++ {},
++};
++MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
++
++static struct platform_driver zynqmp_clock_driver = {
++ .driver = {
++ .name = "zynqmp_clock",
++ .of_match_table = zynqmp_clock_of_match,
++ },
++ .probe = zynqmp_clock_probe,
++};
++module_platform_driver(zynqmp_clock_driver);
+diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
+new file mode 100644
+index 0000000..a371c66
+--- /dev/null
++++ b/drivers/clk/zynqmp/divider.c
+@@ -0,0 +1,217 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Zynq UltraScale+ MPSoC Divider support
++ *
++ * Copyright (C) 2016-2018 Xilinx
++ *
++ * Adjustable divider clock implementation
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/slab.h>
++#include "clk-zynqmp.h"
++
++/*
++ * DOC: basic adjustable divider clock that cannot gate
++ *
++ * Traits of this clock:
++ * prepare - clk_prepare only ensures that parents are prepared
++ * enable - clk_enable only ensures that parents are enabled
++ * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
++ * parent - fixed parent. No clk_set_parent support
++ */
++
++#define to_zynqmp_clk_divider(_hw) \
++ container_of(_hw, struct zynqmp_clk_divider, hw)
++
++#define CLK_FRAC BIT(13) /* has a fractional parent */
++
++/**
++ * struct zynqmp_clk_divider - adjustable divider clock
++ * @hw: handle between common and hardware-specific interfaces
++ * @flags: Hardware specific flags
++ * @clk_id: Id of clock
++ * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
++ */
++struct zynqmp_clk_divider {
++ struct clk_hw hw;
++ u8 flags;
++ u32 clk_id;
++ u32 div_type;
++};
++
++static inline int zynqmp_divider_get_val(unsigned long parent_rate,
++ unsigned long rate)
++{
++ return DIV_ROUND_CLOSEST(parent_rate, rate);
++}
++
++/**
++ * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
++ * @hw: handle between common and hardware-specific interfaces
++ * @parent_rate: rate of parent clock
++ *
++ * Return: 0 on success else error+reason
++ */
++static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = divider->clk_id;
++ u32 div_type = divider->div_type;
++ u32 div, value;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ ret = eemi_ops->clock_getdivider(clk_id, &div);
++
++ if (ret)
++ pr_warn_once("%s() get divider failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ if (div_type == TYPE_DIV1)
++ value = div & 0xFFFF;
++ else
++ value = div >> 16;
++
++ return DIV_ROUND_UP_ULL(parent_rate, value);
++}
++
++/**
++ * zynqmp_clk_divider_round_rate() - Round rate of divider clock
++ * @hw: handle between common and hardware-specific interfaces
++ * @rate: rate of clock to be set
++ * @prate: rate of parent clock
++ *
++ * Return: 0 on success else error+reason
++ */
++static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
++ unsigned long rate,
++ unsigned long *prate)
++{
++ struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = divider->clk_id;
++ u32 div_type = divider->div_type;
++ u32 bestdiv;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ /* if read only, just return current value */
++ if (divider->flags & CLK_DIVIDER_READ_ONLY) {
++ ret = eemi_ops->clock_getdivider(clk_id, &bestdiv);
++
++ if (ret)
++ pr_warn_once("%s() get divider failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++ if (div_type == TYPE_DIV1)
++ bestdiv = bestdiv & 0xFFFF;
++ else
++ bestdiv = bestdiv >> 16;
++
++ return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
++ }
++
++ bestdiv = zynqmp_divider_get_val(*prate, rate);
++
++ if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) &&
++ (divider->flags & CLK_FRAC))
++ bestdiv = rate % *prate ? 1 : bestdiv;
++ *prate = rate * bestdiv;
++
++ return rate;
++}
++
++/**
++ * zynqmp_clk_divider_set_rate() - Set rate of divider clock
++ * @hw: handle between common and hardware-specific interfaces
++ * @rate: rate of clock to be set
++ * @parent_rate: rate of parent clock
++ *
++ * Return: 0 on success else error+reason
++ */
++static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long parent_rate)
++{
++ struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = divider->clk_id;
++ u32 div_type = divider->div_type;
++ u32 value, div;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ value = zynqmp_divider_get_val(parent_rate, rate);
++ if (div_type == TYPE_DIV1) {
++ div = value & 0xFFFF;
++ div |= 0xffff << 16;
++ } else {
++ div = 0xffff;
++ div |= value << 16;
++ }
++
++ ret = eemi_ops->clock_setdivider(clk_id, div);
++
++ if (ret)
++ pr_warn_once("%s() set divider failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ return ret;
++}
++
++static const struct clk_ops zynqmp_clk_divider_ops = {
++ .recalc_rate = zynqmp_clk_divider_recalc_rate,
++ .round_rate = zynqmp_clk_divider_round_rate,
++ .set_rate = zynqmp_clk_divider_set_rate,
++};
++
++/**
++ * zynqmp_clk_register_divider() - Register a divider clock
++ * @name: Name of this clock
++ * @clk_id: Id of clock
++ * @parents: Name of this clock's parents
++ * @num_parents: Number of parents
++ * @nodes: Clock topology node
++ *
++ * Return: clock hardware to registered clock divider
++ */
++struct clk_hw *zynqmp_clk_register_divider(const char *name,
++ u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes)
++{
++ struct zynqmp_clk_divider *div;
++ struct clk_hw *hw;
++ struct clk_init_data init;
++ int ret;
++
++ /* allocate the divider */
++ div = kzalloc(sizeof(*div), GFP_KERNEL);
++ if (!div)
++ return ERR_PTR(-ENOMEM);
++
++ init.name = name;
++ init.ops = &zynqmp_clk_divider_ops;
++ init.flags = nodes->flag;
++ init.parent_names = parents;
++ init.num_parents = 1;
++
++ /* struct clk_divider assignments */
++ div->flags = nodes->type_flag;
++ div->hw.init = &init;
++ div->clk_id = clk_id;
++ div->div_type = nodes->type;
++
++ hw = &div->hw;
++ ret = clk_hw_register(NULL, hw);
++ if (ret) {
++ kfree(div);
++ hw = ERR_PTR(ret);
++ }
++
++ return hw;
++}
++EXPORT_SYMBOL_GPL(zynqmp_clk_register_divider);
+diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
+new file mode 100644
+index 0000000..626bb5f
+--- /dev/null
++++ b/drivers/clk/zynqmp/pll.c
+@@ -0,0 +1,335 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Zynq UltraScale+ MPSoC PLL driver
++ *
++ * Copyright (C) 2016-2018 Xilinx
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/slab.h>
++#include "clk-zynqmp.h"
++
++/**
++ * struct zynqmp_pll - PLL clock
++ * @hw: Handle between common and hardware-specific interfaces
++ * @clk_id: PLL clock ID
++ */
++struct zynqmp_pll {
++ struct clk_hw hw;
++ u32 clk_id;
++};
++
++#define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
++
++#define PLL_FBDIV_MIN 25
++#define PLL_FBDIV_MAX 125
++
++#define PS_PLL_VCO_MIN 1500000000
++#define PS_PLL_VCO_MAX 3000000000UL
++
++enum pll_mode {
++ PLL_MODE_INT,
++ PLL_MODE_FRAC,
++};
++
++#define FRAC_OFFSET 0x8
++#define PLLFCFG_FRAC_EN BIT(31)
++#define FRAC_DIV BIT(16) /* 2^16 */
++
++/**
++ * zynqmp_pll_get_mode() - Get mode of PLL
++ * @hw: Handle between common and hardware-specific interfaces
++ *
++ * Return: Mode of PLL
++ */
++static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
++{
++ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
++ u32 clk_id = clk->clk_id;
++ const char *clk_name = clk_hw_get_name(hw);
++ __le32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ ret = eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_MODE, clk_id, 0,
++ ret_payload);
++ if (ret)
++ pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ return ret_payload[1];
++}
++
++/**
++ * zynqmp_pll_set_mode() - Set the PLL mode
++ * @hw: Handle between common and hardware-specific interfaces
++ * @on: Flag to determine the mode
++ */
++static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
++{
++ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
++ u32 clk_id = clk->clk_id;
++ const char *clk_name = clk_hw_get_name(hw);
++ int ret;
++ u32 mode;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ if (on)
++ mode = PLL_MODE_FRAC;
++ else
++ mode = PLL_MODE_INT;
++
++ ret = eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode, NULL);
++ if (ret)
++ pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++}
++
++/**
++ * zynqmp_pll_round_rate() - Round a clock frequency
++ * @hw: Handle between common and hardware-specific interfaces
++ * @rate: Desired clock frequency
++ * @prate: Clock frequency of parent clock
++ *
++ * Return: Frequency closest to @rate the hardware can generate
++ */
++static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long *prate)
++{
++ u32 fbdiv;
++ long rate_div, f;
++
++ /* Enable the fractional mode if needed */
++ rate_div = (rate * FRAC_DIV) / *prate;
++ f = rate_div % FRAC_DIV;
++ zynqmp_pll_set_mode(hw, !!f);
++
++ if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
++ if (rate > PS_PLL_VCO_MAX) {
++ fbdiv = rate / PS_PLL_VCO_MAX;
++ rate = rate / (fbdiv + 1);
++ }
++ if (rate < PS_PLL_VCO_MIN) {
++ fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
++ rate = rate * fbdiv;
++ }
++ return rate;
++ }
++
++ fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
++ fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
++ return *prate * fbdiv;
++}
++
++/**
++ * zynqmp_pll_recalc_rate() - Recalculate clock frequency
++ * @hw: Handle between common and hardware-specific interfaces
++ * @parent_rate: Clock frequency of parent clock
++ *
++ * Return: Current clock frequency
++ */
++static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
++ u32 clk_id = clk->clk_id;
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 fbdiv, data;
++ unsigned long rate, frac;
++ __le32 ret_payload[PAYLOAD_ARG_CNT];
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ ret = eemi_ops->clock_getdivider(clk_id, &fbdiv);
++ if (ret)
++ pr_warn_once("%s() get divider failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ rate = parent_rate * fbdiv;
++ if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
++ eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_DATA, clk_id, 0,
++ ret_payload);
++ data = ret_payload[1];
++ frac = (parent_rate * data) / FRAC_DIV;
++ rate = rate + frac;
++ }
++
++ return rate;
++}
++
++/**
++ * zynqmp_pll_set_rate() - Set rate of PLL
++ * @hw: Handle between common and hardware-specific interfaces
++ * @rate: Frequency of clock to be set
++ * @parent_rate: Clock frequency of parent clock
++ *
++ * Set PLL divider to set desired rate.
++ *
++ * Returns: rate which is set on success else error code
++ */
++static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long parent_rate)
++{
++ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
++ u32 clk_id = clk->clk_id;
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 fbdiv;
++ long rate_div, frac, m, f;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
++ rate_div = (rate * FRAC_DIV) / parent_rate;
++ m = rate_div / FRAC_DIV;
++ f = rate_div % FRAC_DIV;
++ m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
++ rate = parent_rate * m;
++ frac = (parent_rate * f) / FRAC_DIV;
++
++ ret = eemi_ops->clock_setdivider(clk_id, m);
++ if (ret)
++ pr_warn_once("%s() set divider failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL);
++
++ return rate + frac;
++ }
++
++ fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
++ fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
++ ret = eemi_ops->clock_setdivider(clk_id, fbdiv);
++ if (ret)
++ pr_warn_once("%s() set divider failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ return parent_rate * fbdiv;
++}
++
++/**
++ * zynqmp_pll_is_enabled() - Check if a clock is enabled
++ * @hw: Handle between common and hardware-specific interfaces
++ *
++ * Return: 1 if the clock is enabled, 0 otherwise
++ */
++static int zynqmp_pll_is_enabled(struct clk_hw *hw)
++{
++ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = clk->clk_id;
++ unsigned int state;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ ret = eemi_ops->clock_getstate(clk_id, &state);
++ if (ret) {
++ pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++ return -EIO;
++ }
++
++ return state ? 1 : 0;
++}
++
++/**
++ * zynqmp_pll_enable() - Enable clock
++ * @hw: Handle between common and hardware-specific interfaces
++ *
++ * Return: 0 on success else error code
++ */
++static int zynqmp_pll_enable(struct clk_hw *hw)
++{
++ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = clk->clk_id;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ if (zynqmp_pll_is_enabled(hw))
++ return 0;
++
++ ret = eemi_ops->clock_enable(clk_id);
++ if (ret)
++ pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++
++ return ret;
++}
++
++/**
++ * zynqmp_pll_disable() - Disable clock
++ * @hw: Handle between common and hardware-specific interfaces
++ */
++static void zynqmp_pll_disable(struct clk_hw *hw)
++{
++ struct zynqmp_pll *clk = to_zynqmp_pll(hw);
++ const char *clk_name = clk_hw_get_name(hw);
++ u32 clk_id = clk->clk_id;
++ int ret;
++ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
++
++ if (!zynqmp_pll_is_enabled(hw))
++ return;
++
++ ret = eemi_ops->clock_disable(clk_id);
++ if (ret)
++ pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
++ __func__, clk_name, ret);
++}
++
++static const struct clk_ops zynqmp_pll_ops = {
++ .enable = zynqmp_pll_enable,
++ .disable = zynqmp_pll_disable,
++ .is_enabled = zynqmp_pll_is_enabled,
++ .round_rate = zynqmp_pll_round_rate,
++ .recalc_rate = zynqmp_pll_recalc_rate,
++ .set_rate = zynqmp_pll_set_rate,
++};
++
++/**
++ * zynqmp_clk_register_pll() - Register PLL with the clock framework
++ * @name: PLL name
++ * @clk_id: Clock ID
++ * @parents: Name of this clock's parents
++ * @num_parents: Number of parents
++ * @nodes: Clock topology node
++ *
++ * Return: clock hardware to the registered clock
++ */
++struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
++ const char * const *parents,
++ u8 num_parents,
++ const struct clock_topology *nodes)
++{
++ struct zynqmp_pll *pll;
++ struct clk_hw *hw;
++ struct clk_init_data init;
++ int ret;
++
++ init.name = name;
++ init.ops = &zynqmp_pll_ops;
++ init.flags = nodes->flag;
++ init.parent_names = parents;
++ init.num_parents = 1;
++
++ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
++ if (!pll)
++ return ERR_PTR(-ENOMEM);
++
++ pll->hw.init = &init;
++ pll->clk_id = clk_id;
++
++ hw = &pll->hw;
++ ret = clk_hw_register(NULL, hw);
++ if (ret) {
++ kfree(pll);
++ return ERR_PTR(ret);
++ }
++
++ clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX);
++ if (ret < 0)
++ pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret);
++
++ return hw;
++}
+diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
+index 58a7478..a3ef7d6 100644
+--- a/include/linux/firmware/xlnx-zynqmp.h
++++ b/include/linux/firmware/xlnx-zynqmp.h
+@@ -72,6 +72,7 @@ enum pm_query_id {
+ PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
+ PM_QID_CLOCK_GET_PARENTS,
+ PM_QID_CLOCK_GET_ATTRIBUTES,
++ PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
+ };
+
+ /**
+
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+Subject: [PATCH v11 11/11] firmware: xilinx: Replace init call with probe
+ method
+Date: Fri, 3 Aug 2018 10:53:28 -0700
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+Cc: devicetree@vger.kernel.org, Rajan Vaja <rajan.vaja@xilinx.com>,
+ linux-kernel@vger.kernel.org, Jolly Shah <jollys@xilinx.com>,
+ rajanv@xilinx.com, linux-arm-kernel@lists.infradead.org
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+From: Rajan Vaja <rajan.vaja@xilinx.com>
+
+As of all of child of ZynqMP firmware are platform
+driver, there is no need of init call in firmware
+driver. Earlier clock driver was init method so
+firmware driver had to use init call to make sure
+firmware init is done in early stage.
+
+Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
+Signed-off-by: Jolly Shah <jollys@xilinx.com>
+---
+ drivers/firmware/xilinx/zynqmp.c | 63 ++++++++++++----------------------------
+ 1 file changed, 18 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
+index 7ccedf0..ce6c746 100644
+--- a/drivers/firmware/xilinx/zynqmp.c
++++ b/drivers/firmware/xilinx/zynqmp.c
+@@ -476,50 +476,17 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_get_eemi_ops);
+ static int zynqmp_firmware_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+-
+- return of_platform_populate(dev->of_node, NULL, NULL, dev);
+-}
+-
+-static const struct of_device_id zynqmp_firmware_of_match[] = {
+- {.compatible = "xlnx,zynqmp-firmware"},
+- {},
+-};
+-MODULE_DEVICE_TABLE(of, zynqmp_firmware_of_match);
+-
+-static struct platform_driver zynqmp_firmware_driver = {
+- .driver = {
+- .name = "zynqmp_firmware",
+- .of_match_table = zynqmp_firmware_of_match,
+- },
+- .probe = zynqmp_firmware_probe,
+-};
+-module_platform_driver(zynqmp_firmware_driver);
+-
+-static int __init zynqmp_plat_init(void)
+-{
+- int ret;
+ struct device_node *np;
++ int ret;
+
+ np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp");
+ if (!np)
+ return 0;
+ of_node_put(np);
+
+- /*
+- * We're running on a ZynqMP machine,
+- * the zynqmp-firmware node is mandatory.
+- */
+- np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp-firmware");
+- if (!np) {
+- pr_warn("%s: zynqmp-firmware node not found\n", __func__);
+- return -ENXIO;
+- }
+-
+- ret = get_set_conduit_method(np);
+- if (ret) {
+- of_node_put(np);
++ ret = get_set_conduit_method(dev->of_node);
++ if (ret)
+ return ret;
+- }
+
+ /* Check PM API version number */
+ zynqmp_pm_get_api_version(&pm_api_version);
+@@ -547,16 +514,22 @@ static int __init zynqmp_plat_init(void)
+ pr_info("%s Trustzone version v%d.%d\n", __func__,
+ pm_tz_version >> 16, pm_tz_version & 0xFFFF);
+
+- of_node_put(np);
++ zynqmp_pm_api_debugfs_init();
+
+- return ret;
++ return of_platform_populate(dev->of_node, NULL, NULL, dev);
+ }
+-early_initcall(zynqmp_plat_init);
+
+-static int zynqmp_firmware_init(void)
+-{
+- zynqmp_pm_api_debugfs_init();
++static const struct of_device_id zynqmp_firmware_of_match[] = {
++ {.compatible = "xlnx,zynqmp-firmware"},
++ {},
++};
++MODULE_DEVICE_TABLE(of, zynqmp_firmware_of_match);
+
+- return 0;
+-}
+-device_initcall(zynqmp_firmware_init);
++static struct platform_driver zynqmp_firmware_driver = {
++ .driver = {
++ .name = "zynqmp_firmware",
++ .of_match_table = zynqmp_firmware_of_match,
++ },
++ .probe = zynqmp_firmware_probe,
++};
++module_platform_driver(zynqmp_firmware_driver);
diff --git a/kernel-aarch64-debug.config b/kernel-aarch64-debug.config
index 0c585e7d4..e95986700 100644
--- a/kernel-aarch64-debug.config
+++ b/kernel-aarch64-debug.config
@@ -981,6 +981,7 @@ CONFIG_COMMON_CLK_VERSATILE=y
CONFIG_COMMON_CLK_XGENE=y
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_ZYNQMP=y
# CONFIG_COMMON_RESET_HI3660 is not set
CONFIG_COMMON_RESET_HI6220=m
CONFIG_COMPACTION=y
@@ -7039,3 +7040,5 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
+CONFIG_ZYNQMP_FIRMWARE=y
diff --git a/kernel-aarch64.config b/kernel-aarch64.config
index 5802d5cf5..7d2dc0a51 100644
--- a/kernel-aarch64.config
+++ b/kernel-aarch64.config
@@ -981,6 +981,7 @@ CONFIG_COMMON_CLK_VERSATILE=y
CONFIG_COMMON_CLK_XGENE=y
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_ZYNQMP=y
# CONFIG_COMMON_RESET_HI3660 is not set
CONFIG_COMMON_RESET_HI6220=m
CONFIG_COMPACTION=y
@@ -7015,3 +7016,5 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
+CONFIG_ZYNQMP_FIRMWARE=y
diff --git a/kernel-armv7hl-debug.config b/kernel-armv7hl-debug.config
index 9e832253f..4acdb1f13 100644
--- a/kernel-armv7hl-debug.config
+++ b/kernel-armv7hl-debug.config
@@ -7554,3 +7554,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-armv7hl-lpae-debug.config b/kernel-armv7hl-lpae-debug.config
index f0b684a0c..3d9711adc 100644
--- a/kernel-armv7hl-lpae-debug.config
+++ b/kernel-armv7hl-lpae-debug.config
@@ -7097,3 +7097,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-armv7hl-lpae.config b/kernel-armv7hl-lpae.config
index 1a8ac0cae..edf99a84b 100644
--- a/kernel-armv7hl-lpae.config
+++ b/kernel-armv7hl-lpae.config
@@ -7073,3 +7073,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-armv7hl.config b/kernel-armv7hl.config
index c80c4393b..b4aa65102 100644
--- a/kernel-armv7hl.config
+++ b/kernel-armv7hl.config
@@ -7530,3 +7530,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-i686-PAE.config b/kernel-i686-PAE.config
index 9e96cd3ac..0834591e7 100644
--- a/kernel-i686-PAE.config
+++ b/kernel-i686-PAE.config
@@ -6651,3 +6651,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-i686-PAEdebug.config b/kernel-i686-PAEdebug.config
index 2b22355ec..fab02ee69 100644
--- a/kernel-i686-PAEdebug.config
+++ b/kernel-i686-PAEdebug.config
@@ -6676,3 +6676,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-i686-debug.config b/kernel-i686-debug.config
index fd3786b0f..8ee08e686 100644
--- a/kernel-i686-debug.config
+++ b/kernel-i686-debug.config
@@ -6674,3 +6674,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-i686.config b/kernel-i686.config
index 670a960fb..8f387bbb1 100644
--- a/kernel-i686.config
+++ b/kernel-i686.config
@@ -6649,3 +6649,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-ppc64-debug.config b/kernel-ppc64-debug.config
index b101d8582..32835ba70 100644
--- a/kernel-ppc64-debug.config
+++ b/kernel-ppc64-debug.config
@@ -6349,3 +6349,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-ppc64.config b/kernel-ppc64.config
index fb39a1db3..f162ac6df 100644
--- a/kernel-ppc64.config
+++ b/kernel-ppc64.config
@@ -6322,3 +6322,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-ppc64le-debug.config b/kernel-ppc64le-debug.config
index c0e1ad35e..8d5a8d6db 100644
--- a/kernel-ppc64le-debug.config
+++ b/kernel-ppc64le-debug.config
@@ -6270,3 +6270,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-ppc64le.config b/kernel-ppc64le.config
index b72e87b7f..5b281a436 100644
--- a/kernel-ppc64le.config
+++ b/kernel-ppc64le.config
@@ -6243,3 +6243,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-s390x-debug.config b/kernel-s390x-debug.config
index c1d6380b3..4f8f333e2 100644
--- a/kernel-s390x-debug.config
+++ b/kernel-s390x-debug.config
@@ -6155,3 +6155,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-s390x.config b/kernel-s390x.config
index 61e9337ca..e68f395e5 100644
--- a/kernel-s390x.config
+++ b/kernel-s390x.config
@@ -6128,3 +6128,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-x86_64-debug.config b/kernel-x86_64-debug.config
index b3bf89720..b8298162a 100644
--- a/kernel-x86_64-debug.config
+++ b/kernel-x86_64-debug.config
@@ -6760,3 +6760,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel-x86_64.config b/kernel-x86_64.config
index 9dc79279a..cf9c26888 100644
--- a/kernel-x86_64.config
+++ b/kernel-x86_64.config
@@ -6735,3 +6735,4 @@ CONFIG_ZRAM=m
CONFIG_ZSMALLOC=y
CONFIG_ZSWAP=y
# CONFIG_ZX_TDM is not set
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
diff --git a/kernel.spec b/kernel.spec
index 0aa0448c1..6d8ecefa5 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -595,6 +595,9 @@ Patch309: mmc-sunxi-remove-output-of-virtual-base-address.patch
Patch310: arm-dts-armada388-helios4.patch
+# https://www.spinics.net/lists/arm-kernel/msg670137.html
+Patch311: arm64-ZynqMP-firmware-clock-drivers-core.patch
+
# Enabling Patches for the RPi3+
Patch330: bcm2837-enable-pmu.patch
@@ -1907,6 +1910,9 @@ fi
#
#
%changelog
+* Sat Aug 11 2018 Peter Robinson <pbrobinson@fedoraproject.org>
+- Add ZYNQMP clock and firmware driver
+
* Fri Aug 10 2018 Laura Abbott <labbott@redhat.com> - 4.18.0-0.rc8.git2.1
- Linux v4.18-rc8-4-gfedb8da96355