Fixes for Tegra Jetson TX series, Initial support for NVIDIA Jetson Nano

3 files changed, 2150 insertions, 0 deletions

diff --git a/arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch b/arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch
new file mode 100644
index 000000000..a1a67acb7
--- /dev/null
+++ b/arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch
@@ -0,0 +1,2072 @@
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+From: Thierry Reding <thierry.reding@gmail.com>
+To: Thierry Reding <thierry.reding@gmail.com>
+Subject: [PATCH] arm64: tegra: Add NVIDIA Jetson Nano Developer Kit support
+Date: Tue, 19 Mar 2019 00:23:13 +0100
+Message-Id: <20190318232313.24270-1-thierry.reding@gmail.com>
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+Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ Jonathan Hunter <jonathanh@nvidia.com>
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+From: Thierry Reding <treding@nvidia.com>
+
+The Jetson Nano Developer Kit is a Tegra X1 based development board. It
+is similar to Jetson TX1 but it is not pin compatible. It features 4 GB
+of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot
+used for storage.
+
+HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
+and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
+Ethernet controller provides onboard network connectivity.
+
+A 40-pin header on the board can be used to extend the capabilities and
+exposed interfaces of the Jetson Nano.
+
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+---
+This patch, along with some related patches can be found in the p3450
+branch in the following repository:
+
+	https://github.com/thierryreding/linux
+
+ arch/arm64/boot/dts/nvidia/Makefile           |    1 +
+ .../boot/dts/nvidia/tegra210-p3450-0000.dts   | 1911 +++++++++++++++++
+ 2 files changed, 1912 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+
+diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
+index 6b8ab5568481..bcd018c3162b 100644
+--- a/arch/arm64/boot/dts/nvidia/Makefile
++++ b/arch/arm64/boot/dts/nvidia/Makefile
+@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
+ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
+ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
+ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
++dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb
+ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
+ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb
+ dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+new file mode 100644
+index 000000000000..b1d8a49ca8c4
+--- /dev/null
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+@@ -0,0 +1,1911 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++
++#include <dt-bindings/input/gpio-keys.h>
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/mfd/max77620.h>
++
++#include "tegra210.dtsi"
++
++/ {
++	model = "NVIDIA Jetson Nano Developer Kit";
++	compatible = "nvidia,p3450-0000", "nvidia,tegra210";
++
++	aliases {
++		ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
++		rtc0 = "/i2c@7000d000/pmic@3c";
++		rtc1 = "/rtc@7000e000";
++		serial0 = &uarta;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x0 0x80000000 0x1 0x0>;
++	};
++
++	pcie@1003000 {
++		status = "okay";
++
++		hvddio-pex-supply = <&vdd_1v8>;
++		dvddio-pex-supply = <&vdd_pex_1v05>;
++		vddio-pex-ctl-supply = <&vdd_1v8>;
++
++		pci@1,0 {
++			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
++			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
++			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
++			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
++			phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
++			nvidia,num-lanes = <4>;
++			status = "okay";
++		};
++
++		pci@2,0 {
++			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
++			phy-names = "pcie-0";
++			status = "okay";
++
++			ethernet@0,0 {
++				reg = <0x000000 0 0 0 0>;
++				mac-address = [ 00 00 00 00 00 00 ];
++			};
++		};
++	};
++
++	host1x@50000000 {
++		dpaux@54040000 {
++			status = "okay";
++		};
++
++		sor@54580000 {
++			status = "okay";
++
++			avdd-io-supply = <&avdd_1v05>;
++			vdd-pll-supply = <&vdd_1v8>;
++			hdmi-supply = <&vdd_hdmi>;
++
++			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
++			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
++					   GPIO_ACTIVE_LOW>;
++			nvidia,xbar-cfg = <0 1 2 3 4>;
++		};
++	};
++
++	gpu@57000000 {
++		vdd-supply = <&vdd_gpu>;
++		status = "okay";
++	};
++
++	pinmux: pinmux@700008d4 {
++		pinctrl-names = "boot";
++		pinctrl-0 = <&state_boot>;
++
++		state_boot: pinmux {
++			pex_l0_rst_n_pa0 {
++				nvidia,pins = "pex_l0_rst_n_pa0";
++				nvidia,function = "pe0";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			pex_l0_clkreq_n_pa1 {
++				nvidia,pins = "pex_l0_clkreq_n_pa1";
++				nvidia,function = "pe0";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			pex_wake_n_pa2 {
++				nvidia,pins = "pex_wake_n_pa2";
++				nvidia,function = "pe";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			pex_l1_rst_n_pa3 {
++				nvidia,pins = "pex_l1_rst_n_pa3";
++				nvidia,function = "pe1";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			pex_l1_clkreq_n_pa4 {
++				nvidia,pins = "pex_l1_clkreq_n_pa4";
++				nvidia,function = "pe1";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			sata_led_active_pa5 {
++				nvidia,pins = "sata_led_active_pa5";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pa6 {
++				nvidia,pins = "pa6";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap1_fs_pb0 {
++				nvidia,pins = "dap1_fs_pb0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap1_din_pb1 {
++				nvidia,pins = "dap1_din_pb1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap1_dout_pb2 {
++				nvidia,pins = "dap1_dout_pb2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap1_sclk_pb3 {
++				nvidia,pins = "dap1_sclk_pb3";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi2_mosi_pb4 {
++				nvidia,pins = "spi2_mosi_pb4";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi2_miso_pb5 {
++				nvidia,pins = "spi2_miso_pb5";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi2_sck_pb6 {
++				nvidia,pins = "spi2_sck_pb6";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi2_cs0_pb7 {
++				nvidia,pins = "spi2_cs0_pb7";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi1_mosi_pc0 {
++				nvidia,pins = "spi1_mosi_pc0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi1_miso_pc1 {
++				nvidia,pins = "spi1_miso_pc1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi1_sck_pc2 {
++				nvidia,pins = "spi1_sck_pc2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi1_cs0_pc3 {
++				nvidia,pins = "spi1_cs0_pc3";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi1_cs1_pc4 {
++				nvidia,pins = "spi1_cs1_pc4";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi4_sck_pc5 {
++				nvidia,pins = "spi4_sck_pc5";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi4_cs0_pc6 {
++				nvidia,pins = "spi4_cs0_pc6";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi4_mosi_pc7 {
++				nvidia,pins = "spi4_mosi_pc7";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spi4_miso_pd0 {
++				nvidia,pins = "spi4_miso_pd0";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart3_tx_pd1 {
++				nvidia,pins = "uart3_tx_pd1";
++				nvidia,function = "uartc";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart3_rx_pd2 {
++				nvidia,pins = "uart3_rx_pd2";
++				nvidia,function = "uartc";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart3_rts_pd3 {
++				nvidia,pins = "uart3_rts_pd3";
++				nvidia,function = "uartc";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart3_cts_pd4 {
++				nvidia,pins = "uart3_cts_pd4";
++				nvidia,function = "uartc";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dmic1_clk_pe0 {
++				nvidia,pins = "dmic1_clk_pe0";
++				nvidia,function = "i2s3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dmic1_dat_pe1 {
++				nvidia,pins = "dmic1_dat_pe1";
++				nvidia,function = "i2s3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dmic2_clk_pe2 {
++				nvidia,pins = "dmic2_clk_pe2";
++				nvidia,function = "i2s3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dmic2_dat_pe3 {
++				nvidia,pins = "dmic2_dat_pe3";
++				nvidia,function = "i2s3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dmic3_clk_pe4 {
++				nvidia,pins = "dmic3_clk_pe4";
++				nvidia,function = "rsvd2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dmic3_dat_pe5 {
++				nvidia,pins = "dmic3_dat_pe5";
++				nvidia,function = "rsvd2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pe6 {
++				nvidia,pins = "pe6";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pe7 {
++				nvidia,pins = "pe7";
++				nvidia,function = "pwm3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			gen3_i2c_scl_pf0 {
++				nvidia,pins = "gen3_i2c_scl_pf0";
++				nvidia,function = "i2c3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			gen3_i2c_sda_pf1 {
++				nvidia,pins = "gen3_i2c_sda_pf1";
++				nvidia,function = "i2c3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			uart2_tx_pg0 {
++				nvidia,pins = "uart2_tx_pg0";
++				nvidia,function = "uartb";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart2_rx_pg1 {
++				nvidia,pins = "uart2_rx_pg1";
++				nvidia,function = "uartb";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart2_rts_pg2 {
++				nvidia,pins = "uart2_rts_pg2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart2_cts_pg3 {
++				nvidia,pins = "uart2_cts_pg3";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			wifi_en_ph0 {
++				nvidia,pins = "wifi_en_ph0";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			wifi_rst_ph1 {
++				nvidia,pins = "wifi_rst_ph1";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			wifi_wake_ap_ph2 {
++				nvidia,pins = "wifi_wake_ap_ph2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			ap_wake_bt_ph3 {
++				nvidia,pins = "ap_wake_bt_ph3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			bt_rst_ph4 {
++				nvidia,pins = "bt_rst_ph4";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			bt_wake_ap_ph5 {
++				nvidia,pins = "bt_wake_ap_ph5";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			ph6 {
++				nvidia,pins = "ph6";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			ap_wake_nfc_ph7 {
++				nvidia,pins = "ap_wake_nfc_ph7";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			nfc_en_pi0 {
++				nvidia,pins = "nfc_en_pi0";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			nfc_int_pi1 {
++				nvidia,pins = "nfc_int_pi1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			gps_en_pi2 {
++				nvidia,pins = "gps_en_pi2";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			gps_rst_pi3 {
++				nvidia,pins = "gps_rst_pi3";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart4_tx_pi4 {
++				nvidia,pins = "uart4_tx_pi4";
++				nvidia,function = "uartd";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart4_rx_pi5 {
++				nvidia,pins = "uart4_rx_pi5";
++				nvidia,function = "uartd";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart4_rts_pi6 {
++				nvidia,pins = "uart4_rts_pi6";
++				nvidia,function = "uartd";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart4_cts_pi7 {
++				nvidia,pins = "uart4_cts_pi7";
++				nvidia,function = "uartd";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			gen1_i2c_sda_pj0 {
++				nvidia,pins = "gen1_i2c_sda_pj0";
++				nvidia,function = "i2c1";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
++			};
++			gen1_i2c_scl_pj1 {
++				nvidia,pins = "gen1_i2c_scl_pj1";
++				nvidia,function = "i2c1";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
++			};
++			gen2_i2c_scl_pj2 {
++				nvidia,pins = "gen2_i2c_scl_pj2";
++				nvidia,function = "i2c2";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
++			};
++			gen2_i2c_sda_pj3 {
++				nvidia,pins = "gen2_i2c_sda_pj3";
++				nvidia,function = "i2c2";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
++			};
++			dap4_fs_pj4 {
++				nvidia,pins = "dap4_fs_pj4";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap4_din_pj5 {
++				nvidia,pins = "dap4_din_pj5";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap4_dout_pj6 {
++				nvidia,pins = "dap4_dout_pj6";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap4_sclk_pj7 {
++				nvidia,pins = "dap4_sclk_pj7";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pk0 {
++				nvidia,pins = "pk0";
++				nvidia,function = "rsvd2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pk1 {
++				nvidia,pins = "pk1";
++				nvidia,function = "rsvd2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pk2 {
++				nvidia,pins = "pk2";
++				nvidia,function = "rsvd2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pk3 {
++				nvidia,pins = "pk3";
++				nvidia,function = "rsvd2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pk4 {
++				nvidia,pins = "pk4";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pk5 {
++				nvidia,pins = "pk5";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pk6 {
++				nvidia,pins = "pk6";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pk7 {
++				nvidia,pins = "pk7";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pl0 {
++				nvidia,pins = "pl0";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pl1 {
++				nvidia,pins = "pl1";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc1_clk_pm0 {
++				nvidia,pins = "sdmmc1_clk_pm0";
++				nvidia,function = "sdmmc1";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc1_cmd_pm1 {
++				nvidia,pins = "sdmmc1_cmd_pm1";
++				nvidia,function = "sdmmc1";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc1_dat3_pm2 {
++				nvidia,pins = "sdmmc1_dat3_pm2";
++				nvidia,function = "sdmmc1";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc1_dat2_pm3 {
++				nvidia,pins = "sdmmc1_dat2_pm3";
++				nvidia,function = "sdmmc1";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc1_dat1_pm4 {
++				nvidia,pins = "sdmmc1_dat1_pm4";
++				nvidia,function = "sdmmc1";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc1_dat0_pm5 {
++				nvidia,pins = "sdmmc1_dat0_pm5";
++				nvidia,function = "sdmmc1";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc3_clk_pp0 {
++				nvidia,pins = "sdmmc3_clk_pp0";
++				nvidia,function = "sdmmc3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc3_cmd_pp1 {
++				nvidia,pins = "sdmmc3_cmd_pp1";
++				nvidia,function = "sdmmc3";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc3_dat3_pp2 {
++				nvidia,pins = "sdmmc3_dat3_pp2";
++				nvidia,function = "sdmmc3";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc3_dat2_pp3 {
++				nvidia,pins = "sdmmc3_dat2_pp3";
++				nvidia,function = "sdmmc3";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc3_dat1_pp4 {
++				nvidia,pins = "sdmmc3_dat1_pp4";
++				nvidia,function = "sdmmc3";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			sdmmc3_dat0_pp5 {
++				nvidia,pins = "sdmmc3_dat0_pp5";
++				nvidia,function = "sdmmc3";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			cam1_mclk_ps0 {
++				nvidia,pins = "cam1_mclk_ps0";
++				nvidia,function = "extperiph3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			cam2_mclk_ps1 {
++				nvidia,pins = "cam2_mclk_ps1";
++				nvidia,function = "extperiph3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			cam_i2c_scl_ps2 {
++				nvidia,pins = "cam_i2c_scl_ps2";
++				nvidia,function = "i2cvi";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
++			};
++			cam_i2c_sda_ps3 {
++				nvidia,pins = "cam_i2c_sda_ps3";
++				nvidia,function = "i2cvi";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
++			};
++			cam_rst_ps4 {
++				nvidia,pins = "cam_rst_ps4";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			cam_af_en_ps5 {
++				nvidia,pins = "cam_af_en_ps5";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			cam_flash_en_ps6 {
++				nvidia,pins = "cam_flash_en_ps6";
++				nvidia,function = "rsvd2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			cam1_pwdn_ps7 {
++				nvidia,pins = "cam1_pwdn_ps7";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			cam2_pwdn_pt0 {
++				nvidia,pins = "cam2_pwdn_pt0";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			cam1_strobe_pt1 {
++				nvidia,pins = "cam1_strobe_pt1";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart1_tx_pu0 {
++				nvidia,pins = "uart1_tx_pu0";
++				nvidia,function = "uarta";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart1_rx_pu1 {
++				nvidia,pins = "uart1_rx_pu1";
++				nvidia,function = "uarta";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart1_rts_pu2 {
++				nvidia,pins = "uart1_rts_pu2";
++				nvidia,function = "uarta";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			uart1_cts_pu3 {
++				nvidia,pins = "uart1_cts_pu3";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			lcd_bl_pwm_pv0 {
++				nvidia,pins = "lcd_bl_pwm_pv0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			lcd_bl_en_pv1 {
++				nvidia,pins = "lcd_bl_en_pv1";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			lcd_rst_pv2 {
++				nvidia,pins = "lcd_rst_pv2";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			lcd_gpio1_pv3 {
++				nvidia,pins = "lcd_gpio1_pv3";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			lcd_gpio2_pv4 {
++				nvidia,pins = "lcd_gpio2_pv4";
++				nvidia,function = "pwm1";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			ap_ready_pv5 {
++				nvidia,pins = "ap_ready_pv5";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			touch_rst_pv6 {
++				nvidia,pins = "touch_rst_pv6";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			touch_clk_pv7 {
++				nvidia,pins = "touch_clk_pv7";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			modem_wake_ap_px0 {
++				nvidia,pins = "modem_wake_ap_px0";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			touch_int_px1 {
++				nvidia,pins = "touch_int_px1";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			motion_int_px2 {
++				nvidia,pins = "motion_int_px2";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			als_prox_int_px3 {
++				nvidia,pins = "als_prox_int_px3";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			temp_alert_px4 {
++				nvidia,pins = "temp_alert_px4";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			button_power_on_px5 {
++				nvidia,pins = "button_power_on_px5";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			button_vol_up_px6 {
++				nvidia,pins = "button_vol_up_px6";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			button_vol_down_px7 {
++				nvidia,pins = "button_vol_down_px7";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			button_slide_sw_py0 {
++				nvidia,pins = "button_slide_sw_py0";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			button_home_py1 {
++				nvidia,pins = "button_home_py1";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			lcd_te_py2 {
++				nvidia,pins = "lcd_te_py2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pwr_i2c_scl_py3 {
++				nvidia,pins = "pwr_i2c_scl_py3";
++				nvidia,function = "i2cpmu";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			pwr_i2c_sda_py4 {
++				nvidia,pins = "pwr_i2c_sda_py4";
++				nvidia,function = "i2cpmu";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			clk_32k_out_py5 {
++				nvidia,pins = "clk_32k_out_py5";
++				nvidia,function = "rsvd2";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pz0 {
++				nvidia,pins = "pz0";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pz1 {
++				nvidia,pins = "pz1";
++				nvidia,function = "sdmmc1";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pz2 {
++				nvidia,pins = "pz2";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pz3 {
++				nvidia,pins = "pz3";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pz4 {
++				nvidia,pins = "pz4";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pz5 {
++				nvidia,pins = "pz5";
++				nvidia,function = "soc";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap2_fs_paa0 {
++				nvidia,pins = "dap2_fs_paa0";
++				nvidia,function = "i2s2";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap2_sclk_paa1 {
++				nvidia,pins = "dap2_sclk_paa1";
++				nvidia,function = "i2s2";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap2_din_paa2 {
++				nvidia,pins = "dap2_din_paa2";
++				nvidia,function = "i2s2";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dap2_dout_paa3 {
++				nvidia,pins = "dap2_dout_paa3";
++				nvidia,function = "i2s2";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			aud_mclk_pbb0 {
++				nvidia,pins = "aud_mclk_pbb0";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dvfs_pwm_pbb1 {
++				nvidia,pins = "dvfs_pwm_pbb1";
++				nvidia,function = "cldvfs";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			dvfs_clk_pbb2 {
++				nvidia,pins = "dvfs_clk_pbb2";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			gpio_x1_aud_pbb3 {
++				nvidia,pins = "gpio_x1_aud_pbb3";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			gpio_x3_aud_pbb4 {
++				nvidia,pins = "gpio_x3_aud_pbb4";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			hdmi_cec_pcc0 {
++				nvidia,pins = "hdmi_cec_pcc0";
++				nvidia,function = "cec";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
++			};
++			hdmi_int_dp_hpd_pcc1 {
++				nvidia,pins = "hdmi_int_dp_hpd_pcc1";
++				nvidia,function = "dp";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			spdif_out_pcc2 {
++				nvidia,pins = "spdif_out_pcc2";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			spdif_in_pcc3 {
++				nvidia,pins = "spdif_in_pcc3";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			usb_vbus_en0_pcc4 {
++				nvidia,pins = "usb_vbus_en0_pcc4";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			usb_vbus_en1_pcc5 {
++				nvidia,pins = "usb_vbus_en1_pcc5";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			dp_hpd0_pcc6 {
++				nvidia,pins = "dp_hpd0_pcc6";
++				nvidia,function = "dp";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pcc7 {
++				nvidia,pins = "pcc7";
++				nvidia,function = "rsvd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
++			};
++			spi2_cs1_pdd0 {
++				nvidia,pins = "spi2_cs1_pdd0";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			qspi_sck_pee0 {
++				nvidia,pins = "qspi_sck_pee0";
++				nvidia,function = "qspi";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			qspi_cs_n_pee1 {
++				nvidia,pins = "qspi_cs_n_pee1";
++				nvidia,function = "qspi";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			qspi_io0_pee2 {
++				nvidia,pins = "qspi_io0_pee2";
++				nvidia,function = "qspi";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			qspi_io1_pee3 {
++				nvidia,pins = "qspi_io1_pee3";
++				nvidia,function = "qspi";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			qspi_io2_pee4 {
++				nvidia,pins = "qspi_io2_pee4";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			qspi_io3_pee5 {
++				nvidia,pins = "qspi_io3_pee5";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			core_pwr_req {
++				nvidia,pins = "core_pwr_req";
++				nvidia,function = "core";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			cpu_pwr_req {
++				nvidia,pins = "cpu_pwr_req";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			pwr_int_n {
++				nvidia,pins = "pwr_int_n";
++				nvidia,function = "pmi";
++				nvidia,pull = <TEGRA_PIN_PULL_UP>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			clk_32k_in {
++				nvidia,pins = "clk_32k_in";
++				nvidia,function = "clk";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			jtag_rtck {
++				nvidia,pins = "jtag_rtck";
++				nvidia,function = "jtag";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			clk_req {
++				nvidia,pins = "clk_req";
++				nvidia,function = "rsvd1";
++				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
++				nvidia,tristate = <TEGRA_PIN_ENABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++			shutdown {
++				nvidia,pins = "shutdown";
++				nvidia,function = "shutdown";
++				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
++				nvidia,tristate = <TEGRA_PIN_DISABLE>;
++				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
++				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
++			};
++		};
++	};
++
++	/* debug port */
++	serial@70006000 {
++		status = "okay";
++	};
++
++	hdmi_ddc: i2c@7000c700 {
++		status = "okay";
++		clock-frequency = <100000>;
++	};
++
++	i2c@7000d000 {
++		status = "okay";
++		clock-frequency = <400000>;
++
++		pmic: pmic@3c {
++			compatible = "maxim,max77620";
++			reg = <0x3c>;
++			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++
++			#interrupt-cells = <2>;
++			interrupt-controller;
++
++			#gpio-cells = <2>;
++			gpio-controller;
++
++			pinctrl-names = "default";
++			pinctrl-0 = <&max77620_default>;
++
++			max77620_default: pinmux {
++				gpio0 {
++					pins = "gpio0";
++					function = "gpio";
++				};
++
++				gpio1 {
++					pins = "gpio1";
++					function = "fps-out";
++					drive-push-pull = <1>;
++					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
++					maxim,active-fps-power-up-slot = <0>;
++					maxim,active-fps-power-down-slot = <7>;
++				};
++
++				gpio2 {
++					pins = "gpio2";
++					function = "fps-out";
++					drive-open-drain = <1>;
++					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++					maxim,active-fps-power-up-slot = <0>;
++					maxim,active-fps-power-down-slot = <7>;
++				};
++
++				gpio3 {
++					pins = "gpio3";
++					function = "fps-out";
++					drive-open-drain = <1>;
++					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++					maxim,active-fps-power-up-slot = <4>;
++					maxim,active-fps-power-down-slot = <3>;
++				};
++
++				gpio4 {
++					pins = "gpio4";
++					function = "32k-out1";
++				};
++
++				gpio5_6_7 {
++					pins = "gpio5", "gpio6", "gpio7";
++					function = "gpio";
++					drive-push-pull = <1>;
++				};
++			};
++
++			fps {
++				fps0 {
++					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
++					maxim,suspend-fps-time-period-us = <5120>;
++				};
++
++				fps1 {
++					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
++					maxim,suspend-fps-time-period-us = <5120>;
++				};
++
++				fps2 {
++					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
++				};
++			};
++
++			regulators {
++				in-ldo0-1-supply = <&vdd_pre>;
++				in-ldo2-supply = <&vdd_3v3_sys>;
++				in-ldo3-5-supply = <&vdd_1v8>;
++				in-ldo4-6-supply = <&vdd_5v0_sys>;
++				in-ldo7-8-supply = <&vdd_pre>;
++				in-sd0-supply = <&vdd_5v0_sys>;
++				in-sd1-supply = <&vdd_5v0_sys>;
++				in-sd2-supply = <&vdd_5v0_sys>;
++				in-sd3-supply = <&vdd_5v0_sys>;
++
++				vdd_soc: sd0 {
++					regulator-name = "VDD_SOC";
++					regulator-min-microvolt = <1000000>;
++					regulator-max-microvolt = <1170000>;
++					regulator-enable-ramp-delay = <146>;
++					regulator-disable-ramp-delay = <4080>;
++					regulator-ramp-delay = <27500>;
++					regulator-ramp-delay-scale = <300>;
++					regulator-always-on;
++					regulator-boot-on;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
++					maxim,active-fps-power-up-slot = <1>;
++					maxim,active-fps-power-down-slot = <6>;
++				};
++
++				vdd_ddr: sd1 {
++					regulator-name = "VDD_DDR_1V1_PMIC";
++					regulator-min-microvolt = <1150000>;
++					regulator-max-microvolt = <1150000>;
++					regulator-enable-ramp-delay = <176>;
++					regulator-disable-ramp-delay = <145800>;
++					regulator-ramp-delay = <27500>;
++					regulator-ramp-delay-scale = <300>;
++					regulator-always-on;
++					regulator-boot-on;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++					maxim,active-fps-power-up-slot = <5>;
++					maxim,active-fps-power-down-slot = <2>;
++				};
++
++				vdd_pre: sd2 {
++					regulator-name = "VDD_PRE_REG_1V35";
++					regulator-min-microvolt = <1350000>;
++					regulator-max-microvolt = <1350000>;
++					regulator-enable-ramp-delay = <176>;
++					regulator-disable-ramp-delay = <32000>;
++					regulator-ramp-delay = <27500>;
++					regulator-ramp-delay-scale = <350>;
++					regulator-always-on;
++					regulator-boot-on;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
++					maxim,active-fps-power-up-slot = <2>;
++					maxim,active-fps-power-down-slot = <5>;
++				};
++
++				vdd_1v8: sd3 {
++					regulator-name = "VDD_1V8";
++					regulator-min-microvolt = <1800000>;
++					regulator-max-microvolt = <1800000>;
++					regulator-enable-ramp-delay = <242>;
++					regulator-disable-ramp-delay = <118000>;
++					regulator-ramp-delay = <27500>;
++					regulator-ramp-delay-scale = <360>;
++					regulator-always-on;
++					regulator-boot-on;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++					maxim,active-fps-power-up-slot = <3>;
++					maxim,active-fps-power-down-slot = <4>;
++				};
++
++				vdd_sys_1v2: ldo0 {
++					regulator-name = "AVDD_SYS_1V2";
++					regulator-min-microvolt = <1200000>;
++					regulator-max-microvolt = <1200000>;
++					regulator-enable-ramp-delay = <26>;
++					regulator-disable-ramp-delay = <626>;
++					regulator-ramp-delay = <100000>;
++					regulator-ramp-delay-scale = <200>;
++					regulator-always-on;
++					regulator-boot-on;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
++					maxim,active-fps-power-up-slot = <0>;
++					maxim,active-fps-power-down-slot = <7>;
++				};
++
++				vdd_pex_1v05: ldo1 {
++					regulator-name = "VDD_PEX_1V05";
++					regulator-min-microvolt = <1050000>;
++					regulator-max-microvolt = <1050000>;
++					regulator-enable-ramp-delay = <22>;
++					regulator-disable-ramp-delay = <650>;
++					regulator-ramp-delay = <100000>;
++					regulator-ramp-delay-scale = <200>;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
++					maxim,active-fps-power-up-slot = <0>;
++					maxim,active-fps-power-down-slot = <7>;
++				};
++
++				vddio_sdmmc: ldo2 {
++					regulator-name = "VDDIO_SDMMC";
++					regulator-min-microvolt = <1800000>;
++					regulator-max-microvolt = <3300000>;
++					regulator-enable-ramp-delay = <62>;
++					regulator-disable-ramp-delay = <650>;
++					regulator-ramp-delay = <100000>;
++					regulator-ramp-delay-scale = <200>;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
++					maxim,active-fps-power-up-slot = <0>;
++					maxim,active-fps-power-down-slot = <7>;
++				};
++
++				ldo3 {
++					status = "disabled";
++				};
++
++				vdd_rtc: ldo4 {
++					regulator-name = "VDD_RTC";
++					regulator-min-microvolt = <850000>;
++					regulator-max-microvolt = <1100000>;
++					regulator-enable-ramp-delay = <22>;
++					regulator-disable-ramp-delay = <610>;
++					regulator-ramp-delay = <100000>;
++					regulator-ramp-delay-scale = <200>;
++					regulator-disable-active-discharge;
++					regulator-always-on;
++					regulator-boot-on;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++					maxim,active-fps-power-up-slot = <1>;
++					maxim,active-fps-power-down-slot = <6>;
++				};
++
++				ldo5 {
++					status = "disabled";
++				};
++
++				ldo6 {
++					status = "disabled";
++				};
++
++				avdd_1v05_pll: ldo7 {
++					regulator-name = "AVDD_1V05_PLL";
++					regulator-min-microvolt = <1050000>;
++					regulator-max-microvolt = <1050000>;
++					regulator-enable-ramp-delay = <24>;
++					regulator-disable-ramp-delay = <2768>;
++					regulator-ramp-delay = <100000>;
++					regulator-ramp-delay-scale = <200>;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
++					maxim,active-fps-power-up-slot = <3>;
++					maxim,active-fps-power-down-slot = <4>;
++				};
++
++				avdd_1v05: ldo8 {
++					regulator-name = "AVDD_SATA_HDMI_DP_1V05";
++					regulator-min-microvolt = <1050000>;
++					regulator-max-microvolt = <1050000>;
++					regulator-enable-ramp-delay = <22>;
++					regulator-disable-ramp-delay = <1160>;
++					regulator-ramp-delay = <100000>;
++					regulator-ramp-delay-scale = <200>;
++
++					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
++					maxim,active-fps-power-up-slot = <6>;
++					maxim,active-fps-power-down-slot = <1>;
++				};
++			};
++		};
++	};
++
++	pmc@7000e400 {
++		nvidia,invert-interrupt;
++	};
++
++	hda@70030000 {
++		status = "okay";
++	};
++
++	usb@70090000 {
++		phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
++		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
++		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
++		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
++		phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
++
++		avdd-usb-supply = <&vdd_3v3_sys>;
++		dvddio-pex-supply = <&vdd_pex_1v05>;
++		hvddio-pex-supply = <&vdd_1v8>;
++
++		status = "okay";
++	};
++
++	padctl@7009f000 {
++		status = "okay";
++
++		avdd-pll-utmip-supply = <&vdd_1v8>;
++		avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
++		dvdd-pex-pll-supply = <&vdd_pex_1v05>;
++		hvdd-pex-pll-e-supply = <&vdd_1v8>;
++
++		pads {
++			usb2 {
++				status = "okay";
++
++				lanes {
++					usb2-0 {
++						nvidia,function = "xusb";
++						status = "okay";
++					};
++
++					usb2-1 {
++						nvidia,function = "xusb";
++						status = "okay";
++					};
++
++					usb2-2 {
++						nvidia,function = "xusb";
++						status = "okay";
++					};
++				};
++			};
++
++			pcie {
++				status = "okay";
++
++				lanes {
++					pcie-0 {
++						nvidia,function = "pcie-x1";
++						status = "okay";
++					};
++
++					pcie-1 {
++						nvidia,function = "pcie-x4";
++						status = "okay";
++					};
++
++					pcie-2 {
++						nvidia,function = "pcie-x4";
++						status = "okay";
++					};
++
++					pcie-3 {
++						nvidia,function = "pcie-x4";
++						status = "okay";
++					};
++
++					pcie-4 {
++						nvidia,function = "pcie-x4";
++						status = "okay";
++					};
++
++					pcie-5 {
++						nvidia,function = "usb3-ss";
++						status = "okay";
++					};
++
++					pcie-6 {
++						nvidia,function = "usb3-ss";
++						status = "okay";
++					};
++				};
++			};
++		};
++
++		ports {
++			usb2-0 {
++				status = "okay";
++				mode = "otg";
++			};
++
++			usb2-1 {
++				status = "okay";
++				mode = "host";
++			};
++
++			usb2-2 {
++				status = "okay";
++				mode = "host";
++			};
++
++			usb3-0 {
++				status = "okay";
++				nvidia,usb2-companion = <1>;
++				vbus-supply = <&vdd_hub_3v3>;
++			};
++		};
++	};
++
++	sdhci@700b0000 {
++		status = "okay";
++		bus-width = <4>;
++
++		cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
++
++		vqmmc-supply = <&vddio_sdmmc>;
++		vmmc-supply = <&vdd_3v3_sd>;
++	};
++
++	clocks {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		clk32k_in: clock@0 {
++			compatible = "fixed-clock";
++			reg = <0>;
++			#clock-cells = <0>;
++			clock-frequency = <32768>;
++		};
++	};
++
++	cpus {
++		cpu@0 {
++			enable-method = "psci";
++		};
++
++		cpu@1 {
++			enable-method = "psci";
++		};
++
++		cpu@2 {
++			enable-method = "psci";
++		};
++
++		cpu@3 {
++			enable-method = "psci";
++		};
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		power {
++			label = "Power";
++			gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
++			linux,input-type = <EV_KEY>;
++			linux,code = <KEY_POWER>;
++			debounce-interval = <30>;
++			wakeup-event-action = <EV_ACT_ASSERTED>;
++			wakeup-source;
++		};
++
++		force-recovery {
++			label = "Force Recovery";
++			gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
++			linux,input-type = <EV_KEY>;
++			linux,code = <BTN_1>;
++			debounce-interval = <30>;
++		};
++	};
++
++	psci {
++		compatible = "arm,psci-1.0";
++		method = "smc";
++	};
++
++	regulators {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		vdd_5v0_sys: regulator@0 {
++			compatible = "regulator-fixed";
++			reg = <0>;
++
++			regulator-name = "VDD_5V0_SYS";
++			regulator-min-microvolt = <5000000>;
++			regulator-max-microvolt = <5000000>;
++			regulator-always-on;
++			regulator-boot-on;
++		};
++
++		vdd_3v3_sys: regulator@1 {
++			compatible = "regulator-fixed";
++			reg = <1>;
++			regulator-name = "VDD_3V3_SYS";
++			regulator-min-microvolt = <3300000>;
++			regulator-max-microvolt = <3300000>;
++			regulator-enable-ramp-delay = <240>;
++			regulator-disable-ramp-delay = <11340>;
++			regulator-always-on;
++			regulator-boot-on;
++
++			gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
++			enable-active-high;
++
++			vin-supply = <&vdd_5v0_sys>;
++		};
++
++		vdd_3v3_sd: regulator@2 {
++			compatible = "regulator-fixed";
++			reg = <2>;
++
++			regulator-name = "VDD_3V3_SD";
++			regulator-min-microvolt = <3300000>;
++			regulator-max-microvolt = <3300000>;
++
++			gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
++			enable-active-high;
++
++			vin-supply = <&vdd_3v3_sys>;
++		};
++
++		vdd_hdmi: regulator@3 {
++			compatible = "regulator-fixed";
++			reg = <3>;
++
++			regulator-name = "VDD_HDMI_5V0";
++			regulator-min-microvolt = <5000000>;
++			regulator-max-microvolt = <5000000>;
++
++			vin-supply = <&vdd_5v0_sys>;
++		};
++
++		vdd_hub_3v3: regulator@4 {
++			compatible = "regulator-fixed";
++			reg = <4>;
++
++			regulator-name = "VDD_HUB_3V3";
++			regulator-min-microvolt = <3300000>;
++			regulator-max-microvolt = <3300000>;
++
++			gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
++			enable-active-high;
++
++			vin-supply = <&vdd_5v0_sys>;
++		};
++
++		vdd_cpu: regulator@5 {
++			compatible = "regulator-fixed";
++			reg = <5>;
++
++			regulator-name = "VDD_CPU";
++			regulator-min-microvolt = <5000000>;
++			regulator-max-microvolt = <5000000>;
++			regulator-always-on;
++			regulator-boot-on;
++
++			gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
++			enable-active-high;
++
++			vin-supply = <&vdd_5v0_sys>;
++		};
++
++		vdd_gpu: regulator@6 {
++			compatible = "regulator-fixed";
++			reg = <6>;
++
++			regulator-name = "VDD_GPU";
++			regulator-min-microvolt = <5000000>;
++			regulator-max-microvolt = <5000000>;
++			regulator-enable-ramp-delay = <250>;
++
++			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
++			enable-active-high;
++
++			vin-supply = <&vdd_5v0_sys>;
++		};
++	};
++};
diff --git a/arm64-tegra-jetson-tx1-fixes.patch b/arm64-tegra-jetson-tx1-fixes.patch
new file mode 100644
index 000000000..4ac5ea22a
--- /dev/null
+++ b/arm64-tegra-jetson-tx1-fixes.patch
@@ -0,0 +1,68 @@
+From 005e0b987019fff6013dff99f44d9f6ce68f08ad Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Sat, 23 Mar 2019 17:42:18 +0000
+Subject: [PATCH 1/3] arm64: tegra210: Jetson TX1: disable WP to make SD card
+ work
+
+There's some issue with Write Protect detection on the Jetson TX1
+so just apply a quirk to disable the check for the time being.
+
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+index a96e6ee70c21..072788646cbf 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+@@ -1456,6 +1456,7 @@
+ 	sdhci@700b0000 {
+ 		status = "okay";
+ 		bus-width = <4>;
++		disable-wp;
+ 
+ 		cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+ 
+-- 
+2.20.1
+
+From aea4a7a551fd7342299d34f04a8b75f58644ac07 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Sat, 23 Mar 2019 17:45:10 +0000
+Subject: [PATCH 2/3] arm64: tegra210: Jetson TX1: disable display panel and
+ associated backlight
+
+The Jetson TX1 dev kit doesn't ship with a screen by default and if
+it's not there it appears to crash on boot so disable them both by
+default until we work out the problem.
+
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+index 37e3c46e753f..a16f24f1d5ff 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+@@ -36,7 +36,7 @@
+ 
+ 	host1x@50000000 {
+ 		dsi@54300000 {
+-			status = "okay";
++			status = "disabled";
+ 
+ 			avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+ 
+@@ -54,6 +54,8 @@
+ 
+ 	i2c@7000c400 {
+ 		backlight: backlight@2c {
++			status = "disabled";
++
+ 			compatible = "ti,lp8557";
+ 			reg = <0x2c>;
+ 
+-- 
+2.20.1
diff --git a/kernel.spec b/kernel.spec
index d0b130dce..2c3e9cd23 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -568,6 +568,12 @@ Patch312: arm64-rock960-enable-tsadc.patch
 
 Patch339: bcm2835-cpufreq-add-CPU-frequency-control-driver.patch
 
+# Tegra bits
+Patch340: arm64-tegra-jetson-tx1-fixes.patch
+
+# https://patchwork.kernel.org/patch/10858639/
+Patch341: arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch
+
 # 400 - IBM (ppc/s390x) patches
 
 # 500 - Temp fixes/CVEs etc
@@ -1855,6 +1861,10 @@ fi
 #
 #
 %changelog
+* Sat Mar 23 2019 Peter Robinson <pbrobinson@fedoraproject.org>
+- Fixes for Tegra Jetson TX series
+- Initial support for NVIDIA Jetson Nano
+
 * Fri Mar 22 2019 Jeremy Cline <jcline@redhat.com> - 5.1.0-0.rc1.git2.1
 - Linux v5.1-rc1-66-gfd1f297b794c