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authorThorsten Leemhuis <fedora@leemhuis.info>2020-11-05 05:53:20 +0100
committerThorsten Leemhuis <fedora@leemhuis.info>2020-11-05 05:53:20 +0100
commit606fa81ac78c3fb6b0567f0d2059b0514dff4f98 (patch)
tree43c254b4d299a48c6951f3586ac6b7631fdf98ef
parente701b9d5461eb5337c6395e13edc779d4f5ea4c1 (diff)
parent4171a171ebfd0e09de704f0f0faeadbaf5ca0b47 (diff)
downloadkernel-606fa81ac78c3fb6b0567f0d2059b0514dff4f98.tar.gz
kernel-606fa81ac78c3fb6b0567f0d2059b0514dff4f98.tar.xz
kernel-606fa81ac78c3fb6b0567f0d2059b0514dff4f98.zip
-rw-r--r--0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch241
-rw-r--r--arm64-dts-rockchip-disable-USB-type-c-DisplayPort.patch168
-rw-r--r--arm64-tegra-Use-valid-PWM-period-for-VDD_GPU-on-Tegra210.patch48
-rw-r--r--brcmfmac-BCM4329-Fixes-and-improvement.patch372
-rw-r--r--configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST2
-rw-r--r--configs/fedora/generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U2
-rw-r--r--iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch48
-rw-r--r--kernel-aarch64-debug-fedora.config4
-rw-r--r--kernel-aarch64-fedora.config4
-rw-r--r--kernel.spec24
-rw-r--r--memory-tegra-Remove-GPU-from-DRM-IOMMU-group.patch113
-rw-r--r--mmc-sdhci-iproc-Enable-eMMC-DDR-3.3V-support-for-bcm2711.patch98
-rw-r--r--sources2
13 files changed, 1117 insertions, 9 deletions
diff --git a/0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch b/0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch
new file mode 100644
index 000000000..030343641
--- /dev/null
+++ b/0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch
@@ -0,0 +1,241 @@
+From dc7294c776b82b0f0feec1536b2f4676806b4b8a Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Tue, 3 Nov 2020 14:04:29 +0000
+Subject: [PATCH] PCI: Add MCFG quirks for Tegra194 host controllers
+
+The PCIe controller in Tegra194 SoC is not completely ECAM-compliant.
+With the current hardware design limitations in place, ECAM can be enabled
+only for one controller (C5 controller to be precise) with bus numbers
+starting from 160 instead of 0. A different approach is taken to avoid this
+abnormal way of enabling ECAM for just one controller but to enable
+configuration space access for all the other controllers. In this approach,
+ops are added through MCFG quirk mechanism which access the configuration
+spaces by dynamically programming iATU (internal AddressTranslation Unit)
+to generate respective configuration accesses just like the way it is
+done in DesignWare core sub-system.
+
+Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
+Acked-by: Thierry Reding <treding@nvidia.com>
+[ Updated by jonathanh@nvidia.com only permit building the Tegra194
+ PCIe driver into the kernel and not as a module ]
+Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ drivers/acpi/pci_mcfg.c | 7 ++
+ drivers/pci/controller/dwc/Kconfig | 10 +-
+ drivers/pci/controller/dwc/Makefile | 2 +-
+ drivers/pci/controller/dwc/pcie-tegra194.c | 102 +++++++++++++++++++++
+ include/linux/pci-ecam.h | 1 +
+ 5 files changed, 117 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
+index 54b36b7ad47d..6573d495d9c1 100644
+--- a/drivers/acpi/pci_mcfg.c
++++ b/drivers/acpi/pci_mcfg.c
+@@ -116,6 +116,13 @@ static struct mcfg_fixup mcfg_quirks[] = {
+ THUNDER_ECAM_QUIRK(2, 12),
+ THUNDER_ECAM_QUIRK(2, 13),
+
++ { "NVIDIA", "TEGRA194", 1, 0, MCFG_BUS_ANY, &tegra194_pcie_ops},
++ { "NVIDIA", "TEGRA194", 1, 1, MCFG_BUS_ANY, &tegra194_pcie_ops},
++ { "NVIDIA", "TEGRA194", 1, 2, MCFG_BUS_ANY, &tegra194_pcie_ops},
++ { "NVIDIA", "TEGRA194", 1, 3, MCFG_BUS_ANY, &tegra194_pcie_ops},
++ { "NVIDIA", "TEGRA194", 1, 4, MCFG_BUS_ANY, &tegra194_pcie_ops},
++ { "NVIDIA", "TEGRA194", 1, 5, MCFG_BUS_ANY, &tegra194_pcie_ops},
++
+ #define XGENE_V1_ECAM_MCFG(rev, seg) \
+ {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
+ &xgene_v1_pcie_ecam_ops }
+diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
+index 044a3761c44f..e4ee4bf9ac64 100644
+--- a/drivers/pci/controller/dwc/Kconfig
++++ b/drivers/pci/controller/dwc/Kconfig
+@@ -247,25 +247,27 @@ config PCI_MESON
+ implement the driver.
+
+ config PCIE_TEGRA194
+- tristate
++ bool
+
+ config PCIE_TEGRA194_HOST
+- tristate "NVIDIA Tegra194 (and later) PCIe controller - Host Mode"
++ bool "NVIDIA Tegra194 (and later) PCIe controller - Host Mode"
+ depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIE_DW_HOST
+ select PHY_TEGRA194_P2U
+ select PCIE_TEGRA194
++ default y if ARCH_TEGRA_194_SOC
+ help
+ Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to
+ work in host mode. There are two instances of PCIe controllers in
+ Tegra194. This controller can work either as EP or RC. In order to
+ enable host-specific features PCIE_TEGRA194_HOST must be selected and
+ in order to enable device-specific features PCIE_TEGRA194_EP must be
+- selected. This uses the DesignWare core.
++ selected. This uses the DesignWare core. ACPI platforms with Tegra194
++ don't need to enable this.
+
+ config PCIE_TEGRA194_EP
+- tristate "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode"
++ bool "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode"
+ depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
+ depends on PCI_ENDPOINT
+ select PCIE_DW_EP
+diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
+index a751553fa0db..dbb981876556 100644
+--- a/drivers/pci/controller/dwc/Makefile
++++ b/drivers/pci/controller/dwc/Makefile
+@@ -17,7 +17,6 @@ obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
+ obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
+ obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+ obj-$(CONFIG_PCI_MESON) += pci-meson.o
+-obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
+ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
+ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
+
+@@ -34,4 +33,5 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
+ ifdef CONFIG_PCI
+ obj-$(CONFIG_ARM64) += pcie-al.o
+ obj-$(CONFIG_ARM64) += pcie-hisi.o
++obj-$(CONFIG_ARM64) += pcie-tegra194.o
+ endif
+diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
+index 70498689d0c0..3db514e1ea7e 100644
+--- a/drivers/pci/controller/dwc/pcie-tegra194.c
++++ b/drivers/pci/controller/dwc/pcie-tegra194.c
+@@ -22,6 +22,8 @@
+ #include <linux/of_irq.h>
+ #include <linux/of_pci.h>
+ #include <linux/pci.h>
++#include <linux/pci-acpi.h>
++#include <linux/pci-ecam.h>
+ #include <linux/phy/phy.h>
+ #include <linux/pinctrl/consumer.h>
+ #include <linux/platform_device.h>
+@@ -324,6 +326,103 @@ struct tegra_pcie_dw_of_data {
+ enum dw_pcie_device_mode mode;
+ };
+
++#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
++struct tegra194_pcie_acpi {
++ void __iomem *config_base;
++ void __iomem *iatu_base;
++ void __iomem *dbi_base;
++};
++
++static int tegra194_acpi_init(struct pci_config_window *cfg)
++{
++ struct device *dev = cfg->parent;
++ struct tegra194_pcie_acpi *pcie;
++
++ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
++ if (!pcie)
++ return -ENOMEM;
++
++ pcie->config_base = cfg->win;
++ pcie->iatu_base = cfg->win + SZ_256K;
++ pcie->dbi_base = cfg->win + SZ_512K;
++ cfg->priv = pcie;
++
++ return 0;
++}
++
++static inline void atu_reg_write(struct tegra194_pcie_acpi *pcie, int index,
++ u32 val, u32 reg)
++{
++ u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
++
++ writel(val, pcie->iatu_base + offset + reg);
++}
++
++static void program_outbound_atu(struct tegra194_pcie_acpi *pcie, int index,
++ int type, u64 cpu_addr, u64 pci_addr, u64 size)
++{
++ atu_reg_write(pcie, index, lower_32_bits(cpu_addr),
++ PCIE_ATU_LOWER_BASE);
++ atu_reg_write(pcie, index, upper_32_bits(cpu_addr),
++ PCIE_ATU_UPPER_BASE);
++ atu_reg_write(pcie, index, lower_32_bits(pci_addr),
++ PCIE_ATU_LOWER_TARGET);
++ atu_reg_write(pcie, index, lower_32_bits(cpu_addr + size - 1),
++ PCIE_ATU_LIMIT);
++ atu_reg_write(pcie, index, upper_32_bits(pci_addr),
++ PCIE_ATU_UPPER_TARGET);
++ atu_reg_write(pcie, index, type, PCIE_ATU_CR1);
++ atu_reg_write(pcie, index, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
++}
++
++static void __iomem *tegra194_map_bus(struct pci_bus *bus,
++ unsigned int devfn, int where)
++{
++ struct pci_config_window *cfg = bus->sysdata;
++ struct tegra194_pcie_acpi *pcie = cfg->priv;
++ u32 busdev;
++ int type;
++
++ if (bus->number < cfg->busr.start || bus->number > cfg->busr.end)
++ return NULL;
++
++ if (bus->number == cfg->busr.start) {
++ if (PCI_SLOT(devfn) == 0)
++ return pcie->dbi_base + where;
++ else
++ return NULL;
++ }
++
++ busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
++ PCIE_ATU_FUNC(PCI_FUNC(devfn));
++
++ if (bus->parent->number == cfg->busr.start) {
++ if (PCI_SLOT(devfn) == 0)
++ type = PCIE_ATU_TYPE_CFG0;
++ else
++ return NULL;
++ } else {
++ type = PCIE_ATU_TYPE_CFG1;
++ }
++
++ program_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, type,
++ cfg->res.start, busdev, SZ_256K);
++ return (void __iomem *)(pcie->config_base + where);
++}
++
++const struct pci_ecam_ops tegra194_pcie_ops = {
++ .bus_shift = 20,
++ .init = tegra194_acpi_init,
++ .pci_ops = {
++ .map_bus = tegra194_map_bus,
++ .read = pci_generic_config_read,
++ .write = pci_generic_config_write,
++ }
++};
++#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
++
++#ifdef CONFIG_PCIE_TEGRA194
++
+ static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
+ {
+ return container_of(pci, struct tegra_pcie_dw, pci);
+@@ -2403,3 +2502,6 @@ MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
+ MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
+ MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
+ MODULE_LICENSE("GPL v2");
++
++#endif /* CONFIG_PCIE_TEGRA194 */
++
+diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
+index 1af5cb02ef7f..3fb16ada505a 100644
+--- a/include/linux/pci-ecam.h
++++ b/include/linux/pci-ecam.h
+@@ -57,6 +57,7 @@ extern const struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
+ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
+ extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
+ extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
++extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
+ #endif
+
+ #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
+--
+2.28.0
+
diff --git a/arm64-dts-rockchip-disable-USB-type-c-DisplayPort.patch b/arm64-dts-rockchip-disable-USB-type-c-DisplayPort.patch
new file mode 100644
index 000000000..dab88080d
--- /dev/null
+++ b/arm64-dts-rockchip-disable-USB-type-c-DisplayPort.patch
@@ -0,0 +1,168 @@
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+From: Jian-Hong Pan <jhp@endlessos.org>
+To: Rob Herring <robh+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de>,
+ Soeren Moch <smoch@web.de>, Tobias Schramm <t.schramm@manjaro.org>,
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+ Hugh Cole-Baker <sigmaris@gmail.com>, Robin Murphy <robin.murphy@arm.com>
+Subject: [PATCH] arm64: dts: rockchip: disable USB type-c DisplayPort
+Date: Thu, 24 Sep 2020 14:30:43 +0800
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+Cc: devicetree@vger.kernel.org, Jian-Hong Pan <jhp@endlessos.org>,
+ linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
+ linux@endlessm.com, linux-arm-kernel@lists.infradead.org
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+ linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
+
+The cdn-dp sub driver probes the device failed on PINEBOOK Pro.
+
+kernel: cdn-dp fec00000.dp: [drm:cdn_dp_probe [rockchipdrm]] *ERROR* missing extcon or phy
+kernel: cdn-dp: probe of fec00000.dp failed with error -22
+
+Then, the device halts all of the DRM related device jobs. For example,
+the operations: vop_component_ops, vop_component_ops and
+rockchip_dp_component_ops cannot be bound to corresponding devices. So,
+Xorg cannot find the correct DRM device.
+
+The USB type-C DisplayPort does not work for now. So, disable the
+DisplayPort node until the type-C phy work has been done.
+
+Link: https://patchwork.kernel.org/patch/11794141/#23639877
+Signed-off-by: Jian-Hong Pan <jhp@endlessos.org>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+index 06d48338c836..d624c595c533 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+@@ -380,7 +380,7 @@ mains_charger: dc-charger {
+ };
+
+ &cdn_dp {
+- status = "okay";
++ status = "disabled";
+ };
+
+ &cpu_b0 {
diff --git a/arm64-tegra-Use-valid-PWM-period-for-VDD_GPU-on-Tegra210.patch b/arm64-tegra-Use-valid-PWM-period-for-VDD_GPU-on-Tegra210.patch
new file mode 100644
index 000000000..3a7ad1e00
--- /dev/null
+++ b/arm64-tegra-Use-valid-PWM-period-for-VDD_GPU-on-Tegra210.patch
@@ -0,0 +1,48 @@
+From a267434b15bc06c72708327fb1110bf565577a15 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Tue, 3 Nov 2020 16:53:02 +0000
+Subject: [PATCH] arm64: tegra: Use valid PWM period for VDD_GPU on Tegra210
+
+From: Thierry Reding <treding@nvidia.com>
+
+The PWM on Tegra210 can run at a maximum frequency of 48 MHz and cannot
+reach the minimum period is 5334 ns. The currently configured period of
+4880 ns is not within the valid range, so set it to 8000 ns. This value
+was taken from the downstream DTS files and seems to work fine.
+
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +-
+ arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+index 6a4b50aaa25d..85ee7e6b71ac 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+@@ -337,7 +337,7 @@ psci {
+
+ vdd_gpu: regulator@100 {
+ compatible = "pwm-regulator";
+- pwms = <&pwm 1 4880>;
++ pwms = <&pwm 1 8000>;
+ regulator-name = "VDD_GPU";
+ regulator-min-microvolt = <710000>;
+ regulator-max-microvolt = <1320000>;
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+index 2282ea1c6279..195a43e2356b 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+@@ -818,7 +818,7 @@ vdd_cpu: regulator@5 {
+
+ vdd_gpu: regulator@6 {
+ compatible = "pwm-regulator";
+- pwms = <&pwm 1 4880>;
++ pwms = <&pwm 1 8000>;
+
+ regulator-name = "VDD_GPU";
+ regulator-min-microvolt = <710000>;
+--
+2.28.0
+
diff --git a/brcmfmac-BCM4329-Fixes-and-improvement.patch b/brcmfmac-BCM4329-Fixes-and-improvement.patch
new file mode 100644
index 000000000..b492f82c9
--- /dev/null
+++ b/brcmfmac-BCM4329-Fixes-and-improvement.patch
@@ -0,0 +1,372 @@
+From patchwork Sun Aug 30 19:14:37 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Dmitry Osipenko <digetx@gmail.com>
+X-Patchwork-Id: 11745283
+X-Patchwork-Delegate: kvalo@adurom.com
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+ Sun, 30 Aug 2020 12:15:04 -0700 (PDT)
+From: Dmitry Osipenko <digetx@gmail.com>
+To: Arend van Spriel <arend.vanspriel@broadcom.com>,
+ Franky Lin <franky.lin@broadcom.com>,
+ Hante Meuleman <hante.meuleman@broadcom.com>,
+ Chi-Hsien Lin <chi-hsien.lin@cypress.com>,
+ Wright Feng <wright.feng@cypress.com>,
+ Kalle Valo <kvalo@codeaurora.org>
+Cc: linux-wireless@vger.kernel.org,
+ brcm80211-dev-list.pdl@broadcom.com,
+ brcm80211-dev-list@cypress.com, netdev@vger.kernel.org,
+ linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH v3 1/3] brcmfmac: increase F2 watermark for BCM4329
+Date: Sun, 30 Aug 2020 22:14:37 +0300
+Message-Id: <20200830191439.10017-2-digetx@gmail.com>
+X-Mailer: git-send-email 2.27.0
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+
+This patch fixes SDHCI CRC errors during of RX throughput testing on
+BCM4329 chip if SDIO BUS is clocked above 25MHz. In particular the
+checksum problem is observed on NVIDIA Tegra20 SoCs. The good watermark
+value is borrowed from downstream BCMDHD driver and it's matching to the
+value that is already used for the BCM4339 chip, hence let's re-use it
+for BCM4329.
+
+Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com>
+Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+index d1b96bad2718..b16944a898f9 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+@@ -4278,6 +4278,7 @@ static void brcmf_sdio_firmware_callback(struct device *dev, int err,
+ brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
+ CY_43012_MESBUSYCTRL, &err);
+ break;
++ case SDIO_DEVICE_ID_BROADCOM_4329:
+ case SDIO_DEVICE_ID_BROADCOM_4339:
+ brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes for 4339\n",
+ CY_4339_F2_WATERMARK);
+
+From patchwork Sun Aug 30 19:14:38 2020
+Content-Type: text/plain; charset="utf-8"
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+X-Patchwork-Id: 11745287
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+ Sun, 30 Aug 2020 12:15:05 -0700 (PDT)
+From: Dmitry Osipenko <digetx@gmail.com>
+To: Arend van Spriel <arend.vanspriel@broadcom.com>,
+ Franky Lin <franky.lin@broadcom.com>,
+ Hante Meuleman <hante.meuleman@broadcom.com>,
+ Chi-Hsien Lin <chi-hsien.lin@cypress.com>,
+ Wright Feng <wright.feng@cypress.com>,
+ Kalle Valo <kvalo@codeaurora.org>
+Cc: linux-wireless@vger.kernel.org,
+ brcm80211-dev-list.pdl@broadcom.com,
+ brcm80211-dev-list@cypress.com, netdev@vger.kernel.org,
+ linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH v3 2/3] brcmfmac: drop chip id from debug messages
+Date: Sun, 30 Aug 2020 22:14:38 +0300
+Message-Id: <20200830191439.10017-3-digetx@gmail.com>
+X-Mailer: git-send-email 2.27.0
+In-Reply-To: <20200830191439.10017-1-digetx@gmail.com>
+References: <20200830191439.10017-1-digetx@gmail.com>
+MIME-Version: 1.0
+Sender: linux-wireless-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-wireless.vger.kernel.org>
+X-Mailing-List: linux-wireless@vger.kernel.org
+
+The chip ID was already printed out at the time when debug message about
+the changed F2 watermark is printed, hence let's drop the unnecessary part
+of the debug messages. This cleans code a tad and also allows to re-use
+the F2 watermark debug messages by multiple chips.
+
+Suggested-by: Arend van Spriel <arend.vanspriel@broadcom.com>
+Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+index b16944a898f9..d4989e0cd7be 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+@@ -4280,7 +4280,7 @@ static void brcmf_sdio_firmware_callback(struct device *dev, int err,
+ break;
+ case SDIO_DEVICE_ID_BROADCOM_4329:
+ case SDIO_DEVICE_ID_BROADCOM_4339:
+- brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes for 4339\n",
++ brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
+ CY_4339_F2_WATERMARK);
+ brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
+ CY_4339_F2_WATERMARK, &err);
+@@ -4293,7 +4293,7 @@ static void brcmf_sdio_firmware_callback(struct device *dev, int err,
+ CY_4339_MESBUSYCTRL, &err);
+ break;
+ case SDIO_DEVICE_ID_BROADCOM_43455:
+- brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes for 43455\n",
++ brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
+ CY_43455_F2_WATERMARK);
+ brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
+ CY_43455_F2_WATERMARK, &err);
+
+From patchwork Sun Aug 30 19:14:39 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Dmitry Osipenko <digetx@gmail.com>
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+ Sun, 30 Aug 2020 12:15:06 -0700 (PDT)
+From: Dmitry Osipenko <digetx@gmail.com>
+To: Arend van Spriel <arend.vanspriel@broadcom.com>,
+ Franky Lin <franky.lin@broadcom.com>,
+ Hante Meuleman <hante.meuleman@broadcom.com>,
+ Chi-Hsien Lin <chi-hsien.lin@cypress.com>,
+ Wright Feng <wright.feng@cypress.com>,
+ Kalle Valo <kvalo@codeaurora.org>
+Cc: linux-wireless@vger.kernel.org,
+ brcm80211-dev-list.pdl@broadcom.com,
+ brcm80211-dev-list@cypress.com, netdev@vger.kernel.org,
+ linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH v3 3/3] brcmfmac: set F2 SDIO block size to 128 bytes for
+ BCM4329
+Date: Sun, 30 Aug 2020 22:14:39 +0300
+Message-Id: <20200830191439.10017-4-digetx@gmail.com>
+X-Mailer: git-send-email 2.27.0
+In-Reply-To: <20200830191439.10017-1-digetx@gmail.com>
+References: <20200830191439.10017-1-digetx@gmail.com>
+MIME-Version: 1.0
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+List-ID: <linux-wireless.vger.kernel.org>
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+
+Setting F2 block size to 128 bytes for BCM4329 allows to significantly
+improve RX throughput on NVIDIA Tegra20. Before this change the throughput
+was capped to 30 Mbit/s on Tegra, now throughput is at 40 Mbit/s, which is
+a maximum throughput for the BCM4329 chip. The F2 block size is borrowed
+from the downstream BCMDHD driver. The comment in the BCMDHD driver says
+that 128B improves throughput and turns out that it works for the brcmfmac
+as well.
+
+Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
+index 0dc4de2fa9f6..318bd00bf94f 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
+@@ -45,6 +45,7 @@
+ #define SDIO_FUNC2_BLOCKSIZE 512
+ #define SDIO_4373_FUNC2_BLOCKSIZE 256
+ #define SDIO_435X_FUNC2_BLOCKSIZE 256
++#define SDIO_4329_FUNC2_BLOCKSIZE 128
+ /* Maximum milliseconds to wait for F2 to come up */
+ #define SDIO_WAIT_F2RDY 3000
+
+@@ -920,6 +921,9 @@ int brcmf_sdiod_probe(struct brcmf_sdio_dev *sdiodev)
+ case SDIO_DEVICE_ID_BROADCOM_4356:
+ f2_blksz = SDIO_435X_FUNC2_BLOCKSIZE;
+ break;
++ case SDIO_DEVICE_ID_BROADCOM_4329:
++ f2_blksz = SDIO_4329_FUNC2_BLOCKSIZE;
++ break;
+ default:
+ break;
+ }
diff --git a/configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST b/configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST
index d79eeb7a7..005ca5c32 100644
--- a/configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST
+++ b/configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST
@@ -1 +1 @@
-CONFIG_PCIE_TEGRA194_HOST=m
+CONFIG_PCIE_TEGRA194_HOST=y
diff --git a/configs/fedora/generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U b/configs/fedora/generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U
index 23e44783c..96d1b8819 100644
--- a/configs/fedora/generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U
+++ b/configs/fedora/generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U
@@ -1 +1 @@
-CONFIG_PHY_TEGRA194_P2U=m
+CONFIG_PHY_TEGRA194_P2U=y
diff --git a/iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch b/iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch
new file mode 100644
index 000000000..381fb3659
--- /dev/null
+++ b/iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch
@@ -0,0 +1,48 @@
+From c461469e12073007ac4bbddd3a4830632c065738 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Mon, 28 Sep 2020 11:34:09 +0100
+Subject: [PATCH] These two patches fix ACTIVE_TLB_LINES field setting in
+ tegra-smmu driver for Tegra210 platforms.
+
+This resend in series groups two previous seperate changes that're
+corelated, being pointed out by Thierry. Also adding his Acked-by.
+
+Nicolin Chen (2):
+ iommu/tegra-smmu: Fix tlb_mask
+ memory: tegra: Correct num_tlb_lines for tegra210
+
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ drivers/iommu/tegra-smmu.c | 2 +-
+ drivers/memory/tegra/tegra210.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
+index 7426b7666e2b..d5f1384ef6a1 100644
+--- a/drivers/iommu/tegra-smmu.c
++++ b/drivers/iommu/tegra-smmu.c
+@@ -1022,7 +1022,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
+ smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
+ dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
+ mc->soc->num_address_bits, smmu->pfn_mask);
+- smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1;
++ smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1;
+ dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines,
+ smmu->tlb_mask);
+
+diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
+index cc0482434c75..7212d1d7b348 100644
+--- a/drivers/memory/tegra/tegra210.c
++++ b/drivers/memory/tegra/tegra210.c
+@@ -1073,7 +1073,7 @@ static const struct tegra_smmu_soc tegra210_smmu_soc = {
+ .num_groups = ARRAY_SIZE(tegra210_groups),
+ .supports_round_robin_arbitration = true,
+ .supports_request_limit = true,
+- .num_tlb_lines = 32,
++ .num_tlb_lines = 48,
+ .num_asids = 128,
+ };
+
+--
+2.26.2
+
diff --git a/kernel-aarch64-debug-fedora.config b/kernel-aarch64-debug-fedora.config
index 0c4c0827f..874f98236 100644
--- a/kernel-aarch64-debug-fedora.config
+++ b/kernel-aarch64-debug-fedora.config
@@ -4746,7 +4746,7 @@ CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_PTM=y
CONFIG_PCIE_QCOM=y
# CONFIG_PCIE_ROCKCHIP_HOST is not set
-CONFIG_PCIE_TEGRA194_HOST=m
+CONFIG_PCIE_TEGRA194_HOST=y
CONFIG_PCIE_XILINX_CPM=y
CONFIG_PCIE_XILINX_NWL=y
CONFIG_PCIE_XILINX=y
@@ -4862,7 +4862,7 @@ CONFIG_PHY_SUN4I_USB=m
CONFIG_PHY_SUN50I_USB3=m
CONFIG_PHY_SUN6I_MIPI_DPHY=m
# CONFIG_PHY_SUN9I_USB is not set
-CONFIG_PHY_TEGRA194_P2U=m
+CONFIG_PHY_TEGRA194_P2U=y
CONFIG_PHY_TEGRA_XUSB=m
# CONFIG_PHY_TUSB1210 is not set
CONFIG_PHY_XGENE=y
diff --git a/kernel-aarch64-fedora.config b/kernel-aarch64-fedora.config
index ccf6afda6..fdef9e50f 100644
--- a/kernel-aarch64-fedora.config
+++ b/kernel-aarch64-fedora.config
@@ -4727,7 +4727,7 @@ CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_PTM=y
CONFIG_PCIE_QCOM=y
# CONFIG_PCIE_ROCKCHIP_HOST is not set
-CONFIG_PCIE_TEGRA194_HOST=m
+CONFIG_PCIE_TEGRA194_HOST=y
CONFIG_PCIE_XILINX_CPM=y
CONFIG_PCIE_XILINX_NWL=y
CONFIG_PCIE_XILINX=y
@@ -4843,7 +4843,7 @@ CONFIG_PHY_SUN4I_USB=m
CONFIG_PHY_SUN50I_USB3=m
CONFIG_PHY_SUN6I_MIPI_DPHY=m
# CONFIG_PHY_SUN9I_USB is not set
-CONFIG_PHY_TEGRA194_P2U=m
+CONFIG_PHY_TEGRA194_P2U=y
CONFIG_PHY_TEGRA_XUSB=m
# CONFIG_PHY_TUSB1210 is not set
CONFIG_PHY_XGENE=y
diff --git a/kernel.spec b/kernel.spec
index 67a400bc0..5077938ea 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -96,8 +96,7 @@ Summary: The Linux kernel
%define stable_rc 0
# Do we have a -stable update to apply?
-%define stable_update 3
-
+%define stable_update 4
# Set rpm version accordingly
%if 0%{?stable_update}
%define stablerev %{stable_update}
@@ -851,6 +850,22 @@ Patch68: 0001-drm-sun4i-sun6i_mipi_dsi-fix-horizontal-timing-calcu.patch
Patch70: 0001-e1000e-bump-up-timeout-to-wait-when-ME-un-configure-.patch
Patch72: 0001-Work-around-for-gcc-bug-https-gcc.gnu.org-bugzilla-s.patch
+# https://patchwork.kernel.org/patch/11743769/
+Patch100: mmc-sdhci-iproc-Enable-eMMC-DDR-3.3V-support-for-bcm2711.patch
+
+# https://patchwork.kernel.org/patch/11745283/
+Patch101: brcmfmac-BCM4329-Fixes-and-improvement.patch
+
+# https://patchwork.kernel.org/patch/11796255/
+Patch102: arm64-dts-rockchip-disable-USB-type-c-DisplayPort.patch
+
+# Tegra fixes
+Patch105: 0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch
+Patch106: arm64-tegra-Use-valid-PWM-period-for-VDD_GPU-on-Tegra210.patch
+Patch107: memory-tegra-Remove-GPU-from-DRM-IOMMU-group.patch
+# https://www.spinics.net/lists/linux-tegra/msg53605.html
+Patch108: iommu-tegra-smmu-Fix-TLB-line-for-Tegra210.patch
+
# A patch to fix some undocumented things broke a bunch of Allwinner networks due to wrong assumptions
Patch124: 0001-update-phy-on-pine64-a64-devices.patch
# https://patchwork.kernel.org/project/linux-arm-kernel/patch/20201024162515.30032-2-wens@kernel.org/
@@ -2987,6 +3002,11 @@ fi
#
#
%changelog
+* Wed Nov 4 17:08:50 CST 2020 Justin M. Forbes <jforbes@fedoraproject.org> - 5.9.4-300
+- Linux v5.9.4
+- Fixes CVE-2020-25668 (rhbz 1893287 1893288)
+- Fixes CVE-2020-27673 (rhbz 1891110 1891112)
+
* Mon Nov 2 12:03:06 CST 2020 Justin M. Forbes <jforbes@fedoraproject.org> - 5.9.3-300
- Linux v5.9.3
diff --git a/memory-tegra-Remove-GPU-from-DRM-IOMMU-group.patch b/memory-tegra-Remove-GPU-from-DRM-IOMMU-group.patch
new file mode 100644
index 000000000..7b30b78b2
--- /dev/null
+++ b/memory-tegra-Remove-GPU-from-DRM-IOMMU-group.patch
@@ -0,0 +1,113 @@
+From patchwork Tue Sep 1 15:32:48 2020
+Content-Type: text/plain; charset="utf-8"
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+ Tue, 01 Sep 2020 08:32:52 -0700 (PDT)
+From: Thierry Reding <thierry.reding@gmail.com>
+To: Krzysztof Kozlowski <krzk@kernel.org>,
+ Thierry Reding <thierry.reding@gmail.com>
+Cc: Jonathan Hunter <jonathanh@nvidia.com>, Dmitry Osipenko <digetx@gmail.com>,
+ linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
+ Matias Zuniga <matias.nicolas.zc@gmail.com>
+Subject: [PATCH] memory: tegra: Remove GPU from DRM IOMMU group
+Date: Tue, 1 Sep 2020 17:32:48 +0200
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+
+From: Thierry Reding <treding@nvidia.com>
+
+Commit 63a613fdb16c ("memory: tegra: Add gr2d and gr3d to DRM IOMMU
+group") added the GPU to the DRM IOMMU group, which doesn't make any
+sense. This causes problems when Nouveau tries to attach to the SMMU
+and causes it to fall back to using the DMA API.
+
+Remove the GPU from the DRM groups to restore the old behaviour. The
+GPU should always have its own IOMMU domain to make sure it can map
+buffers into contiguous chunks (for big page support) without getting
+in the way of mappings from the DRM group.
+
+Fixes: 63a613fdb16c ("memory: tegra: Add gr2d and gr3d to DRM IOMMU group")
+Reported-by: Matias Zuniga <matias.nicolas.zc@gmail.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
+---
+ drivers/memory/tegra/tegra124.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
+index 493b5dc3a4b3..0cede24479bf 100644
+--- a/drivers/memory/tegra/tegra124.c
++++ b/drivers/memory/tegra/tegra124.c
+@@ -957,7 +957,6 @@ static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
+ static const unsigned int tegra124_group_drm[] = {
+ TEGRA_SWGROUP_DC,
+ TEGRA_SWGROUP_DCB,
+- TEGRA_SWGROUP_GPU,
+ TEGRA_SWGROUP_VIC,
+ };
+
diff --git a/mmc-sdhci-iproc-Enable-eMMC-DDR-3.3V-support-for-bcm2711.patch b/mmc-sdhci-iproc-Enable-eMMC-DDR-3.3V-support-for-bcm2711.patch
new file mode 100644
index 000000000..6f5cf820b
--- /dev/null
+++ b/mmc-sdhci-iproc-Enable-eMMC-DDR-3.3V-support-for-bcm2711.patch
@@ -0,0 +1,98 @@
+From patchwork Fri Aug 28 21:47:14 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Stefan Wahren <stefan.wahren@i2se.com>
+X-Patchwork-Id: 11743769
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+From: Stefan Wahren <stefan.wahren@i2se.com>
+To: Adrian Hunter <adrian.hunter@intel.com>,
+ Ulf Hansson <ulf.hansson@linaro.org>,
+ Ray Jui <rjui@broadcom.com>,
+ Scott Branden <sbranden@broadcom.com>
+Cc: Florian Fainelli <f.fainelli@gmail.com>,
+ Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
+ Matthias Brugger <mbrugger@suse.com>,
+ bcm-kernel-feedback-list@broadcom.com, linux-mmc@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org,
+ Stefan Wahren <stefan.wahren@i2se.com>
+Subject: [PATCH] mmc: sdhci-iproc: Enable eMMC DDR 3.3V support for bcm2711
+Date: Fri, 28 Aug 2020 23:47:14 +0200
+Message-Id: <1598651234-29826-1-git-send-email-stefan.wahren@i2se.com>
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+ VLEnvtryHj/lA4fHtioyBJ4A5CpKR2At7wnlKOICKyaHniUfMlssMuxexvZkbh5Tk/TR7aW7A
+ krPi5wigbGYz2Pf0BiIjJOix9EDYS3+e2oyn6oFZX2gJcfDBT48tMcVYK3IOk6vnwvvmszY/k
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+Sender: linux-mmc-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-mmc.vger.kernel.org>
+X-Mailing-List: linux-mmc@vger.kernel.org
+
+The emmc2 interface on the bcm2711 supports DDR modes for eMMC devices
+running at 3.3V. This allows to run eMMC module with 3.3V signaling voltage
+at DDR52 mode on the Raspberry Pi 4 using a SD adapter:
+
+ clock: 52000000 Hz
+ actual clock: 50000000 Hz
+ vdd: 21 (3.3 ~ 3.4 V)
+ bus mode: 2 (push-pull)
+ chip select: 0 (don't care)
+ power mode: 2 (on)
+ bus width: 2 (4 bits)
+ timing spec: 8 (mmc DDR52)
+ signal voltage: 0 (3.30 V)
+ driver type: 0 (driver type B)
+
+Link: https://github.com/raspberrypi/linux/issues/3802
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+---
+ drivers/mmc/host/sdhci-iproc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/mmc/host/sdhci-iproc.c b/drivers/mmc/host/sdhci-iproc.c
+index e2d8dfe..b540aa6 100644
+--- a/drivers/mmc/host/sdhci-iproc.c
++++ b/drivers/mmc/host/sdhci-iproc.c
+@@ -283,6 +283,7 @@ static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
+
+ static const struct sdhci_iproc_data bcm2711_data = {
+ .pdata = &sdhci_bcm2711_pltfm_data,
++ .mmc_caps = MMC_CAP_3_3V_DDR,
+ };
+
+ static const struct of_device_id sdhci_iproc_of_match[] = {
diff --git a/sources b/sources
index 4b3887fca..45c7d907c 100644
--- a/sources
+++ b/sources
@@ -1,2 +1,2 @@
SHA512 (linux-5.9.tar.xz) = cafd463ca0c9b256479b7dd774f908cedef6d265c44f99de075558ab923808ddfacda1377ae000ce02730c6611527bddffbfc4421bbc4f44fd8e59d97cbc4363
-SHA512 (patch-5.9.3.xz) = 6a5a61671d5cdf8025900a02a268d9479fb79b27b772ecb5d25ee908ddd233ffb048568a2bbf9e95f20b5b807038774988d8bc22039e6429d1fb30a906471028
+SHA512 (patch-5.9.4.xz) = cbf45c5c4dd1397b06d94197a1ad7ec2539943adbd91b7f84039648b3595bf2f40cb7ab5e5bd551eca902a7246268698359c238737a038416e8b3fdfa6c7970b