Merge remote-tracking branch 'origin/stabilization' into stabilization-user-thl-vanilla-fedora

3 files changed, 1545 insertions, 146 deletions

diff --git a/allwinner-net-emac.patch b/allwinner-net-emac.patch
index 346c50809..6d4f11d90 100644
--- a/allwinner-net-emac.patch
+++ b/allwinner-net-emac.patch
@@ -1,18 +1,575 @@
-From 83e18f0ad4793ea83e03cb8e608bdd2939e76d78 Mon Sep 17 00:00:00 2001
-From: Peter Robinson <pbrobinson@gmail.com>
-Date: Mon, 4 Sep 2017 13:04:34 +0100
-Subject: [PATCH 1/4] Revert "net: stmmac: sun8i: Remove the compatibles"
+From 1b28a544627ddce094091946f06f99bc41d0098f Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 24 Oct 2017 19:57:12 +0200
+Subject: [PATCH 01/11] net: stmmac: snps, dwmac-mdio MDIOs are automatically
+ registered
+
+stmmac bindings docs said that its mdio node must have
+compatible = "snps,dwmac-mdio";
+Since dwmac-sun8i does not have any good reasons to not doing it, all
+their MDIO node must have it.
+
+Since these compatible is automatically registered, dwmac-sun8i compatible
+does not need to be in need_mdio_ids.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+index 6383695004a5..645ef949705f 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+@@ -318,10 +318,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
+ 	bool mdio = true;
+ 	static const struct of_device_id need_mdio_ids[] = {
+ 		{ .compatible = "snps,dwc-qos-ethernet-4.10" },
+-		{ .compatible = "allwinner,sun8i-a83t-emac" },
+-		{ .compatible = "allwinner,sun8i-h3-emac" },
+-		{ .compatible = "allwinner,sun8i-v3s-emac" },
+-		{ .compatible = "allwinner,sun50i-a64-emac" },
+ 		{},
+ 	};
+ 
+-- 
+2.14.3
+
+From 9a5b1d9a7614b022512744896d889e76f687e90a Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 24 Oct 2017 19:57:13 +0200
+Subject: [PATCH 02/11] net: stmmac: dwmac-sun8i: Handle integrated/external
+ MDIOs
+
+The Allwinner H3 SoC have two distinct MDIO bus, only one could be
+active at the same time.
+The selection of the active MDIO bus are done via some bits in the EMAC
+register of the system controller.
+
+This patch implement this MDIO switch via a custom MDIO-mux.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+---
+ drivers/net/ethernet/stmicro/stmmac/Kconfig       |   1 +
+ drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 353 ++++++++++++++--------
+ 2 files changed, 224 insertions(+), 130 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
+index 97035766c291..e28c0d2c58e9 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
+@@ -159,6 +159,7 @@ config DWMAC_SUN8I
+ 	tristate "Allwinner sun8i GMAC support"
+ 	default ARCH_SUNXI
+ 	depends on OF && (ARCH_SUNXI || COMPILE_TEST)
++	select MDIO_BUS_MUX
+ 	---help---
+ 	  Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
+ 
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 39c2122a4f26..b3eb344bb158 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -17,6 +17,7 @@
+ #include <linux/clk.h>
+ #include <linux/io.h>
+ #include <linux/iopoll.h>
++#include <linux/mdio-mux.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of_device.h>
+@@ -41,14 +42,14 @@
+  *				This value is used for disabling properly EMAC
+  *				and used as a good starting value in case of the
+  *				boot process(uboot) leave some stuff.
+- * @internal_phy:		Does the MAC embed an internal PHY
++ * @soc_has_internal_phy:	Does the MAC embed an internal PHY
+  * @support_mii:		Does the MAC handle MII
+  * @support_rmii:		Does the MAC handle RMII
+  * @support_rgmii:		Does the MAC handle RGMII
+  */
+ struct emac_variant {
+ 	u32 default_syscon_value;
+-	int internal_phy;
++	bool soc_has_internal_phy;
+ 	bool support_mii;
+ 	bool support_rmii;
+ 	bool support_rgmii;
+@@ -61,7 +62,8 @@ struct emac_variant {
+  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
+  * @variant:	reference to the current board variant
+  * @regmap:	regmap for using the syscon
+- * @use_internal_phy: Does the current PHY choice imply using the internal PHY
++ * @internal_phy_powered: Does the internal PHY is enabled
++ * @mux_handle:	Internal pointer used by mdio-mux lib
+  */
+ struct sunxi_priv_data {
+ 	struct clk *tx_clk;
+@@ -70,12 +72,13 @@ struct sunxi_priv_data {
+ 	struct reset_control *rst_ephy;
+ 	const struct emac_variant *variant;
+ 	struct regmap *regmap;
+-	bool use_internal_phy;
++	bool internal_phy_powered;
++	void *mux_handle;
+ };
+ 
+ static const struct emac_variant emac_variant_h3 = {
+ 	.default_syscon_value = 0x58000,
+-	.internal_phy = PHY_INTERFACE_MODE_MII,
++	.soc_has_internal_phy = true,
+ 	.support_mii = true,
+ 	.support_rmii = true,
+ 	.support_rgmii = true
+@@ -83,20 +86,20 @@ static const struct emac_variant emac_variant_h3 = {
+ 
+ static const struct emac_variant emac_variant_v3s = {
+ 	.default_syscon_value = 0x38000,
+-	.internal_phy = PHY_INTERFACE_MODE_MII,
++	.soc_has_internal_phy = true,
+ 	.support_mii = true
+ };
+ 
+ static const struct emac_variant emac_variant_a83t = {
+ 	.default_syscon_value = 0,
+-	.internal_phy = 0,
++	.soc_has_internal_phy = false,
+ 	.support_mii = true,
+ 	.support_rgmii = true
+ };
+ 
+ static const struct emac_variant emac_variant_a64 = {
+ 	.default_syscon_value = 0,
+-	.internal_phy = 0,
++	.soc_has_internal_phy = false,
+ 	.support_mii = true,
+ 	.support_rmii = true,
+ 	.support_rgmii = true
+@@ -195,6 +198,9 @@ static const struct emac_variant emac_variant_a64 = {
+ #define H3_EPHY_LED_POL		BIT(17) /* 1: active low, 0: active high */
+ #define H3_EPHY_SHUTDOWN	BIT(16) /* 1: shutdown, 0: power up */
+ #define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
++#define H3_EPHY_MUX_MASK	(H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
++#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID	1
++#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID	2
+ 
+ /* H3/A64 specific bits */
+ #define SYSCON_RMII_EN		BIT(13) /* 1: enable RMII (overrides EPIT) */
+@@ -634,6 +640,159 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)
+ 	return 0;
+ }
+ 
++/* Search in mdio-mux node for internal PHY node and get its clk/reset */
++static int get_ephy_nodes(struct stmmac_priv *priv)
++{
++	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
++	struct device_node *mdio_mux, *iphynode;
++	struct device_node *mdio_internal;
++	int ret;
++
++	mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
++	if (!mdio_mux) {
++		dev_err(priv->device, "Cannot get mdio-mux node\n");
++		return -ENODEV;
++	}
++
++	mdio_internal = of_find_compatible_node(mdio_mux, NULL,
++						"allwinner,sun8i-h3-mdio-internal");
++	if (!mdio_internal) {
++		dev_err(priv->device, "Cannot get internal_mdio node\n");
++		return -ENODEV;
++	}
++
++	/* Seek for internal PHY */
++	for_each_child_of_node(mdio_internal, iphynode) {
++		gmac->ephy_clk = of_clk_get(iphynode, 0);
++		if (IS_ERR(gmac->ephy_clk))
++			continue;
++		gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
++		if (IS_ERR(gmac->rst_ephy)) {
++			ret = PTR_ERR(gmac->rst_ephy);
++			if (ret == -EPROBE_DEFER)
++				return ret;
++			continue;
++		}
++		dev_info(priv->device, "Found internal PHY node\n");
++		return 0;
++	}
++	return -ENODEV;
++}
++
++static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
++{
++	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
++	int ret;
++
++	if (gmac->internal_phy_powered) {
++		dev_warn(priv->device, "Internal PHY already powered\n");
++		return 0;
++	}
++
++	dev_info(priv->device, "Powering internal PHY\n");
++	ret = clk_prepare_enable(gmac->ephy_clk);
++	if (ret) {
++		dev_err(priv->device, "Cannot enable internal PHY\n");
++		return ret;
++	}
++
++	/* Make sure the EPHY is properly reseted, as U-Boot may leave
++	 * it at deasserted state, and thus it may fail to reset EMAC.
++	 */
++	reset_control_assert(gmac->rst_ephy);
++
++	ret = reset_control_deassert(gmac->rst_ephy);
++	if (ret) {
++		dev_err(priv->device, "Cannot deassert internal phy\n");
++		clk_disable_unprepare(gmac->ephy_clk);
++		return ret;
++	}
++
++	gmac->internal_phy_powered = true;
++
++	return 0;
++}
++
++static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
++{
++	if (!gmac->internal_phy_powered)
++		return 0;
++
++	clk_disable_unprepare(gmac->ephy_clk);
++	reset_control_assert(gmac->rst_ephy);
++	gmac->internal_phy_powered = false;
++	return 0;
++}
++
++/* MDIO multiplexing switch function
++ * This function is called by the mdio-mux layer when it thinks the mdio bus
++ * multiplexer needs to switch.
++ * 'current_child' is the current value of the mux register
++ * 'desired_child' is the value of the 'reg' property of the target child MDIO
++ * node.
++ * The first time this function is called, current_child == -1.
++ * If current_child == desired_child, then the mux is already set to the
++ * correct bus.
++ */
++static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
++				     void *data)
++{
++	struct stmmac_priv *priv = data;
++	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
++	u32 reg, val;
++	int ret = 0;
++	bool need_power_ephy = false;
++
++	if (current_child ^ desired_child) {
++		regmap_read(gmac->regmap, SYSCON_EMAC_REG, &reg);
++		switch (desired_child) {
++		case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
++			dev_info(priv->device, "Switch mux to internal PHY");
++			val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
++
++			need_power_ephy = true;
++			break;
++		case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
++			dev_info(priv->device, "Switch mux to external PHY");
++			val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
++			need_power_ephy = false;
++			break;
++		default:
++			dev_err(priv->device, "Invalid child ID %x\n",
++				desired_child);
++			return -EINVAL;
++		}
++		regmap_write(gmac->regmap, SYSCON_EMAC_REG, val);
++		if (need_power_ephy) {
++			ret = sun8i_dwmac_power_internal_phy(priv);
++			if (ret)
++				return ret;
++		} else {
++			sun8i_dwmac_unpower_internal_phy(gmac);
++		}
++		/* After changing syscon value, the MAC need reset or it will
++		 * use the last value (and so the last PHY set).
++		 */
++		ret = sun8i_dwmac_reset(priv);
++	}
++	return ret;
++}
++
++static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
++{
++	int ret;
++	struct device_node *mdio_mux;
++	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
++
++	mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
++	if (!mdio_mux)
++		return -ENODEV;
++
++	ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
++			    &gmac->mux_handle, priv, priv->mii);
++	return ret;
++}
++
+ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
+ {
+ 	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+@@ -648,35 +807,25 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
+ 			 "Current syscon value is not the default %x (expect %x)\n",
+ 			 val, reg);
+ 
+-	if (gmac->variant->internal_phy) {
+-		if (!gmac->use_internal_phy) {
+-			/* switch to external PHY interface */
+-			reg &= ~H3_EPHY_SELECT;
+-		} else {
+-			reg |= H3_EPHY_SELECT;
+-			reg &= ~H3_EPHY_SHUTDOWN;
+-			dev_dbg(priv->device, "Select internal_phy %x\n", reg);
+-
+-			if (of_property_read_bool(priv->plat->phy_node,
+-						  "allwinner,leds-active-low"))
+-				reg |= H3_EPHY_LED_POL;
+-			else
+-				reg &= ~H3_EPHY_LED_POL;
+-
+-			/* Force EPHY xtal frequency to 24MHz. */
+-			reg |= H3_EPHY_CLK_SEL;
+-
+-			ret = of_mdio_parse_addr(priv->device,
+-						 priv->plat->phy_node);
+-			if (ret < 0) {
+-				dev_err(priv->device, "Could not parse MDIO addr\n");
+-				return ret;
+-			}
+-			/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
+-			 * address. No need to mask it again.
+-			 */
+-			reg |= ret << H3_EPHY_ADDR_SHIFT;
++	if (gmac->variant->soc_has_internal_phy) {
++		if (of_property_read_bool(priv->plat->phy_node,
++					  "allwinner,leds-active-low"))
++			reg |= H3_EPHY_LED_POL;
++		else
++			reg &= ~H3_EPHY_LED_POL;
++
++		/* Force EPHY xtal frequency to 24MHz. */
++		reg |= H3_EPHY_CLK_SEL;
++
++		ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node);
++		if (ret < 0) {
++			dev_err(priv->device, "Could not parse MDIO addr\n");
++			return ret;
+ 		}
++		/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
++		 * address. No need to mask it again.
++		 */
++		reg |= 1 << H3_EPHY_ADDR_SHIFT;
+ 	}
+ 
+ 	if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
+@@ -746,81 +895,21 @@ static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
+ 	regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
+ }
+ 
+-static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
++static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ {
+-	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+-	int ret;
+-
+-	if (!gmac->use_internal_phy)
+-		return 0;
+-
+-	ret = clk_prepare_enable(gmac->ephy_clk);
+-	if (ret) {
+-		dev_err(priv->device, "Cannot enable ephy\n");
+-		return ret;
+-	}
+-
+-	/* Make sure the EPHY is properly reseted, as U-Boot may leave
+-	 * it at deasserted state, and thus it may fail to reset EMAC.
+-	 */
+-	reset_control_assert(gmac->rst_ephy);
++	struct sunxi_priv_data *gmac = priv;
+ 
+-	ret = reset_control_deassert(gmac->rst_ephy);
+-	if (ret) {
+-		dev_err(priv->device, "Cannot deassert ephy\n");
+-		clk_disable_unprepare(gmac->ephy_clk);
+-		return ret;
++	if (gmac->variant->soc_has_internal_phy) {
++		/* sun8i_dwmac_exit could be called with mdiomux uninit */
++		if (gmac->mux_handle)
++			mdio_mux_uninit(gmac->mux_handle);
++		if (gmac->internal_phy_powered)
++			sun8i_dwmac_unpower_internal_phy(gmac);
+ 	}
+ 
+-	return 0;
+-}
+-
+-static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
+-{
+-	if (!gmac->use_internal_phy)
+-		return 0;
+-
+-	clk_disable_unprepare(gmac->ephy_clk);
+-	reset_control_assert(gmac->rst_ephy);
+-	return 0;
+-}
+-
+-/* sun8i_power_phy() - Activate the PHY:
+- * In case of error, no need to call sun8i_unpower_phy(),
+- * it will be called anyway by sun8i_dwmac_exit()
+- */
+-static int sun8i_power_phy(struct stmmac_priv *priv)
+-{
+-	int ret;
+-
+-	ret = sun8i_dwmac_power_internal_phy(priv);
+-	if (ret)
+-		return ret;
+-
+-	ret = sun8i_dwmac_set_syscon(priv);
+-	if (ret)
+-		return ret;
+-
+-	/* After changing syscon value, the MAC need reset or it will use
+-	 * the last value (and so the last PHY set.
+-	 */
+-	ret = sun8i_dwmac_reset(priv);
+-	if (ret)
+-		return ret;
+-	return 0;
+-}
+-
+-static void sun8i_unpower_phy(struct sunxi_priv_data *gmac)
+-{
+ 	sun8i_dwmac_unset_syscon(gmac);
+-	sun8i_dwmac_unpower_internal_phy(gmac);
+-}
+-
+-static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+-{
+-	struct sunxi_priv_data *gmac = priv;
+ 
+-	sun8i_unpower_phy(gmac);
++	reset_control_put(gmac->rst_ephy);
+ 
+ 	clk_disable_unprepare(gmac->tx_clk);
+ 
+@@ -849,7 +938,7 @@ static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
+ 	if (!mac)
+ 		return NULL;
+ 
+-	ret = sun8i_power_phy(priv);
++	ret = sun8i_dwmac_set_syscon(priv);
+ 	if (ret)
+ 		return NULL;
+ 
+@@ -889,6 +978,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	struct sunxi_priv_data *gmac;
+ 	struct device *dev = &pdev->dev;
+ 	int ret;
++	struct stmmac_priv *priv;
++	struct net_device *ndev;
+ 
+ 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+ 	if (ret)
+@@ -932,29 +1023,6 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	plat_dat->interface = of_get_phy_mode(dev->of_node);
+-	if (plat_dat->interface == gmac->variant->internal_phy) {
+-		dev_info(&pdev->dev, "Will use internal PHY\n");
+-		gmac->use_internal_phy = true;
+-		gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
+-		if (IS_ERR(gmac->ephy_clk)) {
+-			ret = PTR_ERR(gmac->ephy_clk);
+-			dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret);
+-			return -EINVAL;
+-		}
+-
+-		gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
+-		if (IS_ERR(gmac->rst_ephy)) {
+-			ret = PTR_ERR(gmac->rst_ephy);
+-			if (ret == -EPROBE_DEFER)
+-				return ret;
+-			dev_err(&pdev->dev, "No EPHY reset control found %d\n",
+-				ret);
+-			return -EINVAL;
+-		}
+-	} else {
+-		dev_info(&pdev->dev, "Will use external PHY\n");
+-		gmac->use_internal_phy = false;
+-	}
+ 
+ 	/* platform data specifying hardware features and callbacks.
+ 	 * hardware features were copied from Allwinner drivers.
+@@ -973,9 +1041,34 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 
+ 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+ 	if (ret)
+-		sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
++		goto dwmac_exit;
++
++	ndev = dev_get_drvdata(&pdev->dev);
++	priv = netdev_priv(ndev);
++	/* The mux must be registered after parent MDIO
++	 * so after stmmac_dvr_probe()
++	 */
++	if (gmac->variant->soc_has_internal_phy) {
++		ret = get_ephy_nodes(priv);
++		if (ret)
++			goto dwmac_exit;
++		ret = sun8i_dwmac_register_mdio_mux(priv);
++		if (ret) {
++			dev_err(&pdev->dev, "Failed to register mux\n");
++			goto dwmac_mux;
++		}
++	} else {
++		ret = sun8i_dwmac_reset(priv);
++		if (ret)
++			goto dwmac_exit;
++	}
+ 
+ 	return ret;
++dwmac_mux:
++	sun8i_dwmac_unset_syscon(gmac);
++dwmac_exit:
++	sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
++return ret;
+ }
+ 
+ static const struct of_device_id sun8i_dwmac_match[] = {
+-- 
+2.14.3
+
+From f58f11ebb67468471ed8f232c576f348dd1a32b1 Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 24 Oct 2017 19:57:14 +0200
+Subject: [PATCH 03/11] net: stmmac: sun8i: Restore the compatibles
+
+The original dwmac-sun8i DT bindings have some issue on how to handle
+integrated PHY and was reverted in last RC of 4.13.
+But now we have a solution so we need to get back that was reverted.
+
+This patch restore compatibles about dwmac-sun8i
+This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles")
 
-This reverts commit ad4540cc5aa3dccb8e1e12458d57f8c40fae5a1c.
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
 ---
  drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++
  1 file changed, 8 insertions(+)
 
 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
-index 39c2122a4f26..fffd6d5fc907 100644
+index b3eb344bb158..e5ff734d4f9b 100644
 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
-@@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+@@ -1072,6 +1072,14 @@ return ret;
  }
  
  static const struct of_device_id sun8i_dwmac_match[] = {
@@ -28,26 +585,483 @@ index 39c2122a4f26..fffd6d5fc907 100644
  };
  MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
 -- 
-2.13.5
+2.14.3
+
+From 54678636d98cd9625f342c831015e302642bf104 Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 31 Oct 2017 09:19:08 +0100
+Subject: [PATCH 04/11] dt-bindings: net: Restore sun8i dwmac binding
+
+The original dwmac-sun8i DT bindings have some issue on how to handle
+integrated PHY and was reverted in last RC of 4.13.
+But now we have a solution so we need to get back that was reverted.
+
+This patch restore dt-bindings documentation about dwmac-sun8i
+This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac binding")
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../devicetree/bindings/net/dwmac-sun8i.txt        | 84 ++++++++++++++++++++++
+ 1 file changed, 84 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+
+diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+new file mode 100644
+index 000000000000..725f3b187886
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+@@ -0,0 +1,84 @@
++* Allwinner sun8i GMAC ethernet controller
++
++This device is a platform glue layer for stmmac.
++Please see stmmac.txt for the other unchanged properties.
++
++Required properties:
++- compatible: should be one of the following string:
++		"allwinner,sun8i-a83t-emac"
++		"allwinner,sun8i-h3-emac"
++		"allwinner,sun8i-v3s-emac"
++		"allwinner,sun50i-a64-emac"
++- reg: address and length of the register for the device.
++- interrupts: interrupt for the device
++- interrupt-names: should be "macirq"
++- clocks: A phandle to the reference clock for this device
++- clock-names: should be "stmmaceth"
++- resets: A phandle to the reset control for this device
++- reset-names: should be "stmmaceth"
++- phy-mode: See ethernet.txt
++- phy-handle: See ethernet.txt
++- #address-cells: shall be 1
++- #size-cells: shall be 0
++- syscon: A phandle to the syscon of the SoC with one of the following
++ compatible string:
++  - allwinner,sun8i-h3-system-controller
++  - allwinner,sun8i-v3s-system-controller
++  - allwinner,sun50i-a64-system-controller
++  - allwinner,sun8i-a83t-system-controller
++
++Optional properties:
++- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
++- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
++Both delay properties need to be a multiple of 100. They control the delay for
++external PHY.
++
++Optional properties for the following compatibles:
++  - "allwinner,sun8i-h3-emac",
++  - "allwinner,sun8i-v3s-emac":
++- allwinner,leds-active-low: EPHY LEDs are active low
++
++Required child node of emac:
++- mdio bus node: should be named mdio
++
++Required properties of the mdio node:
++- #address-cells: shall be 1
++- #size-cells: shall be 0
++
++The device node referenced by "phy" or "phy-handle" should be a child node
++of the mdio node. See phy.txt for the generic PHY bindings.
++
++Required properties of the phy node with the following compatibles:
++  - "allwinner,sun8i-h3-emac",
++  - "allwinner,sun8i-v3s-emac":
++- clocks: a phandle to the reference clock for the EPHY
++- resets: a phandle to the reset control for the EPHY
++
++Example:
++
++emac: ethernet@1c0b000 {
++	compatible = "allwinner,sun8i-h3-emac";
++	syscon = <&syscon>;
++	reg = <0x01c0b000 0x104>;
++	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++	interrupt-names = "macirq";
++	resets = <&ccu RST_BUS_EMAC>;
++	reset-names = "stmmaceth";
++	clocks = <&ccu CLK_BUS_EMAC>;
++	clock-names = "stmmaceth";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	mdio: mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		int_mii_phy: ethernet-phy@1 {
++			reg = <1>;
++			clocks = <&ccu CLK_BUS_EPHY>;
++			resets = <&ccu RST_BUS_EPHY>;
++		};
++	};
++};
+-- 
+2.14.3
+
+From 227bc8c6bfad58c32c7a6c3bbc13d99eb6d266c0 Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 31 Oct 2017 09:19:09 +0100
+Subject: [PATCH 05/11] dt-bindings: net: dwmac-sun8i: update documentation
+ about integrated PHY
+
+This patch add documentation about the MDIO switch used on sun8i-h3-emac
+for integrated PHY.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+---
+ .../devicetree/bindings/net/dwmac-sun8i.txt        | 147 +++++++++++++++++++--
+ 1 file changed, 135 insertions(+), 12 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+index 725f3b187886..3d6d5fa0c4d5 100644
+--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
++++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+@@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.
+ Please see stmmac.txt for the other unchanged properties.
+ 
+ Required properties:
+-- compatible: should be one of the following string:
++- compatible: must be one of the following string:
+ 		"allwinner,sun8i-a83t-emac"
+ 		"allwinner,sun8i-h3-emac"
+ 		"allwinner,sun8i-v3s-emac"
+ 		"allwinner,sun50i-a64-emac"
+ - reg: address and length of the register for the device.
+ - interrupts: interrupt for the device
+-- interrupt-names: should be "macirq"
++- interrupt-names: must be "macirq"
+ - clocks: A phandle to the reference clock for this device
+-- clock-names: should be "stmmaceth"
++- clock-names: must be "stmmaceth"
+ - resets: A phandle to the reset control for this device
+-- reset-names: should be "stmmaceth"
++- reset-names: must be "stmmaceth"
+ - phy-mode: See ethernet.txt
+ - phy-handle: See ethernet.txt
+ - #address-cells: shall be 1
+@@ -39,23 +39,42 @@ Optional properties for the following compatibles:
+ - allwinner,leds-active-low: EPHY LEDs are active low
+ 
+ Required child node of emac:
+-- mdio bus node: should be named mdio
++- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
+ 
+ Required properties of the mdio node:
+ - #address-cells: shall be 1
+ - #size-cells: shall be 0
+ 
+-The device node referenced by "phy" or "phy-handle" should be a child node
++The device node referenced by "phy" or "phy-handle" must be a child node
+ of the mdio node. See phy.txt for the generic PHY bindings.
+ 
+-Required properties of the phy node with the following compatibles:
++The following compatibles require that the emac node have a mdio-mux child
++node called "mdio-mux":
++  - "allwinner,sun8i-h3-emac"
++  - "allwinner,sun8i-v3s-emac":
++Required properties for the mdio-mux node:
++  - compatible = "allwinner,sun8i-h3-mdio-mux"
++  - mdio-parent-bus: a phandle to EMAC mdio
++  - one child mdio for the integrated mdio with the compatible
++    "allwinner,sun8i-h3-mdio-internal"
++  - one child mdio for the external mdio if present (V3s have none)
++Required properties for the mdio-mux children node:
++  - reg: 1 for internal MDIO bus, 2 for external MDIO bus
++
++The following compatibles require a PHY node representing the integrated
++PHY, under the integrated MDIO bus node if an mdio-mux node is used:
+   - "allwinner,sun8i-h3-emac",
+   - "allwinner,sun8i-v3s-emac":
++
++Additional information regarding generic multiplexer properties can be found
++at Documentation/devicetree/bindings/net/mdio-mux.txt
++
++Required properties of the integrated phy node:
+ - clocks: a phandle to the reference clock for the EPHY
+ - resets: a phandle to the reset control for the EPHY
++- Must be a child of the integrated mdio
+ 
+-Example:
+-
++Example with integrated PHY:
+ emac: ethernet@1c0b000 {
+ 	compatible = "allwinner,sun8i-h3-emac";
+ 	syscon = <&syscon>;
+@@ -72,13 +91,117 @@ emac: ethernet@1c0b000 {
+ 	phy-handle = <&int_mii_phy>;
+ 	phy-mode = "mii";
+ 	allwinner,leds-active-low;
++
++	mdio: mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "snps,dwmac-mdio";
++	};
++
++	mdio-mux {
++		compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		mdio-parent-bus = <&mdio>;
++
++		int_mdio: mdio@1 {
++			compatible = "allwinner,sun8i-h3-mdio-internal";
++			reg = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			int_mii_phy: ethernet-phy@1 {
++				reg = <1>;
++				clocks = <&ccu CLK_BUS_EPHY>;
++				resets = <&ccu RST_BUS_EPHY>;
++				phy-is-integrated;
++			};
++		};
++		ext_mdio: mdio@2 {
++			reg = <2>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++	};
++};
++
++Example with external PHY:
++emac: ethernet@1c0b000 {
++	compatible = "allwinner,sun8i-h3-emac";
++	syscon = <&syscon>;
++	reg = <0x01c0b000 0x104>;
++	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++	interrupt-names = "macirq";
++	resets = <&ccu RST_BUS_EMAC>;
++	reset-names = "stmmaceth";
++	clocks = <&ccu CLK_BUS_EMAC>;
++	clock-names = "stmmaceth";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii";
++	allwinner,leds-active-low;
++
++	mdio: mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "snps,dwmac-mdio";
++	};
++
++	mdio-mux {
++		compatible = "allwinner,sun8i-h3-mdio-mux";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		mdio-parent-bus = <&mdio>;
++
++		int_mdio: mdio@1 {
++			compatible = "allwinner,sun8i-h3-mdio-internal";
++			reg = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			int_mii_phy: ethernet-phy@1 {
++				reg = <1>;
++				clocks = <&ccu CLK_BUS_EPHY>;
++				resets = <&ccu RST_BUS_EPHY>;
++			};
++		};
++		ext_mdio: mdio@2 {
++			reg = <2>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			ext_rgmii_phy: ethernet-phy@1 {
++				reg = <1>;
++			};
++		}:
++	};
++};
++
++Example with SoC without integrated PHY
++
++emac: ethernet@1c0b000 {
++	compatible = "allwinner,sun8i-a83t-emac";
++	syscon = <&syscon>;
++	reg = <0x01c0b000 0x104>;
++	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++	interrupt-names = "macirq";
++	resets = <&ccu RST_BUS_EMAC>;
++	reset-names = "stmmaceth";
++	clocks = <&ccu CLK_BUS_EMAC>;
++	clock-names = "stmmaceth";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii";
++
+ 	mdio: mdio {
++		compatible = "snps,dwmac-mdio";
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-		int_mii_phy: ethernet-phy@1 {
++		ext_rgmii_phy: ethernet-phy@1 {
+ 			reg = <1>;
+-			clocks = <&ccu CLK_BUS_EPHY>;
+-			resets = <&ccu RST_BUS_EPHY>;
+ 		};
+ 	};
+ };
+-- 
+2.14.3
+
+From 1de79efa35a1130c7a085f62b9d9b666d79b9a89 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Wed, 1 Nov 2017 14:04:20 +0000
+Subject: [PATCH 06/11] arm: dts: sunxi: h3/h5: Restore EMAC changes
+
+The original dwmac-sun8i DT bindings have some issue on how to handle
+integrated PHY and was reverted in last RC of 4.13.
+But now we have a solution so we need to get back that was reverted.
+
+This patch restore sunxi-h3-h5.dtsi
+This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+index 11240a8313c2..d38282b9e5d4 100644
+--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+@@ -391,6 +391,32 @@
+ 			clocks = <&osc24M>;
+ 		};
+ 
++		emac: ethernet@1c30000 {
++			compatible = "allwinner,sun8i-h3-emac";
++			syscon = <&syscon>;
++			reg = <0x01c30000 0x10000>;
++			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "macirq";
++			resets = <&ccu RST_BUS_EMAC>;
++			reset-names = "stmmaceth";
++			clocks = <&ccu CLK_BUS_EMAC>;
++			clock-names = "stmmaceth";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			mdio: mdio {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				int_mii_phy: ethernet-phy@1 {
++					compatible = "ethernet-phy-ieee802.3-c22";
++					reg = <1>;
++					clocks = <&ccu CLK_BUS_EPHY>;
++					resets = <&ccu RST_BUS_EPHY>;
++				};
++			};
++		};
++
+ 		spi0: spi@01c68000 {
+ 			compatible = "allwinner,sun8i-h3-spi";
+ 			reg = <0x01c68000 0x1000>;
+-- 
+2.14.3
+
+From 65233cba93184e0efa8d94f907d65af947d197a1 Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 31 Oct 2017 09:19:11 +0100
+Subject: [PATCH 07/11] ARM: dts: sunxi: h3/h5: represent the mdio switch used
+ by sun8i-h3-emac
+
+Since dwmac-sun8i could use either an integrated PHY or an external PHY
+(which could be at same MDIO address), we need to represent this selection
+by a MDIO switch.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+---
+ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +++++++++++++++++++++++++++----
+ 1 file changed, 27 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+index d38282b9e5d4..2721b39c1875 100644
+--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+@@ -408,11 +408,34 @@
+ 			mdio: mdio {
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+-				int_mii_phy: ethernet-phy@1 {
+-					compatible = "ethernet-phy-ieee802.3-c22";
++				compatible = "snps,dwmac-mdio";
++			};
++
++			mdio-mux {
++				compatible = "allwinner,sun8i-h3-mdio-mux";
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mdio-parent-bus = <&mdio>;
++				/* Only one MDIO is usable at the time */
++				internal_mdio: mdio@1 {
++					compatible = "allwinner,sun8i-h3-mdio-internal";
+ 					reg = <1>;
+-					clocks = <&ccu CLK_BUS_EPHY>;
+-					resets = <&ccu RST_BUS_EPHY>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					int_mii_phy: ethernet-phy@1 {
++						compatible = "ethernet-phy-ieee802.3-c22";
++						reg = <1>;
++						clocks = <&ccu CLK_BUS_EPHY>;
++						resets = <&ccu RST_BUS_EPHY>;
++					};
++				};
++
++				external_mdio: mdio@2 {
++					reg = <2>;
++					#address-cells = <1>;
++					#size-cells = <0>;
+ 				};
+ 			};
+ 		};
+-- 
+2.14.3
 
-From fa4788d88903c1e535d034c3dd3fcd386685a02c Mon Sep 17 00:00:00 2001
+From b705315d36dbe1b31062f30c987b3a502b437c85 Mon Sep 17 00:00:00 2001
 From: Peter Robinson <pbrobinson@gmail.com>
-Date: Mon, 4 Sep 2017 13:04:41 +0100
-Subject: [PATCH 2/4] Revert "arm: dts: sunxi: Revert EMAC changes"
+Date: Wed, 1 Nov 2017 14:08:45 +0000
+Subject: [PATCH 08/11] ARM: dts: sunxi: Restore EMAC changes (boards)
+
+The original dwmac-sun8i DT bindings have some issue on how to handle
+integrated PHY and was reverted in last RC of 4.13.
+But now we have a solution so we need to get back that was reverted.
+
+This patch restore all boards DT about dwmac-sun8i
+This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
 
-This reverts commit fe45174b72aead678da581bab9e9a37c9b26a070.
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
 ---
- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts |  9 ++++++++
- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts   | 19 +++++++++++++++++
- arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts         |  7 ++++++
- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts         |  8 +++++++
- arch/arm/boot/dts/sun8i-h3-orangepi-one.dts       |  8 +++++++
+ arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts |  9 +++++++++
+ arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts   | 19 +++++++++++++++++++
+ arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts     | 19 +++++++++++++++++++
+ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts         |  7 +++++++
+ arch/arm/boot/dts/sun8i-h3-orangepi-2.dts         |  8 ++++++++
+ arch/arm/boot/dts/sun8i-h3-orangepi-one.dts       |  8 ++++++++
  arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts   |  5 +++++
- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts        |  8 +++++++
- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts      | 22 +++++++++++++++++++
- arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts    | 16 ++++++++++++++
- arch/arm/boot/dts/sunxi-h3-h5.dtsi                | 26 +++++++++++++++++++++++
- 10 files changed, 128 insertions(+)
+ arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts        |  8 ++++++++
+ arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts      | 22 ++++++++++++++++++++++
+ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts    | 16 ++++++++++++++++
+ 10 files changed, 121 insertions(+)
 
 diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
 index b1502df7b509..6713d0f2b3f4 100644
@@ -77,7 +1091,7 @@ index b1502df7b509..6713d0f2b3f4 100644
  	pinctrl-names = "default";
  	pinctrl-0 = <&mmc0_pins_a>;
 diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
-index a337af1de322..d756ff825116 100644
+index a337af1de322..3f95d806355b 100644
 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
 +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
 @@ -52,6 +52,7 @@
@@ -88,7 +1102,7 @@ index a337af1de322..d756ff825116 100644
  		serial0 = &uart0;
  		serial1 = &uart1;
  	};
-@@ -114,12 +115,30 @@
+@@ -114,6 +115,24 @@
  	status = "okay";
  };
  
@@ -103,22 +1117,43 @@ index a337af1de322..d756ff825116 100644
 +	status = "okay";
 +};
 +
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0>;
++	};
++};
++
  &ir {
  	pinctrl-names = "default";
  	pinctrl-0 = <&ir_pins_a>;
+diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+index 8ddd1b2cc097..ef0371811296 100644
+--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+@@ -62,3 +62,22 @@
+ &ohci2 {
  	status = "okay";
  };
- 
-+&mdio {
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii";
++
++	allwinner,leds-active-low;
++
++	status = "okay";
++};
++
++&external_mdio {
 +	ext_rgmii_phy: ethernet-phy@1 {
 +		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <0>;
++		reg = <7>;
 +	};
 +};
-+
- &mmc0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
 diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
 index 8d2cc6e9a03f..78f6c24952dd 100644
 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -229,7 +1264,7 @@ index 1a044b17d6c6..998b60f8d295 100644
  	pinctrl-names = "default";
  	pinctrl-0 = <&ir_pins_a>;
 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
-index 828ae7a526d9..331ed683ac62 100644
+index 828ae7a526d9..3002c025e187 100644
 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
 @@ -47,6 +47,10 @@
@@ -258,7 +1293,7 @@ index 828ae7a526d9..331ed683ac62 100644
 +	status = "okay";
 +};
 +
-+&mdio {
++&external_mdio {
 +	ext_rgmii_phy: ethernet-phy@1 {
 +		compatible = "ethernet-phy-ieee802.3-c22";
 +		reg = <0>;
@@ -269,7 +1304,7 @@ index 828ae7a526d9..331ed683ac62 100644
  	pinctrl-names = "default";
  	pinctrl-0 = <&mmc2_8bit_pins>;
 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
-index 97920b12a944..80026f3caafc 100644
+index 97920b12a944..6dbf7b2e0c13 100644
 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
 @@ -61,3 +61,19 @@
@@ -286,22 +1321,187 @@ index 97920b12a944..80026f3caafc 100644
 +	status = "okay";
 +};
 +
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
+-- 
+2.14.3
+
+From 516b88bfa40cf54732d2ba5e689fdf592a742ec3 Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 31 Oct 2017 09:19:13 +0100
+Subject: [PATCH 09/11] arm64: dts: allwinner: A64: Restore EMAC changes
+
+The original dwmac-sun8i DT bindings have some issue on how to handle
+integrated PHY and was reverted in last RC of 4.13.
+But now we have a solution so we need to get back that was reverted.
+
+This patch restore arm64 DT about dwmac-sun8i for A64
+This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts   | 16 ++++++++++++++++
+ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts    | 15 +++++++++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts  | 17 +++++++++++++++++
+ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts    | 16 ++++++++++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi        | 20 ++++++++++++++++++++
+ 5 files changed, 84 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+index d347f52e27f6..45bdbfb96126 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+@@ -51,6 +51,7 @@
+ 	compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
+ 
+ 	aliases {
++		ethernet0 = &emac;
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
+ 	};
+@@ -69,6 +70,14 @@
+ 	status = "okay";
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	status = "okay";
++};
++
+ &i2c1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2c1_pins>;
+@@ -79,6 +88,13 @@
+ 	bias-pull-up;
+ };
+ 
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
+ &mmc0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc0_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+index f82ccf332c0f..24f1aac366d6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+@@ -48,3 +48,18 @@
+ 
+ 	/* TODO: Camera, touchscreen, etc. */
+ };
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	status = "okay";
++};
++
 +&mdio {
 +	ext_rgmii_phy: ethernet-phy@1 {
 +		compatible = "ethernet-phy-ieee802.3-c22";
 +		reg = <1>;
 +	};
 +};
-diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
-index 11240a8313c2..d38282b9e5d4 100644
---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
-+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
-@@ -391,6 +391,32 @@
- 			clocks = <&osc24M>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index d06e34b5d192..806442d3e846 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -51,6 +51,7 @@
+ 	compatible = "pine64,pine64", "allwinner,sun50i-a64";
+ 
+ 	aliases {
++		ethernet0 = &emac;
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
+ 		serial2 = &uart2;
+@@ -71,6 +72,15 @@
+ 	status = "okay";
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&ext_rmii_phy1>;
++	status = "okay";
++
++};
++
+ &i2c1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2c1_pins>;
+@@ -81,6 +91,13 @@
+ 	bias-pull-up;
+ };
+ 
++&mdio {
++	ext_rmii_phy1: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
+ &mmc0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc0_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+index 17ccc12b58df..0eb2acedf8c3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -53,6 +53,7 @@
+ 		     "allwinner,sun50i-a64";
+ 
+ 	aliases {
++		ethernet0 = &emac;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -76,6 +77,21 @@
+ 	status = "okay";
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
+ &mmc2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc2_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 8c8db1b057df..50f17bab0c07 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -449,6 +449,26 @@
+ 			#size-cells = <0>;
  		};
  
 +		emac: ethernet@1c30000 {
-+			compatible = "allwinner,sun8i-h3-emac";
++			compatible = "allwinner,sun50i-a64-emac";
 +			syscon = <&syscon>;
 +			reg = <0x01c30000 0x10000>;
 +			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -310,129 +1510,282 @@ index 11240a8313c2..d38282b9e5d4 100644
 +			reset-names = "stmmaceth";
 +			clocks = <&ccu CLK_BUS_EMAC>;
 +			clock-names = "stmmaceth";
++			status = "disabled";
 +			#address-cells = <1>;
 +			#size-cells = <0>;
-+			status = "disabled";
 +
 +			mdio: mdio {
 +				#address-cells = <1>;
 +				#size-cells = <0>;
-+				int_mii_phy: ethernet-phy@1 {
-+					compatible = "ethernet-phy-ieee802.3-c22";
-+					reg = <1>;
-+					clocks = <&ccu CLK_BUS_EPHY>;
-+					resets = <&ccu RST_BUS_EPHY>;
-+				};
 +			};
 +		};
 +
- 		spi0: spi@01c68000 {
- 			compatible = "allwinner,sun8i-h3-spi";
- 			reg = <0x01c68000 0x1000>;
+ 		gic: interrupt-controller@1c81000 {
+ 			compatible = "arm,gic-400";
+ 			reg = <0x01c81000 0x1000>,
 -- 
-2.13.5
+2.14.3
 
-From 11190f020b948ccdf15061b6df8cc2836a2afcb1 Mon Sep 17 00:00:00 2001
-From: Peter Robinson <pbrobinson@gmail.com>
-Date: Mon, 4 Sep 2017 13:04:55 +0100
-Subject: [PATCH 4/4] Revert "dt-bindings: net: Revert sun8i dwmac binding"
+From 070173449eb88e9cf9c91889c77f53616911f4d0 Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 31 Oct 2017 09:19:14 +0100
+Subject: [PATCH 10/11] arm64: dts: allwinner: H5: Restore EMAC changes
+
+The original dwmac-sun8i DT bindings have some issue on how to handle
+integrated PHY and was reverted in last RC of 4.13.
+But now we have a solution so we need to get back that was reverted.
 
-This reverts commit 8aa33ec2f4812d1ee96f4c02ba013f5b9c514343.
+This patch restore arm64 DT about dwmac-sun8i for H5
+This reverts a part of commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
 ---
- .../devicetree/bindings/net/dwmac-sun8i.txt        | 84 ++++++++++++++++++++++
- 1 file changed, 84 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++
+ .../arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++
+ .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts     | 17 +++++++++++++++++
+ 3 files changed, 51 insertions(+)
 
-diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
-new file mode 100644
-index 000000000000..725f3b187886
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
-@@ -0,0 +1,84 @@
-+* Allwinner sun8i GMAC ethernet controller
-+
-+This device is a platform glue layer for stmmac.
-+Please see stmmac.txt for the other unchanged properties.
-+
-+Required properties:
-+- compatible: should be one of the following string:
-+		"allwinner,sun8i-a83t-emac"
-+		"allwinner,sun8i-h3-emac"
-+		"allwinner,sun8i-v3s-emac"
-+		"allwinner,sun50i-a64-emac"
-+- reg: address and length of the register for the device.
-+- interrupts: interrupt for the device
-+- interrupt-names: should be "macirq"
-+- clocks: A phandle to the reference clock for this device
-+- clock-names: should be "stmmaceth"
-+- resets: A phandle to the reset control for this device
-+- reset-names: should be "stmmaceth"
-+- phy-mode: See ethernet.txt
-+- phy-handle: See ethernet.txt
-+- #address-cells: shall be 1
-+- #size-cells: shall be 0
-+- syscon: A phandle to the syscon of the SoC with one of the following
-+ compatible string:
-+  - allwinner,sun8i-h3-system-controller
-+  - allwinner,sun8i-v3s-system-controller
-+  - allwinner,sun50i-a64-system-controller
-+  - allwinner,sun8i-a83t-system-controller
-+
-+Optional properties:
-+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
-+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
-+Both delay properties need to be a multiple of 100. They control the delay for
-+external PHY.
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+index 1c2387bd5df6..6eb8092d8e57 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+@@ -50,6 +50,7 @@
+ 	compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
+ 
+ 	aliases {
++		ethernet0 = &emac;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -108,6 +109,22 @@
+ 	status = "okay";
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii";
++	status = "okay";
++};
 +
-+Optional properties for the following compatibles:
-+  - "allwinner,sun8i-h3-emac",
-+  - "allwinner,sun8i-v3s-emac":
-+- allwinner,leds-active-low: EPHY LEDs are active low
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@7 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <7>;
++	};
++};
 +
-+Required child node of emac:
-+- mdio bus node: should be named mdio
+ &mmc0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+index 4f77c8470f6c..a0ca925175aa 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -59,6 +59,7 @@
+ 	};
+ 
+ 	aliases {
++		ethernet0 = &emac;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -136,6 +137,22 @@
+ 	status = "okay";
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii";
++	status = "okay";
++};
 +
-+Required properties of the mdio node:
-+- #address-cells: shall be 1
-+- #size-cells: shall be 0
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
 +
-+The device node referenced by "phy" or "phy-handle" should be a child node
-+of the mdio node. See phy.txt for the generic PHY bindings.
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&ir_pins_a>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 6be06873e5af..b47790650144 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -54,6 +54,7 @@
+ 	compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
+ 
+ 	aliases {
++		ethernet0 = &emac;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -143,6 +144,22 @@
+ 	status = "okay";
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii";
++	status = "okay";
++};
 +
-+Required properties of the phy node with the following compatibles:
-+  - "allwinner,sun8i-h3-emac",
-+  - "allwinner,sun8i-v3s-emac":
-+- clocks: a phandle to the reference clock for the EPHY
-+- resets: a phandle to the reset control for the EPHY
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
 +
-+Example:
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&ir_pins_a>;
+-- 
+2.14.3
+
+From 63118a9f7808a0a67c23e7d276138c996e094eae Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 31 Oct 2017 09:19:15 +0100
+Subject: [PATCH 11/11] arm64: dts: allwinner: add snps, dwmac-mdio compatible
+ to emac/mdio
+
+stmmac bindings docs said that its mdio node must have
+compatible = "snps,dwmac-mdio";
+Since dwmac-sun8i does not have any good reasons to not doing it, all
+their MDIO node must have it.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 50f17bab0c07..8fd75c95937a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -464,6 +464,7 @@
+ 			#size-cells = <0>;
+ 
+ 			mdio: mdio {
++				compatible = "snps,dwmac-mdio";
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+ 			};
+-- 
+2.14.3
+
+From patchwork Fri Nov 10 09:26:54 2017
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: arm64: allwinner: a64: add Ethernet PHY regulator for several boards
+From: Icenowy Zheng <icenowy@aosc.io>
+X-Patchwork-Id: 10052659
+Message-Id: <20171110092654.10746-1-icenowy@aosc.io>
+To: Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>
+Cc: linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, Icenowy Zheng <icenowy@aosc.io>
+Date: Fri, 10 Nov 2017 17:26:54 +0800
+
+On several A64 boards the Ethernet PHY is powered by the DC1SW regulator
+on the AXP803 PMIC.
+
+Add phy-handle property to these boards' emac node.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Acked-by: Corentin LABBE <clabbe.montjoie@gmail.com>
+Tested-by: Corentin LABBE <clabbe.montjoie@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts     | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts           | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 1 +
+ 3 files changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+index 45bdbfb96126..4a8d3f83a36e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+@@ -75,6 +75,7 @@
+ 	pinctrl-0 = <&rgmii_pins>;
+ 	phy-mode = "rgmii";
+ 	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_dc1sw>;
+ 	status = "okay";
+ };
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index 806442d3e846..604cdaedac38 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -77,6 +77,7 @@
+ 	pinctrl-0 = <&rmii_pins>;
+ 	phy-mode = "rmii";
+ 	phy-handle = <&ext_rmii_phy1>;
++	phy-supply = <&reg_dc1sw>;
+ 	status = "okay";
+ 
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+index 0eb2acedf8c3..a053a6ac5267 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -82,6 +82,7 @@
+ 	pinctrl-0 = <&rgmii_pins>;
+ 	phy-mode = "rgmii";
+ 	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_dc1sw>;
+ 	status = "okay";
+ };
+ 
+From 79e7d6c8bfe67fce8c8fe4953e74ce7f420dd732 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Tue, 21 Nov 2017 15:43:19 +0000
+Subject: [PATCH] ARM: dts: sunxi: sun8i-h3-nanopi-m1-plus: Add missing
+ regulator
+
+This patch add the missing regulator for sun8i-h3-nanopi-m1-plus.
+
+Fixes: ("ARM: dts: sunxi: Restore EMAC changes (boards)")
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+---
+ arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+index ef0371811296..738ef1d9e844 100644
+--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+@@ -45,6 +45,17 @@
+ / {
+ 	model = "FriendlyArm NanoPi M1 Plus";
+ 	compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
 +
-+emac: ethernet@1c0b000 {
-+	compatible = "allwinner,sun8i-h3-emac";
-+	syscon = <&syscon>;
-+	reg = <0x01c0b000 0x104>;
-+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-+	interrupt-names = "macirq";
-+	resets = <&ccu RST_BUS_EMAC>;
-+	reset-names = "stmmaceth";
-+	clocks = <&ccu CLK_BUS_EMAC>;
-+	clock-names = "stmmaceth";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
++        reg_gmac_3v3: gmac-3v3 {
++                compatible = "regulator-fixed";
++                regulator-name = "gmac-3v3";
++                regulator-min-microvolt = <3300000>;
++                regulator-max-microvolt = <3300000>;
++                startup-delay-us = <100000>;
++                enable-active-high;
++                gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++        };
 +
-+	phy-handle = <&int_mii_phy>;
-+	phy-mode = "mii";
-+	allwinner,leds-active-low;
-+	mdio: mdio {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		int_mii_phy: ethernet-phy@1 {
-+			reg = <1>;
-+			clocks = <&ccu CLK_BUS_EPHY>;
-+			resets = <&ccu RST_BUS_EPHY>;
-+		};
-+	};
-+};
+ };
+ 
+ &ehci1 {
 -- 
-2.13.5
+2.14.3
 
diff --git a/arm64-Revert-allwinner-a64-pine64-Use-dcdc1-regulato.patch b/arm64-Revert-allwinner-a64-pine64-Use-dcdc1-regulato.patch
new file mode 100644
index 000000000..33f9271b7
--- /dev/null
+++ b/arm64-Revert-allwinner-a64-pine64-Use-dcdc1-regulato.patch
@@ -0,0 +1,41 @@
+From 90e388ca5d8bbee022f9ed5fc24137b31579fa6e Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Wed, 22 Nov 2017 15:52:36 +0000
+Subject: [PATCH] Revert "arm64: allwinner: a64: pine64: Use dcdc1 regulator
+ for mmc0"
+
+This reverts commit 3f241bfa60bdc9c4fde63fa6664a8ce00fd668c6.
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index d06e34b5d192..caf8b6fbe5e3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -61,6 +61,13 @@
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
++
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
+ };
+ 
+ &ehci0 {
+@@ -84,7 +91,7 @@
+ &mmc0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc0_pins>;
+-	vmmc-supply = <&reg_dcdc1>;
++	vmmc-supply = <&reg_vcc3v3>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ 	cd-inverted;
+ 	disable-wp;
+-- 
+2.14.3
+
diff --git a/kernel.spec b/kernel.spec
index c355e4e0c..e76bb696f 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -17,7 +17,7 @@ Summary: The Linux kernel
 %else
 %global signkernel 0
 %global signmodules 1
-%global zipmodules 0
+%global zipmodules 1
 %endif
 
 %if %{zipmodules}
@@ -595,10 +595,12 @@ Patch303: ARM-tegra-usb-no-reset.patch
 
 Patch304: allwinner-net-emac.patch
 
+Patch305: arm64-Revert-allwinner-a64-pine64-Use-dcdc1-regulato.patch
+
 # https://www.spinics.net/lists/arm-kernel/msg554183.html
-Patch305: arm-imx6-hummingboard2.patch
+Patch306: arm-imx6-hummingboard2.patch
 
-Patch306: arm64-Add-option-of-13-for-FORCE_MAX_ZONEORDER.patch
+Patch307: arm64-Add-option-of-13-for-FORCE_MAX_ZONEORDER.patch
 
 # https://patchwork.kernel.org/patch/9820417/
 Patch310: qcom-msm89xx-fixes.patch
@@ -2207,6 +2209,9 @@ fi
 #
 #
 %changelog
+* Mon Nov 13 2017 Peter Robinson <pbrobinson@fedoraproject.org>
+- Compress modules on all arches
+
 * Tue Nov 21 2017 Justin M. Forbes <jforbes@fedoraproject.org> - 4.14.1-300
 - Linux v4.14.1