drop patch for pre-prod qcom hardware

2 files changed, 6 insertions, 68 deletions

diff --git a/kernel.spec b/kernel.spec
index 40f5398d5..6b0b129c0 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -579,24 +579,21 @@ Patch211: drm-i915-hush-check-crtc-state.patch
 
 # 300 - ARM patches
 
-# a tempory patch for QCOM hardware enablement. Will be gone by F-26 GA
-Patch301: qcom-QDF2432-tmp-errata.patch
-
 # http://www.spinics.net/lists/linux-tegra/msg26029.html
-Patch302: usb-phy-tegra-Add-38.4MHz-clock-table-entry.patch
+Patch301: usb-phy-tegra-Add-38.4MHz-clock-table-entry.patch
 
 # Fix OMAP4 (pandaboard)
-Patch303: arm-revert-mmc-omap_hsmmc-Use-dma_request_chan-for-reque.patch
+Patch302: arm-revert-mmc-omap_hsmmc-Use-dma_request_chan-for-reque.patch
 
 # http://patchwork.ozlabs.org/patch/587554/
-Patch304: ARM-tegra-usb-no-reset.patch
+Patch303: ARM-tegra-usb-no-reset.patch
 
-Patch305: allwinner-net-emac.patch
+Patch304: allwinner-net-emac.patch
 
 # https://www.spinics.net/lists/arm-kernel/msg554183.html
-Patch307: arm-imx6-hummingboard2.patch
+Patch305: arm-imx6-hummingboard2.patch
 
-Patch308: arm64-Add-option-of-13-for-FORCE_MAX_ZONEORDER.patch
+Patch306: arm64-Add-option-of-13-for-FORCE_MAX_ZONEORDER.patch
 
 # https://patchwork.kernel.org/patch/9815555/
 # https://patchwork.kernel.org/patch/9815651/
diff --git a/qcom-QDF2432-tmp-errata.patch b/qcom-QDF2432-tmp-errata.patch
deleted file mode 100644
index f7ace4787..000000000
--- a/qcom-QDF2432-tmp-errata.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From edc7986d4d405daebaf2f66269b353da579fce5f Mon Sep 17 00:00:00 2001
-From: Christopher Covington <cov@codeaurora.org>
-Date: Tue, 31 May 2016 16:19:02 -0400
-Subject: arm64: Workaround for QDF2432 ID_AA64 SR accesses
-
-The ARMv8.0 architecture reserves several system register encodings for
-future use. These encodings should behave as read-only and always return
-zero on a read. As described in Errata 94, the CPU cores in the QDF2432
-errantly cause an instruction abort if an AArch64 MRS instruction attempts
-to read any of the following system register encodings:
-
-	Op0, Op1, CRn, CRm,        Op2
-	3,   0,   C0,  [C4-C7],    [2-3, 6-7]
-	3,   0,   C0,  C3,         [3-7]
-	3,   0,   C0,  [C4,C6,C7], [4-5]
-	3,   0,   C0,  C2,         [6-7]
-
-Naively projecting ARMv8.0 names, this space includes:
-
-	ID_AA64PFR[2-7]_EL1
-	ID_AA64DFR[2-3]_EL1
-	ID_AA64AFR[2-3]_EL1
-	ID_AA64ISAR[2-7]_EL1
-	ID_AA64MMFR[2-7]_EL1
-
-As of v4.8-rc2, Linux only attempts to query one register in this space,
-ID_AA64MMFR2_EL1. As simple workaround, skip that access when the affected
-MIDR is detected.
-
-Signed-off-by: Christopher Covington <cov@codeaurora.org>
----
- arch/arm64/kernel/cpuinfo.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
-index ed1b84f..790de6b 100644
---- a/arch/arm64/kernel/cpuinfo.c
-+++ b/arch/arm64/kernel/cpuinfo.c
-@@ -325,6 +325,8 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
- 
- static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
- {
-+	bool qdf2432_cpu = read_cpuid_id() == 0x510f2811;
-+
- 	info->reg_cntfrq = arch_timer_get_cntfrq();
- 	info->reg_ctr = read_cpuid_cachetype();
- 	info->reg_dczid = read_cpuid(DCZID_EL0);
-@@ -337,7 +339,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
- 	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
- 	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
- 	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
--	info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
-+	info->reg_id_aa64mmfr2 = qdf2432_cpu ? 0 : read_cpuid(ID_AA64MMFR2_EL1);
- 	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
- 	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
- 
--- 
-cgit v0.12
-