Linux v4.7.2

1 files changed, 67 insertions, 86 deletions

diff --git a/0015-drm-i915-gen9-Calculate-watermarks-during-atomic-che.patch b/0015-drm-i915-gen9-Calculate-watermarks-during-atomic-che.patch
index b8f602e0e..691b6b985 100644
--- a/0015-drm-i915-gen9-Calculate-watermarks-during-atomic-che.patch
+++ b/0015-drm-i915-gen9-Calculate-watermarks-during-atomic-che.patch
@@ -1,80 +1,70 @@
-From 71136125cc79dab464a0139dbf0c02891aa9ce6e Mon Sep 17 00:00:00 2001
-From: Fedora Kernel Team <kernel-team@fedoraproject.org>
-Date: Mon, 20 Jun 2016 12:41:46 +0200
+From 664f87c5bfcc7798bd5b16e14792f1e9ba2956ea Mon Sep 17 00:00:00 2001
+From: Matt Roper <matthew.d.roper@intel.com>
+Date: Thu, 12 May 2016 15:11:40 -0700
 Subject: [PATCH 15/17] drm/i915/gen9: Calculate watermarks during atomic
  'check' (v2)
 
-Upstream: since drm-intel-next-2016-05-22
-commit 734fa01f3a17ac80d2d53cee0b05b246c03df0e4
+Moving watermark calculation into the check phase will allow us to to
+reject display configurations for which there are no valid watermark
+values before we start trying to program the hardware (although those
+tests will come in a subsequent patch).
 
-Author:     Matt Roper <matthew.d.roper@intel.com>
-AuthorDate: Thu May 12 15:11:40 2016 -0700
-Commit:     Matt Roper <matthew.d.roper@intel.com>
-CommitDate: Fri May 13 07:35:48 2016 -0700
+Another advantage of moving this calculation to the check phase is that
+we can calculate the watermarks in a single shot as part of the atomic
+transaction.  The watermark interfaces we inherited from our legacy
+modesetting days are a bit broken in the atomic design because they use
+per-crtc entry points but actually re-calculate and re-program something
+that is really more of a global state.  That worked okay in the legacy
+modesetting world because operations only ever updated a single CRTC at
+a time.  However in the atomic world, a transaction can involve multiple
+CRTC's, which means we wind up computing and programming the watermarks
+NxN times (where N is the number of CRTC's involved).  With this patch
+we eliminate the redundant re-calculation of watermark data for atomic
+states (which was the cause of the WARN_ON(!wm_changed) problems that
+have plagued us for a while).
 
-    drm/i915/gen9: Calculate watermarks during atomic 'check' (v2)
+We still need to work on the 'commit' side of watermark handling so that
+we aren't doing redundant NxN programming of watermarks, but that's
+content for future patches.
 
-    Moving watermark calculation into the check phase will allow us to to
-    reject display configurations for which there are no valid watermark
-    values before we start trying to program the hardware (although those
-    tests will come in a subsequent patch).
+v2:
+ - Bail out of skl_write_wm_values() if the CRTC isn't active.  Now that
+   we set dirty_pipes to ~0 if the active pipes change (because
+   we need to deal with DDB changes), we can now wind up here for
+   disabled pipes, whereas we couldn't before.
 
-    Another advantage of moving this calculation to the check phase is that
-    we can calculate the watermarks in a single shot as part of the atomic
-    transaction.  The watermark interfaces we inherited from our legacy
-    modesetting days are a bit broken in the atomic design because they use
-    per-crtc entry points but actually re-calculate and re-program something
-    that is really more of a global state.  That worked okay in the legacy
-    modesetting world because operations only ever updated a single CRTC at
-    a time.  However in the atomic world, a transaction can involve multiple
-    CRTC's, which means we wind up computing and programming the watermarks
-    NxN times (where N is the number of CRTC's involved).  With this patch
-    we eliminate the redundant re-calculation of watermark data for atomic
-    states (which was the cause of the WARN_ON(!wm_changed) problems that
-    have plagued us for a while).
-
-    We still need to work on the 'commit' side of watermark handling so that
-    we aren't doing redundant NxN programming of watermarks, but that's
-    content for future patches.
-
-    v2:
-     - Bail out of skl_write_wm_values() if the CRTC isn't active.  Now that
-       we set dirty_pipes to ~0 if the active pipes change (because
-       we need to deal with DDB changes), we can now wind up here for
-       disabled pipes, whereas we couldn't before.
-
-    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89055
-    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
-    Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
-    Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
-    Tested-by: Daniel Stone <daniels@collabora.com>
-    Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
-    Link: http://patchwork.freedesktop.org/patch/msgid/1463091100-13747-1-git-send-email-matthew.d.roper@intel.com
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89055
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
+Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
+Tested-by: Daniel Stone <daniels@collabora.com>
+Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/1463091100-13747-1-git-send-email-matthew.d.roper@intel.com
 ---
  drivers/gpu/drm/i915/intel_display.c |   2 +-
- drivers/gpu/drm/i915/intel_drv.h     |  14 +++-
- drivers/gpu/drm/i915/intel_pm.c      | 135 ++++++++++++-----------------------
- 3 files changed, 61 insertions(+), 90 deletions(-)
+ drivers/gpu/drm/i915/intel_drv.h     |   2 +-
+ drivers/gpu/drm/i915/intel_pm.c      | 140 +++++++++++++----------------------
+ 3 files changed, 54 insertions(+), 90 deletions(-)
 
 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
-index 9ac2346..1726ea4 100644
+index 2190bac..a75daac 100644
 --- a/drivers/gpu/drm/i915/intel_display.c
 +++ b/drivers/gpu/drm/i915/intel_display.c
-@@ -13522,7 +13522,7 @@ static int intel_atomic_commit(struct drm_device *dev,
+@@ -13627,7 +13627,7 @@ static int intel_atomic_commit(struct drm_device *dev,
  	drm_atomic_helper_swap_state(dev, state);
- 	dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
+ 	dev_priv->wm.config = intel_state->wm_config;
  	dev_priv->wm.distrust_bios_wm = false;
 -	dev_priv->wm.skl_results.ddb = intel_state->ddb;
 +	dev_priv->wm.skl_results = intel_state->wm_results;
+ 	intel_shared_dpll_commit(state);
  
  	if (intel_state->modeset) {
- 		memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
 diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
-index 4d6336a..e5543b8 100644
+index 2218290..ab0be7a 100644
 --- a/drivers/gpu/drm/i915/intel_drv.h
 +++ b/drivers/gpu/drm/i915/intel_drv.h
-@@ -273,7 +273,7 @@ struct intel_atomic_state {
- 	struct intel_wm_config wm_config;
+@@ -314,7 +314,7 @@ struct intel_atomic_state {
+ 	bool skip_intermediate_wm;
  
  	/* Gen9+ only */
 -	struct skl_ddb_allocation ddb;
@@ -82,30 +72,11 @@ index 4d6336a..e5543b8 100644
  };
  
  struct intel_plane_state {
-@@ -1661,6 +1661,18 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
- 
- 	return to_intel_crtc_state(crtc_state);
- }
-+
-+static inline struct intel_plane_state *
-+intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
-+                                     struct intel_plane *plane)
-+{
-+       struct drm_plane_state *plane_state;
-+
-+       plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
-+
-+       return to_intel_plane_state(plane_state);
-+}
-+
- int intel_atomic_setup_scalers(struct drm_device *dev,
- 	struct intel_crtc *intel_crtc,
- 	struct intel_crtc_state *crtc_state);
 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
-index ec22d93..73e5242 100644
+index 342aa66..b072417 100644
 --- a/drivers/gpu/drm/i915/intel_pm.c
 +++ b/drivers/gpu/drm/i915/intel_pm.c
-@@ -3160,23 +3160,6 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
+@@ -3221,23 +3221,6 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
  	return ret;
  }
  
@@ -129,7 +100,7 @@ index ec22d93..73e5242 100644
  static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
  				struct intel_crtc_state *cstate,
  				struct intel_plane_state *intel_pstate,
-@@ -3472,6 +3455,8 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
+@@ -3533,6 +3516,8 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
  
  		if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
  			continue;
@@ -138,7 +109,7 @@ index ec22d93..73e5242 100644
  
  		I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
  
-@@ -3655,66 +3640,9 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
+@@ -3716,66 +3701,9 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
  	else
  		*changed = true;
  
@@ -205,7 +176,7 @@ index ec22d93..73e5242 100644
  static int
  skl_compute_ddb(struct drm_atomic_state *state)
  {
-@@ -3722,6 +3650,7 @@ skl_compute_ddb(struct drm_atomic_state *state)
+@@ -3783,6 +3711,7 @@ skl_compute_ddb(struct drm_atomic_state *state)
  	struct drm_i915_private *dev_priv = to_i915(dev);
  	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
  	struct intel_crtc *intel_crtc;
@@ -213,7 +184,7 @@ index ec22d93..73e5242 100644
  	unsigned realloc_pipes = dev_priv->active_crtcs;
  	int ret;
  
-@@ -3747,8 +3676,10 @@ skl_compute_ddb(struct drm_atomic_state *state)
+@@ -3808,8 +3737,10 @@ skl_compute_ddb(struct drm_atomic_state *state)
  	 * any other display updates race with this transaction, so we need
  	 * to grab the lock on *all* CRTC's.
  	 */
@@ -225,7 +196,7 @@ index ec22d93..73e5242 100644
  
  	for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
  		struct intel_crtc_state *cstate;
-@@ -3757,7 +3688,7 @@ skl_compute_ddb(struct drm_atomic_state *state)
+@@ -3818,7 +3749,7 @@ skl_compute_ddb(struct drm_atomic_state *state)
  		if (IS_ERR(cstate))
  			return PTR_ERR(cstate);
  
@@ -234,7 +205,7 @@ index ec22d93..73e5242 100644
  		if (ret)
  			return ret;
  	}
-@@ -3770,8 +3701,11 @@ skl_compute_wm(struct drm_atomic_state *state)
+@@ -3831,8 +3762,11 @@ skl_compute_wm(struct drm_atomic_state *state)
  {
  	struct drm_crtc *crtc;
  	struct drm_crtc_state *cstate;
@@ -247,7 +218,7 @@ index ec22d93..73e5242 100644
  
  	/*
  	 * If this transaction isn't actually touching any CRTC's, don't
-@@ -3786,10 +3720,44 @@ skl_compute_wm(struct drm_atomic_state *state)
+@@ -3847,10 +3781,45 @@ skl_compute_wm(struct drm_atomic_state *state)
  	if (!changed)
  		return 0;
  
@@ -286,21 +257,22 @@ index ec22d93..73e5242 100644
 +			/* This pipe's WM's did not change */
 +			continue;
 +
++		intel_cstate->update_wm_pre = true;
 +		skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
 +	}
 +
  	return 0;
  }
  
-@@ -3801,21 +3769,12 @@ static void skl_update_wm(struct drm_crtc *crtc)
+@@ -3862,26 +3831,21 @@ static void skl_update_wm(struct drm_crtc *crtc)
  	struct skl_wm_values *results = &dev_priv->wm.skl_results;
  	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
  	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
 -	bool wm_changed;
- 
+-
 -	/* Clear all dirty flags */
 -	results->dirty_pipes = 0;
--
+ 
 -	skl_clear_wm(results, intel_crtc->pipe);
 -
 -	skl_update_pipe_wm(crtc->state, &results->ddb, pipe_wm, &wm_changed);
@@ -311,11 +283,20 @@ index ec22d93..73e5242 100644
 -	skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
 -	results->dirty_pipes |= drm_crtc_mask(&intel_crtc->base);
 +	intel_crtc->wm.active.skl = *pipe_wm;
++
++	mutex_lock(&dev_priv->wm.wm_mutex);
  
 -	skl_update_other_pipe_wm(dev, crtc, results);
  	skl_write_wm_values(dev_priv, results);
  	skl_flush_wm_values(dev_priv, results);
  
+ 	/* store the new configuration */
+ 	dev_priv->wm.skl_hw = *results;
++
++	mutex_unlock(&dev_priv->wm.wm_mutex);
+ }
+ 
+ static void ilk_compute_wm_config(struct drm_device *dev,
 -- 
 2.7.4