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author | Justin M. Forbes <jforbes@fedoraproject.org> | 2020-05-28 10:35:15 -0500 |
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committer | Justin M. Forbes <jforbes@fedoraproject.org> | 2020-05-28 10:35:15 -0500 |
commit | c1d5388741c67796c728a41e28949b05ed72e52c (patch) | |
tree | 9271475cb907db2eb4a9fa111df997c1a461620e /0001-device-use-regular-PRI-accessors-in-chipset-detectio.patch | |
parent | a79d8affb70a95069c35a0ccf7085e230c22a98d (diff) | |
download | kernel-c1d5388741c67796c728a41e28949b05ed72e52c.tar.gz kernel-c1d5388741c67796c728a41e28949b05ed72e52c.tar.xz kernel-c1d5388741c67796c728a41e28949b05ed72e52c.zip |
kernel-5.7.0-0.rc7.20200528gitb0c3ba31be3e.1
* Thu May 28 2020 CKI@GitLab <cki-project@redhat.com> [5.7.0-0.rc7.20200528gitb0c3ba31be3e.1]
- b0c3ba31be3e rebase
- Updated changelog for the release based on 444fc5cde643 ("CKI@GitLab")
Resolves: rhbz#
Signed-off-by: Justin M. Forbes <jforbes@fedoraproject.org>
Diffstat (limited to '0001-device-use-regular-PRI-accessors-in-chipset-detectio.patch')
-rw-r--r-- | 0001-device-use-regular-PRI-accessors-in-chipset-detectio.patch | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/0001-device-use-regular-PRI-accessors-in-chipset-detectio.patch b/0001-device-use-regular-PRI-accessors-in-chipset-detectio.patch new file mode 100644 index 000000000..ec4345169 --- /dev/null +++ b/0001-device-use-regular-PRI-accessors-in-chipset-detectio.patch @@ -0,0 +1,113 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ben Skeggs <bskeggs@redhat.com> +Date: Thu, 30 Apr 2020 14:08:53 +1000 +Subject: [PATCH] device: use regular PRI accessors in chipset detection + +Signed-off-by: Ben Skeggs <bskeggs@redhat.com> +--- + .../gpu/drm/nouveau/nvkm/engine/device/base.c | 31 ++++++++----------- + 1 file changed, 13 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +index f977dddcd809..5b90c2a1bf3d 100644 +--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c ++++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +@@ -2925,9 +2925,9 @@ nvkm_device_del(struct nvkm_device **pdevice) + } + + static inline bool +-nvkm_device_endianness(void __iomem *pri) ++nvkm_device_endianness(struct nvkm_device *device) + { +- u32 boot1 = ioread32_native(pri + 0x000004) & 0x01000001; ++ u32 boot1 = nvkm_rd32(device, 0x000004) & 0x01000001; + #ifdef __BIG_ENDIAN + if (!boot1) + return false; +@@ -2949,7 +2949,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func, + struct nvkm_subdev *subdev; + u64 mmio_base, mmio_size; + u32 boot0, boot1, strap; +- void __iomem *map = NULL; + int ret = -EEXIST, i; + unsigned chipset; + +@@ -2976,8 +2975,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func, + mmio_size = device->func->resource_size(device, 0); + + if (detect || mmio) { +- map = ioremap(mmio_base, mmio_size); +- if (map == NULL) { ++ device->pri = ioremap(mmio_base, mmio_size); ++ if (device->pri == NULL) { + nvdev_error(device, "unable to map PRI\n"); + ret = -ENOMEM; + goto done; +@@ -2987,10 +2986,10 @@ nvkm_device_ctor(const struct nvkm_device_func *func, + /* identify the chipset, and determine classes of subdev/engines */ + if (detect) { + /* switch mmio to cpu's native endianness */ +- if (!nvkm_device_endianness(map)) { +- iowrite32_native(0x01000001, map + 0x000004); +- ioread32_native(map); +- if (!nvkm_device_endianness(map)) { ++ if (!nvkm_device_endianness(device)) { ++ nvkm_wr32(device, 0x000004, 0x01000001); ++ nvkm_rd32(device, 0x000000); ++ if (!nvkm_device_endianness(device)) { + nvdev_error(device, + "GPU not supported on big-endian\n"); + ret = -ENOSYS; +@@ -2998,7 +2997,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, + } + } + +- boot0 = ioread32_native(map + 0x000000); ++ boot0 = nvkm_rd32(device, 0x000000); + + /* chipset can be overridden for devel/testing purposes */ + chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); +@@ -3157,7 +3156,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, + device->chip->name, boot0); + + /* vGPU detection */ +- boot1 = ioread32_native(map + 0x000004); ++ boot1 = nvkm_rd32(device, 0x0000004); + if (device->card_type >= TU100 && (boot1 & 0x00030000)) { + nvdev_info(device, "vGPUs are not supported\n"); + ret = -ENODEV; +@@ -3165,7 +3164,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, + } + + /* read strapping information */ +- strap = ioread32_native(map + 0x101000); ++ strap = nvkm_rd32(device, 0x101000); + + /* determine frequency of timing crystal */ + if ( device->card_type <= NV_10 || device->chipset < 0x17 || +@@ -3187,10 +3186,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func, + if (!device->name) + device->name = device->chip->name; + +- if (mmio) { +- device->pri = map; +- } +- + mutex_init(&device->mutex); + + for (i = 0; i < NVKM_SUBDEV_NR; i++) { +@@ -3278,9 +3273,9 @@ nvkm_device_ctor(const struct nvkm_device_func *func, + + ret = 0; + done: +- if (map && (!mmio || ret)) { ++ if (device->pri && (!mmio || ret)) { ++ iounmap(device->pri); + device->pri = NULL; +- iounmap(map); + } + mutex_unlock(&nv_devices_mutex); + return ret; +-- +2.26.2 + |