sssd.git - Unnamed repository; edit this file to name it for gitweb.

diff options

author	Stephen Gallagher <sgallagh@redhat.com>	2011-01-19 15:42:03 -0500
committer	Stephen Gallagher <sgallagh@redhat.com>	2011-01-21 09:24:56 -0500
commit	aab009992cc8fbc66d5c07ff501b6788144afe61 (patch)
tree	1c6c05249b561202b59fb4a3acc0c29e1b2f72c0 /src/providers/proxy
parent	3ad662a4d26c0d6ee4e382758ca7b3f0c2880d20 (diff)

Perform initgroups lookup for PAM

Previously we were only looking up the user, but we need to make sure that all groups are available for use by access providers.

Diffstat (limited to 'src/providers/proxy')

0 files changed, 0 insertions, 0 deletions

/* * (C) Copyright 2007-2008 * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * * Configuation settings for the AT91SAM9263EK board. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #ifndef __CONFIG_H #define __CONFIG_H /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ #define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH #define CONFIG_SKIP_LOWLEVEL_INIT #endif /* * Hardware drivers */ #define CONFIG_AT91_GPIO 1 #define CONFIG_ATMEL_USART 1 #undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_USART2 #define CONFIG_USART3 1 /* USART 3 is DBGU */ /* LCD */ #define CONFIG_LCD 1 #define LCD_BPP LCD_COLOR8 #define CONFIG_LCD_LOGO 1 #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO 1 #define CONFIG_LCD_INFO_BELOW_LOGO 1 #define CONFIG_SYS_WHITE_ON_BLACK 1 #define CONFIG_ATMEL_LCD 1 #define CONFIG_ATMEL_LCD_BGR555 1 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* LED */ #define CONFIG_AT91_LED #define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* the power led */ #define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* the user1 led */ #define CONFIG_YELLOW_LED AT91_PIO_PORTC, 29 /* the user2 led */ #define CONFIG_BOOTDELAY 3 /* * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE 1 #define CONFIG_BOOTP_BOOTPATH 1 #define CONFIG_BOOTP_GATEWAY 1 #define CONFIG_BOOTP_HOSTNAME 1 /* * Command line configuration. */ #include <config_cmd_default.h> #undef CONFIG_CMD_BDI #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_IMI #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_SOURCE #define CONFIG_CMD_PING 1 #define CONFIG_CMD_DHCP 1 #define CONFIG_CMD_NAND 1 #define CONFIG_CMD_USB 1 /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 #define DATAFLASH_TCSS (0x1a << 16) #define DATAFLASH_TCHS (0x1 << 24) /* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 #define PHYS_FLASH_1 0x10000000 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MONITOR_SEC 1:0-3 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000) #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) /* Address and size of Primary Environment Sector */ #define CONFIG_ENV_SIZE 0x2000 #define xstr(s) str(s) #define str(s) #s #define CONFIG_EXTRA_ENV_SETTINGS \ "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ "update=" \ "protect off ${monitor_base} +${filesize};" \ "erase ${monitor_base} +${filesize};" \ "cp.b ${load_addr} ${monitor_base} ${filesize};" \ "protect on ${monitor_base} +${filesize}\0" #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define MASTER_PLL_MUL 171 #define MASTER_PLL_DIV 14 #define MASTER_PLL_OUT 3 /* clocks */ #define CONFIG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) #define CONFIG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | \ AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ AT91_PMC_PLLXR_PLLCOUNT(63) | \ AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ #define CONFIG_SYS_MATRIX_EBICSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ #define CONFIG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ #define CONFIG_SYS_SDRC_TR_VAL1 0x13C /* SDRAMC_CR - Configuration register*/ #define CONFIG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ AT91_SDRAMC_CAS_3 | \ AT91_SDRAMC_DBW_32 | \ (1 << 8) | /* Write Recovery Delay */ \ (7 << 12) | /* Row Cycle Delay */ \ (2 << 16) | /* Row Precharge Delay */ \ (2 << 20) | /* Row to Column Delay */ \ (5 << 24) | /* Active to Precharge Delay */ \ (1 << 28)) /* Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) #define CONFIG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) #define CONFIG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) #define CONFIG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ #define CONFIG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_MR_URSTEN | \ AT91_RSTC_MR_ERSTL(15)) /* Disable Watchdog */ #define CONFIG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ AT91_WDT_MR_WDD(0xfff)) #endif #else #define CONFIG_SYS_NO_FLASH 1 #endif /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 /* #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 */ #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ #define CONFIG_MACB 1 #define CONFIG_RMII 1 #define CONFIG_NET_MULTI 1 #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R 1 /* USB */ #define CONFIG_USB_ATMEL #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE 1 #define CONFIG_CMD_FAT 1 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_MEMTEST_END 0x23e00000 #ifdef CONFIG_SYS_USE_DATAFLASH


context:
space:
mode: