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/******************************************************************************
 *
 *	(C)Copyright 1998,1999 SysKonnect,
 *	a business unit of Schneider & Koch & Co. Datensysteme GmbH.
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

#ifndef	_HWM_
#define	_HWM_

#include "h/mbuf.h"

/*
 * MACRO for DMA synchronization:
 *	The descriptor 'desc' is flushed for the device 'flag'.
 *	Devices are the CPU (DDI_DMA_SYNC_FORCPU) and the
 *	adapter (DDI_DMA_SYNC_FORDEV).
 *
 *	'desc'	Pointer to a Rx or Tx descriptor.
 *	'flag'	Flag for direction (view for CPU or DEVICE) that
 *		should be synchronized.
 *
 *	Empty macros and defines are specified here. The real macro
 *	is os-specific and should be defined in osdef1st.h.
 */
#ifndef DRV_BUF_FLUSH
#define DRV_BUF_FLUSH(desc,flag)
#define DDI_DMA_SYNC_FORCPU
#define DDI_DMA_SYNC_FORDEV
#endif

	/*
	 * hardware modul dependent receive modes
	 */
#define	RX_ENABLE_PASS_SMT	21
#define	RX_DISABLE_PASS_SMT	22
#define	RX_ENABLE_PASS_NSA	23
#define	RX_DISABLE_PASS_NSA	24
#define	RX_ENABLE_PASS_DB	25
#define	RX_DISABLE_PASS_DB	26
#define	RX_DISABLE_PASS_ALL	27
#define	RX_DISABLE_LLC_PROMISC	28
#define	RX_ENABLE_LLC_PROMISC	29


#ifndef	DMA_RD
#define DMA_RD		1	/* memory -> hw */
#endif
#ifndef DMA_WR
#define DMA_WR		2	/* hw -> memory */
#endif
#define SMT_BUF		0x80

	/*
	 * bits of the frame status byte
	 */
#define EN_IRQ_EOF	0x02	/* get IRQ after end of frame transmission */
#define	LOC_TX		0x04	/* send frame to the local SMT */
#define LAST_FRAG	0x08	/* last TxD of the frame */
#define	FIRST_FRAG	0x10	/* first TxD of the frame */
#define	LAN_TX		0x20	/* send frame to network if set */
#define RING_DOWN	0x40	/* error: unable to send, ring down */
#define OUT_OF_TXD	0x80	/* error: not enough TxDs available */


#ifndef NULL
#define NULL 		0
#endif

#ifdef	LITTLE_ENDIAN
#define HWM_REVERSE(x)	(x)
#else
#define	HWM_REVERSE(x)		((((x)<<24L)&0xff000000L)	+	\
				 (((x)<< 8L)&0x00ff0000L)	+	\
				 (((x)>> 8L)&0x0000ff00L)	+	\
				 (((x)>>24L)&0x000000ffL))
#endif

#define C_INDIC		(1L<<25)
#define A_INDIC		(1L<<26)
#define	RD_FS_LOCAL	0x80

	/*
	 * DEBUG FLAGS
	 */
#define	DEBUG_SMTF	1
#define	DEBUG_SMT	2
#define	DEBUG_ECM	3
#define	DEBUG_RMT	4
#define	DEBUG_CFM	5
#define	DEBUG_PCM	6
#define	DEBUG_SBA	7
#define	DEBUG_ESS	8

#define	DB_HWM_RX	10
#define	DB_HWM_TX	11
#define DB_HWM_GEN	12

struct s_mbuf_pool {
#ifndef	MB_OUTSIDE_SMC
	SMbuf		mb[MAX_MBUF] ;		/* mbuf pool */
#endif
	SMbuf		*mb_start ;		/* points to the first mb */
	SMbuf		*mb_free ;		/* free queue */
} ;

struct hwm_r {
	/*
	 * hardware modul specific receive variables
	 */
	u_int			len ;		/* length of the whole frame */
	char			*mb_pos ;	/* SMbuf receive position */
} ;

struct hw_modul {
	/*
	 * All hardware modul specific variables
	 */
	struct	s_mbuf_pool	mbuf_pool ;
	struct	hwm_r	r ;

	union s_fp_descr volatile *descr_p ; /* points to the desriptor area */

	u_short pass_SMT ;		/* pass SMT frames */
	u_short pass_NSA ;		/* pass all NSA frames */
	u_short pass_DB ;		/* pass Direct Beacon Frames */
	u_short pass_llc_promisc ;	/* pass all llc frames (default ON) */