drivers/net/mpc5xxx_fec.h


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * This file is based on mpc4200fec.h
 * (C) Copyright Motorola, Inc., 2000
 *
 * odin ethernet header file
 */

#ifndef __MPC5XXX_FEC_H
#define __MPC5XXX_FEC_H

typedef unsigned long uint32;
typedef unsigned short uint16;
typedef unsigned char uint8;

typedef struct ethernet_register_set {

/* [10:2]addr = 00 */

/*  Control and status Registers (offset 000-1FF) */

	volatile uint32 fec_id;			/* MBAR_ETH + 0x000 */
	volatile uint32 ievent;			/* MBAR_ETH + 0x004 */
	volatile uint32 imask;			/* MBAR_ETH + 0x008 */

	volatile uint32 RES0[1];		/* MBAR_ETH + 0x00C */
	volatile uint32 r_des_active;		/* MBAR_ETH + 0x010 */
	volatile uint32 x_des_active;		/* MBAR_ETH + 0x014 */
	volatile uint32 r_des_active_cl;	/* MBAR_ETH + 0x018 */
	volatile uint32 x_des_active_cl;	/* MBAR_ETH + 0x01C */
	volatile uint32 ivent_set;		/* MBAR_ETH + 0x020 */
	volatile uint32 ecntrl;			/* MBAR_ETH + 0x024 */

	volatile uint32 RES1[6];		/* MBAR_ETH + 0x028-03C */
	volatile uint32 mii_data;		/* MBAR_ETH + 0x040 */
	volatile uint32 mii_speed;		/* MBAR_ETH + 0x044 */
	volatile uint32 mii_status;		/* MBAR_ETH + 0x048 */

	volatile uint32 RES2[5];		/* MBAR_ETH + 0x04C-05C */
	volatile uint32 mib_data;		/* MBAR_ETH + 0x060 */
	volatile uint32 mib_control;		/* MBAR_ETH + 0x064 */

	volatile uint32 RES3[6];		/* MBAR_ETH + 0x068-7C */
	volatile uint32 r_activate;		/* MBAR_ETH + 0x080 */
	volatile uint32 r_cntrl;		/* MBAR_ETH + 0x084 */
	volatile uint32 r_hash;			/* MBAR_ETH + 0x088 */
	volatile uint32 r_data;			/* MBAR_ETH + 0x08C */
	volatile uint32 ar_done;		/* MBAR_ETH + 0x090 */
	volatile uint32 r_test;			/* MBAR_ETH + 0x094 */
	volatile uint32 r_mib;			/* MBAR_ETH + 0x098 */
	volatile uint32 r_da_low;		/* MBAR_ETH + 0x09C */
	volatile uint32 r_da_high;		/* MBAR_ETH + 0x0A0 */

	volatile uint32 RES4[7];		/* MBAR_ETH + 0x0A4-0BC */
	volatile uint32 x_activate;		/* MBAR_ETH + 0x0C0 */
	volatile uint32 x_cntrl;		/* MBAR_ETH + 0x0C4 */
	volatile uint32 backoff;		/* MBAR_ETH + 0x0C8 */
	volatile uint32 x_data;			/* MBAR_ETH + 0x0CC */
	volatile uint32 x_status;		/* MBAR_ETH + 0x0D0 */
	volatile uint32 x_mib;			/* MBAR_ETH + 0x0D4 */
	volatile uint32 x_test;			/* MBAR_ETH + 0x0D8 */
	volatile uint32 fdxfc_da1;		/* MBAR_ETH + 0x0DC */
	volatile uint32 fdxfc_da2;		/* MBAR_ETH + 0x0E0 */