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/*
* (C) Copyright 2000, 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _FLASH_H_
#define _FLASH_H_
#ifndef CFG_NO_FLASH
/*-----------------------------------------------------------------------
* FLASH Info: contains chip specific data, per FLASH bank
*/
typedef struct {
ulong size; /* total bank size in bytes */
ushort sector_count; /* number of erase units */
ulong flash_id; /* combined device & manufacturer code */
ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */
uchar protect[CFG_MAX_FLASH_SECT]; /* sector protection status */
#ifdef CFG_FLASH_CFI
uchar portwidth; /* the width of the port */
uchar chipwidth; /* the width of the chip */
ushort buffer_size; /* # of bytes in write buffer */
ulong erase_blk_tout; /* maximum block erase timeout */
ulong write_tout; /* maximum write timeout */
ulong buffer_write_tout; /* maximum buffer write timeout */
#endif
} flash_info_t;
/*
* Values for the width of the port
*/
#define FLASH_CFI_8BIT 0x01
#define FLASH_CFI_16BIT 0x02
#define FLASH_CFI_32BIT 0x04
#define FLASH_CFI_64BIT 0x08
/*
* Values for the width of the chip
*/
#define FLASH_CFI_BY8 0x01
#define FLASH_CFI_BY16 0x02
#define FLASH_CFI_BY32 0x04
#define FLASH_CFI_BY64 0x08
/* Prototypes */
extern unsigned long flash_init (void);
extern void flash_print_info (flash_info_t *);
extern int flash_erase (flash_info_t *, int, int);
extern int flash_sect_erase (ulong addr_first, ulong addr_last);
extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
/* common/flash.c */
extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
extern int flash_write (uchar *, ulong, ulong);
extern flash_info_t *addr2info (ulong);
extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
/* board/?/flash.c */
#if defined(CFG_FLASH_PROTECTION)
extern int flash_real_protect(flash_info_t *info, long sector, int prot);
#endif /* CFG_FLASH_PROTECTION */
/*-----------------------------------------------------------------------
* return codes from flash_write():
*/
#define ERR_OK 0
#define ERR_TIMOUT 1
#define ERR_NOT_ERASED 2
#define ERR_PROTECTED 4
#define ERR_INVAL 8
#define ERR_ALIGN 16
#define ERR_UNKNOWN_FLASH_VENDOR 32
#define ERR_UNKNOWN_FLASH_TYPE 64
#define ERR_PROG_ERROR 128
/*-----------------------------------------------------------------------
* Protection Flags for flash_protect():
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
/*-----------------------------------------------------------------------
* Device IDs
*/
#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */
#define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */
#define ATM_MANUFACT 0x001F001F /* ATMEL */
#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
#define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */
#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */
#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */
/* Micron Technologies (INTEL compat.) */
#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
#define AMD_ID_LV040B 0x4F /* 29LV040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
#define AMD_ID_F040B 0xA4 /* 29F040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
#define STM_ID_M29W040B 0xE3 /* M29W040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */
/* 8 Mbit, 512K x 16, */
/* 8 64K x 16 uniform sectors */
#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */
#define AMD_ID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */
#define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */
#define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */
#define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */
#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */
#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */
#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */
#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */
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