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| * Fix bugs in samr python tests.Jelmer Vernooij2008-05-231-1/+1
| * Create new context in pytalloc to avoid problems with talloc_free() freeing t...Jelmer Vernooij2008-05-231-1/+8
| * UFollow conventions for __repr__ contents for talloc python wrapper.Jelmer Vernooij2008-05-231-1/+1
| * Add another test toe the python samr testsuite.Jelmer Vernooij2008-05-231-2/+18
| * Convert samr test to python.Jelmer Vernooij2008-05-231-0/+2
| * Fix bug after reprocessing swig files with newer version of SWIG.Jelmer Vernooij2008-05-232-4/+4
| * dcerpc is now samba.dcerpc, avoid including source code in API documentation.Jelmer Vernooij2008-05-231-1/+3
| * Add docstrings to samba3 and getopt modules.Jelmer Vernooij2008-05-232-0/+18
| * Use restructuredText formatting for docstrings.Jelmer Vernooij2008-05-236-0/+12
| * Add docstrings in misc python module.Jelmer Vernooij2008-05-233-33/+129
| * provision: Generate krb5.conf template separate from named.conf template.Andrew Kroeger2008-05-211-22/+52
| * Fix import in provision test.Jelmer Vernooij2008-05-221-1/+1
| * Move DCE/RPC python bindings into samba package.Jelmer Vernooij2008-05-224-4/+4
| * Fix CFLAGS for SWIG files.Jelmer Vernooij2008-05-221-1/+1
| * Make sure the default ldb modules dir gets initialized.Jelmer Vernooij2008-05-221-0/+2
| * Fix dependencies and imports.Jelmer Vernooij2008-05-223-4/+4
| * Move more modules inside of the samba package.Jelmer Vernooij2008-05-213-4/+9
| * Move CFLAGS overrides for SWIG modules to Makefile.Jelmer Vernooij2008-05-211-0/+2
| * Merge branch 'v4-0-local' of git://git.id10ts.net/samba into 4-0-localAndrew Bartlett2008-05-211-7/+25
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| | * provision: Create instructions for enabling DNS GSS-TSIG updates.Andrew Kroeger2008-05-181-7/+25
| * | Use src dir.Jelmer Vernooij2008-05-181-6/+6
| * | Use variables for source path in libnet/ and scripting/python.Jelmer Vernooij2008-05-181-6/+6
| * | Install python modules by default.Jelmer Vernooij2008-05-161-0/+2
| * | Remove smbpython.Jelmer Vernooij2008-05-113-40/+0
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| * make sure to always use string version of uuid rather than object.Jelmer Vernooij2008-05-112-6/+7
| * Complete dependencies for python modules (actually matters when built standal...Jelmer Vernooij2008-05-111-1/+7
| * Use consistent function names with the standard Python uuid module that is av...Jelmer Vernooij2008-05-113-7/+7
| * Install standalone python modules (so we can use stock python rather than smb...Jelmer Vernooij2008-05-102-6/+5
| * Clean up some git merges gone wrong.Jelmer Vernooij2008-05-101-2/+0
| * Merge branch 'v4-0-test' of ssh://git.samba.org/data/git/samba into v4-0-gmake3Jelmer Vernooij2008-04-2519-92/+245
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| | * Fix the expectations on the unixinfo test.Andrew Bartlett2008-04-171-2/+2
| | * make sure header can be included more than once.Jelmer Vernooij2008-04-161-0/+5
| | * Re-add 'db' subdirectory for LDAP backend provisionAndrew Bartlett2008-04-151-3/+3
| | * Merge branch 'v4-0-test' of ssh://git.samba.org/data/git/samba into 4-0-abartletAndrew Bartlett2008-04-152-2/+4
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| | | * Fix pointers when pushing strings to python during pidl generation.Jelmer Vernooij2008-04-151-0/+2
| | | * Saner names for Python objects.Jelmer Vernooij2008-04-151-2/+2
| | * | Fix provision-backend scriptAndrew Bartlett2008-04-151-3/+4
| | |/
| | * Fix warnings.Jelmer Vernooij2008-04-151-2/+2
| | * Fix the build.Jelmer Vernooij2008-04-151-10/+0
| | * Merge branch 'v4-0-test' of ssh://git.samba.org/data/git/samba into v4-0-gmake4Jelmer Vernooij2008-04-146-17/+14
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| | | * Use RpcInterfaceTestCase everywhere.Jelmer Vernooij2008-04-146-17/+14
| | * | Merge branch 'v4-0-test' of ssh://git.samba.org/data/git/samba into v4-0-gmake4Jelmer Vernooij2008-04-148-15/+105
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| | | * Make sure credentials are specified when running the Python winreg RPC tests.Jelmer Vernooij2008-04-141-2/+2
| | | * Allow command line options in the subunitrun script.Jelmer Vernooij2008-04-141-7/+5
| | | * Also look in the environment for smb.conf path.Jelmer Vernooij2008-04-141-4/+6
| | | * Add convenience TestCase class for testing RPC interfaces.Jelmer Vernooij2008-04-142-5/+11
| | | * Merge branch 'v4-0-test' of ssh://git.samba.org/data/git/samba into 4-0-abartletAndrew Bartlett2008-04-141-16/+1
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| | | * | Re-run SWIGAndrew Bartlett2008-04-142-0/+46
| | | * | Fix newuser and setpassword scripts, and port to idmap.Andrew Bartlett2008-04-142-1/+34
| | | * | Add in a way to get at the private_path() function from pythonAndrew Bartlett2008-04-141-0/+5
generated by cgit (git 2.34.1) at 2026-03-16 03:49:54 +0000
#if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif /*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 11-6 *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ #define CFG_SIUMCR (SIUMCR_MLRC10) /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) /*----------------------------------------------------------------------- * RTCSC - Real-Time Clock Status and Control Register 11-27 *----------------------------------------------------------------------- */ /*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ #define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */ #define CFG_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit * * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ /* up to 50 MHz we use a 1:1 clock */ #define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF00 /* up to 50 MHz we use a 1:1 clock */ #define CFG_SCCR (SCCR_COM11 | SCCR_TBS) /*----------------------------------------------------------------------- * PCMCIA stuff *----------------------------------------------------------------------- * */ #define CFG_PCMCIA_MEM_ADDR (0xE0000000) #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) #define CFG_PCMCIA_DMA_ADDR (0xE4000000) #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) #define CFG_PCMCIA_IO_ADDR (0xEC000000) #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) /*----------------------------------------------------------------------- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) *----------------------------------------------------------------------- */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ #define CFG_ATA_IDE0_OFFSET 0x0000 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR /* Offset for data I/O */ #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) /* Offset for normal register accesses */ #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET 0x0100 /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */ /*#define CFG_DER 0x2002000F*/ #define CFG_DER 0 /* * Init Memory Controller: * * BR0 and OR0 (FLASH) */ #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ #define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ #define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) /* * BR1 and OR1 (SDRAM) * */ #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ #define CFG_OR_TIMING_SDRAM 0x00000E00 #define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) #define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) /* RPXLITE mem setting */ #define CFG_BR3_PRELIM 0xFA400001 /* BCSR */ #define CFG_OR3_PRELIM 0xFFFF8910 #define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ #define CFG_OR4_PRELIM 0xFFFE0970 /* * Memory Periodic Timer Prescaler */ /* periodic timer for refresh */ #define CFG_MAMR_PTA 58 /* * Refresh clock Prescalar */ #define CFG_MPTPR MPTPR_PTP_DIV8 /* * MAMR settings for SDRAM */ /* 10 column SDRAM */ #define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) /* * Internal Definitions * * Boot Flags */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ /* Configuration variable added by yooth. */ /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ /* * BCSRx * * Board Status and Control Registers * */ #define BCSR0 0xFA400000 #define BCSR1 0xFA400001 #define BCSR2 0xFA400002 #define BCSR3 0xFA400003 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ #define BCSR0_COLTEST 0x20 #define BCSR0_ETHLPBK 0x40 #define BCSR0_ETHEN 0x80 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ #define BCSR1_PCVCTL6 0x02 #define BCSR1_PCVCTL5 0x04 #define BCSR1_PCVCTL4 0x08 #define BCSR1_IPB5SEL 0x10 #define BCSR2_ENPA5HDR 0x08 /* USB Control */ #define BCSR2_ENUSBCLK 0x10 #define BCSR2_USBPWREN 0x20 #define BCSR2_USBSPD 0x40 #define BCSR2_USBSUSP 0x80 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ #define BCSR3_BWNVR 0x02 /* NVRAM Battery */ #define BCSR3_RDY_BSY 0x04 /* Flash Operation */ #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ #define BCSR3_D27 0x10 /* Dip Switch settings */ #define BCSR3_D26 0x20 #define BCSR3_D25 0x40 #define BCSR3_D24 0x80 #endif /* __CONFIG_H */
generated by cgit (git 2.34.1) at 2026-03-16 03:49:53 +0000