initial srpm import

1 files changed, 41 insertions, 0 deletions

diff --git a/linux-2.6-pci-cacheline-sizing.patch b/linux-2.6-pci-cacheline-sizing.patch
new file mode 100644
index 0000000..8acaee4
--- /dev/null
+++ b/linux-2.6-pci-cacheline-sizing.patch
@@ -0,0 +1,41 @@
+PCI: Use generic cacheline sizing instead of per-vendor tests.
+
+Instead of the pci code needing to have code to determine the
+cacheline size of each processor, use the data the cpu identification
+code should have already determined during early boot.
+
+I chose not to delete the existing code for the time being.
+Instead I added some additional debug statements to be sure that it's
+doing the right thing, and compares it against what the old code would
+have done.  After this has been proven to be right in a release,
+we can delete the paranoid checks, and all the old vendor checking code.
+
+Signed-off-by: Dave Jones <davej@redhat.com>
+
+diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
+index 2202b62..f371fe8 100644
+--- a/arch/x86/pci/common.c
++++ b/arch/x86/pci/common.c
+@@ -432,6 +432,22 @@ int __init pcibios_init(void)
+ 	else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
+ 		pci_cache_line_size = 128 >> 2;	/* P4 */
+ 
++	if (c->x86_clflush_size != (pci_cache_line_size <<2))
++		printk(KERN_DEBUG "PCI: old code would have set cacheline "
++			"size to %d bytes, but clflush_size = %d\n",
++			pci_cache_line_size << 2,
++			c->x86_clflush_size);
++
++	/* Once we know this logic works, all the above code can be deleted. */
++	if (c->x86_clflush_size > 0) {
++		pci_cache_line_size = c->x86_clflush_size >> 2;
++		printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
++			pci_cache_line_size << 2);
++	} else {
++		pci_cache_line_size = 32 >> 2;
++		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
++	}
++
+ 	pcibios_resource_survey();
+ 
+ 	if (pci_bf_sort >= pci_force_bf)