From 589abe3a0f594a7707a15674ca9e80370c972832 Mon Sep 17 00:00:00 2001 From: Eilon Greenstein Date: Thu, 12 Feb 2009 08:36:55 +0000 Subject: bnx2x: Supporting BCM8726 PHY Also adding the ability to recognize the optic module and disable it if it is not authorized for safety reasons - since this feature might upset some users which are willing to take the risk, it is optional and can be disabled by setting an nvram bit (or a trivial driver patch to set this bit). This dual port PHY requires special handling if the ports are swapped. Signed-off-by: Yaniv Rosner Signed-off-by: Eilon Greenstein Signed-off-by: David S. Miller --- drivers/net/bnx2x_reg.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'drivers/net/bnx2x_reg.h') diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index 6fc1d0df978..520bf695864 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h @@ -5800,9 +5800,25 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PMA_REG_ROM_VER2 0xca1a #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d +#define MDIO_PMA_REG_MISC_CTRL0 0xca23 +#define MDIO_PMA_REG_LRM_MODE 0xca3f #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 #define MDIO_PMA_REG_MISC_CTRL1 0xca85 +#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL 0x8000 +#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK 0x000c +#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE 0x0000 +#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE 0x0004 +#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 +#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_FAILED 0x000c +#define MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT 0x8002 +#define MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR 0x8003 +#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 +#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff +#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 +#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 + + #define MDIO_PMA_REG_7101_RESET 0xc000 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 #define MDIO_PMA_REG_7101_VER1 0xc026 @@ -5832,6 +5848,12 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_XS_PLL_SEQUENCER 0x8000 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a +#define MDIO_XS_8706_REG_BANK_RX0 0x80bc +#define MDIO_XS_8706_REG_BANK_RX1 0x80cc +#define MDIO_XS_8706_REG_BANK_RX2 0x80dc +#define MDIO_XS_8706_REG_BANK_RX3 0x80ec +#define MDIO_XS_8706_REG_BANK_RXA 0x80fc + #define MDIO_AN_DEVAD 0x7 /*ieee*/ #define MDIO_AN_REG_CTRL 0x0000 -- cgit