From 81db718d48b991c33cbc7fe425003e374c087c36 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 22 Apr 2009 13:18:02 -0500 Subject: powerpc/fsl: use of_iomap() for rstcr mapping The rstcr register mapping code was written sometime ago before of_iomap() existed. We can use it and clean up the code a bit and get rid of one user of get_immrbase() in the process. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_soc.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index 5c64ccd402e..95dbc643c4f 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c @@ -379,16 +379,10 @@ static int __init setup_rstcr(void) struct device_node *np; np = of_find_node_by_name(NULL, "global-utilities"); if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) { - const u32 *prop = of_get_property(np, "reg", NULL); - if (prop) { - /* map reset control register - * 0xE00B0 is offset of reset control register - */ - rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff); - if (!rstcr) - printk (KERN_EMERG "Error: reset control " - "register not mapped!\n"); - } + rstcr = of_iomap(np, 0) + 0xb0; + if (!rstcr) + printk (KERN_EMERG "Error: reset control register " + "not mapped!\n"); } else printk (KERN_INFO "rstcr compatible register does not exist!\n"); if (np) -- cgit From 89d93347d1f66832c43e6b25a669fddff89929b5 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Mon, 20 Apr 2009 11:26:48 -0500 Subject: powerpc: make dma_window_* in pci_controller struct avail on 32b Also, convert them to resource_size_t (which is unsigned long on 64-bit, so it's not a change there). We will be using these on fsl 32b to indicate the start and size address of memory that the pci controller can actually reach - this is needed to determine if an address requires bounce buffering. For now, initialize them to a standard value; in the near future, the value will be calculated based on how the inbound windows are programmed. Signed-off-by: Becky Bruce Acked-by: Ben Herrenschmidt Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 78021d8afc5..376603df7c4 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -152,6 +152,10 @@ static void __init setup_pci_atmu(struct pci_controller *hose, out_be32(&pci->piw[2].piwbar,0x00000000); out_be32(&pci->piw[2].piwar, PIWAR_2G); + /* Save the base address and size covered by inbound window mappings */ + hose->dma_window_base_cur = 0x00000000; + hose->dma_window_size = 0x80000000; + iounmap(pci); } -- cgit From ca851c783ccf9784fb6ffebcb25e2b6fd0b8dccc Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 22 Apr 2009 13:44:24 -0500 Subject: powerpc/cpm: Remove some cruft code and defines Kill of some old defines and macros that we no longer use like CPM_MAP_ADDR and CPM_IRQ_OFFSET. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/cpm2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c index fd969f0e312..eb5927212fa 100644 --- a/arch/powerpc/sysdev/cpm2.c +++ b/arch/powerpc/sysdev/cpm2.c @@ -61,7 +61,7 @@ EXPORT_SYMBOL(cpm2_immr); void __init cpm2_reset(void) { #ifdef CONFIG_PPC_85xx - cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE); + cpm2_immr = ioremap(get_immrbase() + 0x80000, CPM_MAP_SIZE); #else cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE); #endif -- cgit From 06c4435021f4856261edd01e2691071edeb8fa51 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 1 May 2009 15:40:47 -0400 Subject: powerpc/qe: update risc allocation for QE Change the RISC allocation to macros instead of enum, add function to read the number of risc engines from the new property "fsl,qe-num-riscs" under the qe node in dts. Add new property "fsl,qe-num-riscs" description in qe.txt Signed-off-by: Haiying Wang Acked-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/qe_lib/qe.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index 01bce3784b0..2533677ae5e 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -575,3 +575,31 @@ struct qe_firmware_info *qe_get_firmware_info(void) } EXPORT_SYMBOL(qe_get_firmware_info); +unsigned int qe_get_num_of_risc(void) +{ + struct device_node *qe; + int size; + unsigned int num_of_risc = 0; + const u32 *prop; + + qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); + if (!qe) { + /* Older devices trees did not have an "fsl,qe" + * compatible property, so we need to look for + * the QE node by name. + */ + qe = of_find_node_by_type(NULL, "qe"); + if (!qe) + return num_of_risc; + } + + prop = of_get_property(qe, "fsl,qe-num-riscs", &size); + if (prop && size == sizeof(*prop)) + num_of_risc = *prop; + + of_node_put(qe); + + return num_of_risc; +} +EXPORT_SYMBOL(qe_get_num_of_risc); + -- cgit From 98ca77af23da6682bb3e34961a3f32e2c064a4ce Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 1 May 2009 15:40:48 -0400 Subject: powerpc/qe: update QE Serial Number The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will get the number of SNUMs from device tree by reading the new property "fsl,qe-num-snums", and set 28 as the default number of SNUMs so that it is compatible with the old QE chips' device trees which don't have this new property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum table which is 256. Also we update the snum_init[] array with 18 more new SNUMs which are confirmed to be useful on new chip. Signed-off-by: Haiying Wang Acked-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/qe_lib/qe.c | 47 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 4 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index 2533677ae5e..b28b0e512d6 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -61,6 +61,7 @@ struct qe_immap __iomem *qe_immr; EXPORT_SYMBOL(qe_immr); static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */ +static unsigned int qe_num_of_snum; static phys_addr_t qebase = -1; @@ -264,10 +265,14 @@ static void qe_snums_init(void) 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D, 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89, 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9, - 0xD8, 0xD9, 0xE8, 0xE9, + 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19, + 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59, + 0x68, 0x69, 0x78, 0x79, 0x80, 0x81, }; - for (i = 0; i < QE_NUM_OF_SNUM; i++) { + qe_num_of_snum = qe_get_num_of_snums(); + + for (i = 0; i < qe_num_of_snum; i++) { snums[i].num = snum_init[i]; snums[i].state = QE_SNUM_STATE_FREE; } @@ -280,7 +285,7 @@ int qe_get_snum(void) int i; spin_lock_irqsave(&qe_lock, flags); - for (i = 0; i < QE_NUM_OF_SNUM; i++) { + for (i = 0; i < qe_num_of_snum; i++) { if (snums[i].state == QE_SNUM_STATE_FREE) { snums[i].state = QE_SNUM_STATE_USED; snum = snums[i].num; @@ -297,7 +302,7 @@ void qe_put_snum(u8 snum) { int i; - for (i = 0; i < QE_NUM_OF_SNUM; i++) { + for (i = 0; i < qe_num_of_snum; i++) { if (snums[i].num == snum) { snums[i].state = QE_SNUM_STATE_FREE; break; @@ -603,3 +608,37 @@ unsigned int qe_get_num_of_risc(void) } EXPORT_SYMBOL(qe_get_num_of_risc); +unsigned int qe_get_num_of_snums(void) +{ + struct device_node *qe; + int size; + unsigned int num_of_snums; + const u32 *prop; + + num_of_snums = 28; /* The default number of snum for threads is 28 */ + qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); + if (!qe) { + /* Older devices trees did not have an "fsl,qe" + * compatible property, so we need to look for + * the QE node by name. + */ + qe = of_find_node_by_type(NULL, "qe"); + if (!qe) + return num_of_snums; + } + + prop = of_get_property(qe, "fsl,qe-num-snums", &size); + if (prop && size == sizeof(*prop)) { + num_of_snums = *prop; + if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) { + /* No QE ever has fewer than 28 SNUMs */ + pr_err("QE: number of snum is invalid\n"); + return -EINVAL; + } + } + + of_node_put(qe); + + return num_of_snums; +} +EXPORT_SYMBOL(qe_get_num_of_snums); -- cgit From bfa568d19a3faed3b94978ad48ac15d1b0d7e5bc Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Sat, 2 May 2009 06:16:47 +0400 Subject: powerpc/85xx: Add PCI IDs for MPC8569 family processors This patch adds PCI IDs for MPC8569 and MPC8569E processors, plus adds appropriate quirks for these IDs, and thus makes PCI-E actually work on MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 376603df7c4..94d8b3feb1e 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -285,6 +285,8 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header); +DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header); +DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header); -- cgit From 3da34aae03d498ee62f75aa7467de93cce3030fd Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 12 May 2009 15:51:56 -0500 Subject: powerpc/fsl: Support unique MSI addresses per PCIe Root Complex Its feasible based on how the PCI address map is setup that the region of PCI address space used for MSIs differs for each PHB on the same SoC. Instead of assuming that the address mappes to CCSRBAR 1:1 we read PEXCSRBAR (BAR0) for the PHB that the given pci_dev is on. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_msi.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index f25ce818d40..da38a1ff97b 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c @@ -113,8 +113,13 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, struct msi_msg *msg) { struct fsl_msi *msi_data = fsl_msi; + struct pci_controller *hose = pci_bus_to_host(pdev->bus); + u32 base = 0; - msg->address_lo = msi_data->msi_addr_lo; + pci_bus_read_config_dword(hose->bus, + PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); + + msg->address_lo = msi_data->msi_addr_lo + base; msg->address_hi = msi_data->msi_addr_hi; msg->data = hwirq; @@ -271,7 +276,7 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev, msi->irqhost->host_data = msi; msi->msi_addr_hi = 0x0; - msi->msi_addr_lo = res.start + features->msiir_offset; + msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff); rc = fsl_msi_init_allocator(msi); if (rc) { -- cgit From fc274a15692b0ee9751f586d7f703267c783809b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 13 May 2009 17:02:24 -0500 Subject: powerpc/fsl_rio: Fix compile warnings We we build with resource_size_t as a 64-bit quantity we get: arch/powerpc/sysdev/fsl_rio.c: In function 'fsl_rio_setup': arch/powerpc/sysdev/fsl_rio.c:1029: warning: format '%08x' expects type 'unsigned int', but argument 4 has type 'resource_size_t' arch/powerpc/sysdev/fsl_rio.c:1029: warning: format '%08x' expects type 'unsigned int', but argument 5 has type 'resource_size_t' Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_rio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index abdb124e1e2..c5aa179fceb 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -1026,8 +1026,7 @@ int fsl_rio_setup(struct of_device *dev) return -EFAULT; } dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name); - dev_info(&dev->dev, "Regs start 0x%08x size 0x%08x\n", regs.start, - regs.end - regs.start + 1); + dev_info(&dev->dev, "Regs: %pR\n", ®s); dt_range = of_get_property(dev->node, "ranges", &rlen); if (!dt_range) { -- cgit From 186e74b9c5ab3f3f053797c879882a1f5c0cbd09 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 May 2009 16:35:59 +0800 Subject: powerpc/fsl_rio: use LAW address from device tree Instead of fixed address in old code. Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_rio.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index c5aa179fceb..39db9d1155d 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -1076,8 +1076,9 @@ int fsl_rio_setup(struct of_device *dev) INIT_LIST_HEAD(&port->dbells); port->iores.start = law_start; - port->iores.end = law_start + law_size; + port->iores.end = law_start + law_size - 1; port->iores.flags = IORESOURCE_MEM; + port->iores.name = "rio_io_win"; priv->bellirq = irq_of_parse_and_map(dev->node, 2); priv->txirq = irq_of_parse_and_map(dev->node, 3); @@ -1155,14 +1156,15 @@ int fsl_rio_setup(struct of_device *dev) out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA); /* Configure maintenance transaction window */ - out_be32(&priv->maint_atmu_regs->rowbar, 0x000c0000); - out_be32(&priv->maint_atmu_regs->rowar, 0x80077015); + out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12); + out_be32(&priv->maint_atmu_regs->rowar, 0x80077015); /* 4M */ priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); /* Configure outbound doorbell window */ - out_be32(&priv->dbell_atmu_regs->rowbar, 0x000c0400); - out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); + out_be32(&priv->dbell_atmu_regs->rowbar, + (law_start + RIO_MAINT_WIN_SIZE) >> 12); + out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */ fsl_rio_doorbell_init(port); return 0; -- cgit From 01af9507ff36578dad89b1cc88ff37ac18e719cb Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 15 Apr 2009 14:38:40 -0500 Subject: powerpc/85xx: Add P2020DS board support The P2020 is a dual e500v2 core based SOC with: * 3 PCIe controllers * 2 General purpose DMA controllers * 2 sRIO controllers * 3 eTSECS * USB 2.0 * SDHC * SPI, I2C, DUART * enhanced localbus * and optional Security (P2020E) security w/XOR acceleration The p2020 DS reference board is pretty similar to the existing MPC85xx DS boards and has a ULI 1575 connected on one of the PCIe controllers. Signed-off-by: Ted Peters Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 94d8b3feb1e..b20171d9df0 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -302,6 +302,8 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); +DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header); +DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header); #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */ #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) -- cgit From 54c181935d2a2d46a1b2f00cbb25acc35e4f5ee2 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 8 May 2009 15:05:23 -0500 Subject: powerpc/fsl: Setup PCI inbound window based on actual amount of memory Previouslly we just always set the inbound window to 2G. This was broken for systems with >2G. If a system has >=4G we will need SWIOTLB support to handle that case. We now allocate PCICSRBAR/PEXCSRBAR right below the lowest PCI outbound address for MMIO or the 4G boundary (if the lowest PCI address is above 4G). Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 130 +++++++++++++++++++++++++++++++++++------- arch/powerpc/sysdev/fsl_pci.h | 6 +- 2 files changed, 115 insertions(+), 21 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index b20171d9df0..0de91c62e3d 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include #include #include @@ -96,7 +98,13 @@ static void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) { struct ccsr_pci __iomem *pci; - int i, j, n; + int i, j, n, mem_log, win_idx = 2; + u64 mem, sz, paddr_hi = 0; + u64 paddr_lo = ULLONG_MAX; + u32 pcicsrbar = 0, pcicsrbar_sz; + u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; + char *name = hose->dn->full_name; pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); @@ -117,6 +125,9 @@ static void __init setup_pci_atmu(struct pci_controller *hose, if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) continue; + paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); + paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); + n = setup_one_atmu(pci, j, &hose->mem_resources[i], hose->pci_mem_offset); @@ -147,14 +158,105 @@ static void __init setup_pci_atmu(struct pci_controller *hose, } } - /* Setup 2G inbound Memory Window @ 1 */ - out_be32(&pci->piw[2].pitar, 0x00000000); - out_be32(&pci->piw[2].piwbar,0x00000000); - out_be32(&pci->piw[2].piwar, PIWAR_2G); + /* convert to pci address space */ + paddr_hi -= hose->pci_mem_offset; + paddr_lo -= hose->pci_mem_offset; + + if (paddr_hi == paddr_lo) { + pr_err("%s: No outbound window space\n", name); + return ; + } + + if (paddr_lo == 0) { + pr_err("%s: No space for inbound window\n", name); + return ; + } + + /* setup PCSRBAR/PEXCSRBAR */ + early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); + early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); + pcicsrbar_sz = ~pcicsrbar_sz + 1; + + if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || + (paddr_lo > 0x100000000ull)) + pcicsrbar = 0x100000000ull - pcicsrbar_sz; + else + pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; + early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); + + paddr_lo = min(paddr_lo, (u64)pcicsrbar); - /* Save the base address and size covered by inbound window mappings */ - hose->dma_window_base_cur = 0x00000000; - hose->dma_window_size = 0x80000000; + pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); + + /* Setup inbound mem window */ + mem = lmb_end_of_DRAM(); + sz = min(mem, paddr_lo); + mem_log = __ilog2_u64(sz); + + /* PCIe can overmap inbound & outbound since RX & TX are separated */ + if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { + /* Size window to exact size if power-of-two or one size up */ + if ((1ull << mem_log) != mem) { + if ((1ull << mem_log) > mem) + pr_info("%s: Setting PCI inbound window " + "greater than memory size\n", name); + mem_log++; + } + + piwar |= (mem_log - 1); + + /* Setup inbound memory window */ + out_be32(&pci->piw[win_idx].pitar, 0x00000000); + out_be32(&pci->piw[win_idx].piwbar, 0x00000000); + out_be32(&pci->piw[win_idx].piwar, piwar); + win_idx--; + + hose->dma_window_base_cur = 0x00000000; + hose->dma_window_size = (resource_size_t)sz; + } else { + u64 paddr = 0; + + /* Setup inbound memory window */ + out_be32(&pci->piw[win_idx].pitar, paddr >> 12); + out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); + out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); + win_idx--; + + paddr += 1ull << mem_log; + sz -= 1ull << mem_log; + + if (sz) { + mem_log = __ilog2_u64(sz); + piwar |= (mem_log - 1); + + out_be32(&pci->piw[win_idx].pitar, paddr >> 12); + out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); + out_be32(&pci->piw[win_idx].piwar, piwar); + win_idx--; + + paddr += 1ull << mem_log; + } + + hose->dma_window_base_cur = 0x00000000; + hose->dma_window_size = (resource_size_t)paddr; + } + + if (hose->dma_window_size < mem) { +#ifndef CONFIG_SWIOTLB + pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " + "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", + name); +#endif + /* adjusting outbound windows could reclaim space in mem map */ + if (paddr_hi < 0xffffffffull) + pr_warning("%s: WARNING: Outbound window cfg leaves " + "gaps in memory map. Adjusting the memory map " + "could reduce unnecessary bounce buffering.\n", + name); + + pr_info("%s: DMA window size is 0x%llx\n", name, + (u64)hose->dma_window_size); + } iounmap(pci); } @@ -180,16 +282,6 @@ static void __init setup_pci_cmd(struct pci_controller *hose) } } -static void __init setup_pci_pcsrbar(struct pci_controller *hose) -{ -#ifdef CONFIG_PCI_MSI - phys_addr_t immr_base; - - immr_base = get_immrbase(); - early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base); -#endif -} - void fsl_pcibios_fixup_bus(struct pci_bus *bus) { struct pci_controller *hose = (struct pci_controller *) bus->sysdata; @@ -273,8 +365,6 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) /* Setup PEX window registers */ setup_pci_atmu(hose, &rsrc); - /* Setup PEXCSRBAR */ - setup_pci_pcsrbar(hose); return 0; } diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 13f30c2a61e..a9d8bbebed8 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -16,7 +16,11 @@ #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ #define PCIE_LTSSM_L0 0x16 /* L0 state */ -#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ +#define PIWAR_EN 0x80000000 /* Enable */ +#define PIWAR_PF 0x20000000 /* prefetch */ +#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 /* PCI/PCI Express outbound window reg */ struct pci_outbound_window_regs { -- cgit From d69a78d7daada190b42269a73daabe32a5e138a6 Mon Sep 17 00:00:00 2001 From: Tony Breeds Date: Tue, 7 Apr 2009 18:26:54 +0000 Subject: powerpc/mpic: Cleanup mpic_find() implementation mpic_find() was overloaded to do two things, finding the mpic instance for a given interrupt and returning if it's an IPI. Instead we introduce mpic_is_ipi() and simplify mpic_find() to just return the mpic instance Also silences the warning: arch/powerpc/sysdev/mpic.c: In function 'mpic_irq_set_priority': arch/powerpc/sysdev/mpic.c:1382: warning: 'is_ipi' may be used uninitialized in this function Signed-off-by: Tony Breeds Acked-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/mpic.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 0efc12d1a3d..bbee441ae86 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -613,23 +613,23 @@ static int irq_choose_cpu(unsigned int virt_irq) #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) /* Find an mpic associated with a given linux interrupt */ -static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) +static struct mpic *mpic_find(unsigned int irq) { - unsigned int src = mpic_irq_to_hw(irq); - struct mpic *mpic; - if (irq < NUM_ISA_INTERRUPTS) return NULL; - mpic = irq_desc[irq].chip_data; + return irq_desc[irq].chip_data; +} - if (is_ipi) - *is_ipi = (src >= mpic->ipi_vecs[0] && - src <= mpic->ipi_vecs[3]); +/* Determine if the linux irq is an IPI */ +static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) +{ + unsigned int src = mpic_irq_to_hw(irq); - return mpic; + return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); } + /* Convert a cpu mask from logical to physical cpu numbers. */ static inline u32 mpic_physmask(u32 cpumask) { @@ -1381,8 +1381,7 @@ void __init mpic_set_serial_int(struct mpic *mpic, int enable) void mpic_irq_set_priority(unsigned int irq, unsigned int pri) { - unsigned int is_ipi; - struct mpic *mpic = mpic_find(irq, &is_ipi); + struct mpic *mpic = mpic_find(irq); unsigned int src = mpic_irq_to_hw(irq); unsigned long flags; u32 reg; @@ -1391,7 +1390,7 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri) return; spin_lock_irqsave(&mpic_lock, flags); - if (is_ipi) { + if (mpic_is_ipi(mpic, irq)) { reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & ~MPIC_VECPRI_PRIORITY_MASK; mpic_ipi_write(src - mpic->ipi_vecs[0], -- cgit From 19afa40797a3b392b64bf0b30b46e62001eeb66f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 30 Apr 2009 03:10:07 +0000 Subject: powerpc/pci: Clean up direct access to sysdata by indirect ops We shouldn't directly access sysdata to get the pci_controller. Instead use pci_bus_to_host() for this purpose. In the future we might have sysdata be a device_node to match ppc64 and unify the code between ppc32 & ppc64. Signed-off-by: Kumar Gala Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/indirect_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index 7fd49c97501..7ed80967664 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -24,7 +24,7 @@ static int indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; u8 cfg_type = 0; u32 bus_no, reg; @@ -82,7 +82,7 @@ static int indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; u8 cfg_type = 0; u32 bus_no, reg; -- cgit From 8206a110cbaa029570d037c0aeafeb181443b6b8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 30 Apr 2009 03:10:08 +0000 Subject: powerpc/pci: Clean up direct access to sysdata by FSL platforms We shouldn't directly access sysdata to get the pci_controller. Instead use pci_bus_to_host() for this purpose. In the future we might have sysdata be a device_node to match ppc64 and unify the code between ppc32 & ppc64. Signed-off-by: Kumar Gala Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/fsl_pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 0de91c62e3d..ae88b144801 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -284,7 +284,7 @@ static void __init setup_pci_cmd(struct pci_controller *hose) void fsl_pcibios_fixup_bus(struct pci_bus *bus) { - struct pci_controller *hose = (struct pci_controller *) bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); int i; if ((bus->parent == hose->bus) && @@ -422,7 +422,7 @@ struct mpc83xx_pcie_priv { static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) { - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) return PCIBIOS_DEVICE_NOT_FOUND; @@ -448,7 +448,7 @@ static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, unsigned int devfn, int offset) { - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); struct mpc83xx_pcie_priv *pcie = hose->dn->data; u8 bus_no = bus->number - hose->first_busno; u32 dev_base = bus_no << 24 | devfn << 16; -- cgit From f159edaef31da2ba01511d1f7b2fe22bb048290f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 30 Apr 2009 03:10:10 +0000 Subject: powerpc/pci: Clean up direct access to sysdata by 4xx platforms We shouldn't directly access sysdata to get the pci_controller. Instead use pci_bus_to_host() for this purpose. In the future we might have sysdata be a device_node to match ppc64 and unify the code between ppc32 & ppc64. Signed-off-by: Kumar Gala Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/ppc4xx_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index 6a2d473c345..daefc93ddff 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c @@ -1295,7 +1295,7 @@ static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { - struct pci_controller *hose = (struct pci_controller *) bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); struct ppc4xx_pciex_port *port = &ppc4xx_pciex_ports[hose->indirect_type]; void __iomem *addr; @@ -1352,7 +1352,7 @@ static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { - struct pci_controller *hose = (struct pci_controller *) bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); struct ppc4xx_pciex_port *port = &ppc4xx_pciex_ports[hose->indirect_type]; void __iomem *addr; -- cgit From bccd6f73f0a81b91655ab63d09bd60f7fbb3231b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 30 Apr 2009 03:10:12 +0000 Subject: powerpc/pci: Clean up direct access to sysdata on tsi108 platforms We shouldn't directly access sysdata to get the pci_controller. Instead use pci_bus_to_host() for this purpose. In the future we might have sysdata be a device_node to match ppc64 and unify the code between ppc32 & ppc64. Signed-off-by: Kumar Gala Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/tsi108_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c index 24e1f5a197a..cf244a419e9 100644 --- a/arch/powerpc/sysdev/tsi108_pci.c +++ b/arch/powerpc/sysdev/tsi108_pci.c @@ -63,7 +63,7 @@ tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc, int offset, int len, u32 val) { volatile unsigned char *cfg_addr; - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); if (ppc_md.pci_exclude_device) if (ppc_md.pci_exclude_device(hose, bus->number, devfunc)) @@ -149,7 +149,7 @@ tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 * val) { volatile unsigned char *cfg_addr; - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); u32 temp; if (ppc_md.pci_exclude_device) -- cgit From 64f16502475ddf663169369fffff6da9b10ea9fb Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Sat, 6 Jun 2009 10:14:22 -0600 Subject: powerpc/virtex: Add support for Xilinx PCI host bridge This patch adds support for the Xilinx plbv46-pci-1.03.a PCI host bridge IPcore. Signed-off-by: Roderick Colenbrander Signed-off-by: Grant Likely --- arch/powerpc/sysdev/Makefile | 1 + arch/powerpc/sysdev/xilinx_pci.c | 132 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/powerpc/sysdev/xilinx_pci.c (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index b33b28a6fe1..2d1c87dd5d1 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_IPIC) += ipic.o obj-$(CONFIG_4xx) += uic.o obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o +obj-$(CONFIG_XILINX_PCI) += xilinx_pci.o obj-$(CONFIG_OF_RTC) += of_rtc.o ifeq ($(CONFIG_PCI),y) obj-$(CONFIG_4xx) += ppc4xx_pci.o diff --git a/arch/powerpc/sysdev/xilinx_pci.c b/arch/powerpc/sysdev/xilinx_pci.c new file mode 100644 index 00000000000..1453b0eed22 --- /dev/null +++ b/arch/powerpc/sysdev/xilinx_pci.c @@ -0,0 +1,132 @@ +/* + * PCI support for Xilinx plbv46_pci soft-core which can be used on + * Xilinx Virtex ML410 / ML510 boards. + * + * Copyright 2009 Roderick Colenbrander + * Copyright 2009 Secret Lab Technologies Ltd. + * + * The pci bridge fixup code was copied from ppc4xx_pci.c and was written + * by Benjamin Herrenschmidt. + * Copyright 2007 Ben. Herrenschmidt , IBM Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include + +#define XPLB_PCI_ADDR 0x10c +#define XPLB_PCI_DATA 0x110 +#define XPLB_PCI_BUS 0x114 + +#define PCI_HOST_ENABLE_CMD PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY + +static struct of_device_id xilinx_pci_match[] = { + { .compatible = "xlnx,plbv46-pci-1.03.a", }, + {} +}; + +/** + * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration. + */ +static void xilinx_pci_fixup_bridge(struct pci_dev *dev) +{ + struct pci_controller *hose; + int i; + + if (dev->devfn || dev->bus->self) + return; + + hose = pci_bus_to_host(dev->bus); + if (!hose) + return; + + if (!of_match_node(xilinx_pci_match, hose->dn)) + return; + + /* Hide the PCI host BARs from the kernel as their content doesn't + * fit well in the resource management + */ + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + + dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n", + pci_name(dev)); +} +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge); + +/** + * xilinx_pci_exclude_device - Don't do config access for non-root bus + * + * This is a hack. Config access to any bus other than bus 0 does not + * currently work on the ML510 so we prevent it here. + */ +static int +xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn) +{ + return (bus != 0); +} + +/** + * xilinx_pci_init - Find and register a Xilinx PCI host bridge + */ +void __init xilinx_pci_init(void) +{ + struct pci_controller *hose; + struct resource r; + void __iomem *pci_reg; + struct device_node *pci_node; + + pci_node = of_find_matching_node(NULL, xilinx_pci_match); + if(!pci_node) + return; + + if (of_address_to_resource(pci_node, 0, &r)) { + pr_err("xilinx-pci: cannot resolve base address\n"); + return; + } + + hose = pcibios_alloc_controller(pci_node); + if (!hose) { + pr_err("xilinx-pci: pcibios_alloc_controller() failed\n"); + return; + } + + /* Setup config space */ + setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR, + r.start + XPLB_PCI_DATA, + PPC_INDIRECT_TYPE_SET_CFG_TYPE); + + /* According to the xilinx plbv46_pci documentation the soft-core starts + * a self-init when the bus master enable bit is set. Without this bit + * set the pci bus can't be scanned. + */ + early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD); + + /* Set the max latency timer to 255 */ + early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff); + + /* Set the max bus number to 255 */ + pci_reg = of_iomap(pci_node, 0); + out_8(pci_reg + XPLB_PCI_BUS, 0xff); + iounmap(pci_reg); + + /* Nothing past the root bridge is working right now. By default + * exclude config access to anything except bus 0 */ + if (!ppc_md.pci_exclude_device) + ppc_md.pci_exclude_device = xilinx_pci_exclude_device; + + /* Register the host bridge with the linux kernel! */ + pci_process_bridge_OF_ranges(hose, pci_node, 1); + + pr_info("xilinx-pci: Registered PCI host bridge\n"); +} -- cgit From 1745fbc744a934b235c2e5ecb5380079fa54be38 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Sat, 6 Jun 2009 10:15:03 -0600 Subject: powerpc/virtex: refactor intc driver and add support for i8259 cascading This patch refactors some of the xilinx_intc interrupt controller driver and adds support for cascading an i8259 off one of the irq lines. This patch was based on the ML510 support work done by Roderick Colenbrander. Signed-off-by: Grant Likely --- arch/powerpc/sysdev/xilinx_intc.c | 76 +++++++++++++++++++++++++++++---------- 1 file changed, 58 insertions(+), 18 deletions(-) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c index c658b413c9b..90b57724a5e 100644 --- a/arch/powerpc/sysdev/xilinx_intc.c +++ b/arch/powerpc/sysdev/xilinx_intc.c @@ -25,6 +25,7 @@ #include #include #include +#include #include /* @@ -191,20 +192,14 @@ struct irq_host * __init xilinx_intc_init(struct device_node *np) { struct irq_host * irq; - struct resource res; void * regs; - int rc; /* Find and map the intc registers */ - rc = of_address_to_resource(np, 0, &res); - if (rc) { - printk(KERN_ERR __FILE__ ": of_address_to_resource() failed\n"); + regs = of_iomap(np, 0); + if (!regs) { + pr_err("xilinx_intc: could not map registers\n"); return NULL; } - regs = ioremap(res.start, 32); - - printk(KERN_INFO "Xilinx intc at 0x%08llx mapped to 0x%p\n", - (unsigned long long) res.start, regs); /* Setup interrupt controller */ out_be32(regs + XINTC_IER, 0); /* disable all irqs */ @@ -217,6 +212,7 @@ xilinx_intc_init(struct device_node *np) if (!irq) panic(__FILE__ ": Cannot allocate IRQ host\n"); irq->host_data = regs; + return irq; } @@ -227,23 +223,65 @@ int xilinx_intc_get_irq(void) return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR)); } +#if defined(CONFIG_PPC_I8259) +/* + * Support code for cascading to 8259 interrupt controllers + */ +static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) +{ + unsigned int cascade_irq = i8259_irq(); + if (cascade_irq) + generic_handle_irq(cascade_irq); + + /* Let xilinx_intc end the interrupt */ + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +static void __init xilinx_i8259_setup_cascade(void) +{ + struct device_node *cascade_node; + int cascade_irq; + + /* Initialize i8259 controller */ + cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic"); + if (!cascade_node) + return; + + cascade_irq = irq_of_parse_and_map(cascade_node, 0); + if (!cascade_irq) { + pr_err("virtex_ml510: Failed to map cascade interrupt\n"); + goto out; + } + + i8259_init(cascade_node, 0); + set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade); + + out: + of_node_put(cascade_node); +} +#else +static inline void xilinx_i8259_setup_cascade(void) { return; } +#endif /* defined(CONFIG_PPC_I8259) */ + +static struct of_device_id xilinx_intc_match[] __initconst = { + { .compatible = "xlnx,opb-intc-1.00.c", }, + { .compatible = "xlnx,xps-intc-1.00.a", }, + {} +}; + +/* + * Initialize master Xilinx interrupt controller + */ void __init xilinx_intc_init_tree(void) { struct device_node *np; /* find top level interrupt controller */ - for_each_compatible_node(np, NULL, "xlnx,opb-intc-1.00.c") { + for_each_matching_node(np, xilinx_intc_match) { if (!of_get_property(np, "interrupts", NULL)) break; } - if (!np) { - for_each_compatible_node(np, NULL, "xlnx,xps-intc-1.00.a") { - if (!of_get_property(np, "interrupts", NULL)) - break; - } - } - - /* xilinx interrupt controller needs to be top level */ BUG_ON(!np); master_irqhost = xilinx_intc_init(np); @@ -251,4 +289,6 @@ void __init xilinx_intc_init_tree(void) irq_set_default_host(master_irqhost); of_node_put(np); + + xilinx_i8259_setup_cascade(); } -- cgit From e52ba9c54176c9757ab6b18bea7b7ed51e2faf16 Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Sat, 6 Jun 2009 10:15:24 -0600 Subject: powerpc/virtex: Add Xilinx ML510 reference design support Signed-off-by: Roderick Colenbrander Signed-off-by: Grant Likely --- arch/powerpc/sysdev/xilinx_intc.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/powerpc/sysdev') diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c index 90b57724a5e..3ee1fd37bbf 100644 --- a/arch/powerpc/sysdev/xilinx_intc.c +++ b/arch/powerpc/sysdev/xilinx_intc.c @@ -257,6 +257,11 @@ static void __init xilinx_i8259_setup_cascade(void) i8259_init(cascade_node, 0); set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade); + /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */ + /* This looks like a dirty hack to me --gcl */ + outb(0xc0, 0x4d0); + outb(0xc0, 0x4d1); + out: of_node_put(cascade_node); } -- cgit