From 3b1d4ed5353af04d6aa20be2701727b9cdb2ac61 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 20 Jun 2007 22:27:10 +0100 Subject: [MIPS] Don't drag a platform specific header into generic arch code. For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle --- arch/mips/kernel/smtc.c | 6 +++--- arch/mips/kernel/time.c | 13 +++++++++---- arch/mips/kernel/traps.c | 20 +++++++++++++++++--- 3 files changed, 29 insertions(+), 10 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 21eb5993a19..2e011470c34 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -13,9 +13,9 @@ #include #include #include +#include #include #include -#include #include #include #include @@ -614,7 +614,7 @@ int setup_irq_smtc(unsigned int irq, struct irqaction * new, #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG unsigned int vpe = current_cpu_data.vpe_id; - vpemask[vpe][irq - MIPSCPU_INT_BASE] = 1; + vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1; #endif irq_hwmask[irq] = hwmask; @@ -822,7 +822,7 @@ void ipi_decode(struct smtc_ipi *pipi) switch (type_copy) { case SMTC_CLOCK_TICK: irq_enter(); - kstat_this_cpu.irqs[MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR]++; + kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_perfcount_irq]++; /* Invoke Clock "Interrupt" */ ipi_timer_latch[dest_copy] = 0; #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 7def1ff3da9..d48d1d5bea0 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -199,11 +199,16 @@ int (*perf_irq)(void) = null_perf_irq; EXPORT_SYMBOL(null_perf_irq); EXPORT_SYMBOL(perf_irq); +/* + * Timer interrupt + */ +int cp0_compare_irq; + /* * Performance counter IRQ or -1 if shared with timer */ -int mipsxx_perfcount_irq; -EXPORT_SYMBOL(mipsxx_perfcount_irq); +int cp0_perfcount_irq; +EXPORT_SYMBOL_GPL(cp0_perfcount_irq); /* * Possibly handle a performance counter interrupt. @@ -213,12 +218,12 @@ static inline int handle_perf_irq (int r2) { /* * The performance counter overflow interrupt may be shared with the - * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a + * timer interrupt (cp0_perfcount_irq < 0). If it is and a * performance counter has overflowed (perf_irq() == IRQ_HANDLED) * and we can't reliably determine if a counter interrupt has also * happened (!r2) then don't check for a timer interrupt. */ - return (mipsxx_perfcount_irq < 0) && + return (cp0_perfcount_irq < 0) && perf_irq() == IRQ_HANDLED && !r2; } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index a7a17eb9bfc..b1233644fcc 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1350,9 +1350,6 @@ void __init per_cpu_trap_init(void) if (!secondaryTC) { #endif /* CONFIG_MIPS_MT_SMTC */ - /* - * Interrupt handling. - */ if (cpu_has_veic || cpu_has_vint) { write_c0_ebase (ebase); /* Setting vector spacing enables EI/VI mode */ @@ -1366,6 +1363,23 @@ void __init per_cpu_trap_init(void) } else set_c0_cause(CAUSEF_IV); } + + /* + * Before R2 both interrupt numbers were fixed to 7, so on R2 only: + * + * o read IntCtl.IPTI to determine the timer interrupt + * o read IntCtl.IPPCI to determine the performance counter interrupt + */ + if (cpu_has_mips_r2) { + cp0_compare_irq = (read_c0_intctl () >> 29) & 7; + cp0_perfcount_irq = -1; + } else { + cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; + cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7; + if (cp0_perfcount_irq != cp0_compare_irq) + cp0_perfcount_irq = -1; + } + #ifdef CONFIG_MIPS_MT_SMTC } #endif /* CONFIG_MIPS_MT_SMTC */ -- cgit