From a0dd005d1d9f4c3beab52086f3844ef9342d1e67 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 17 Feb 2008 10:35:15 +0000 Subject: [ARM] pxa: fix clock lookup to find specific device clocks Ensure that the clock lookup always finds an entry for a specific device and ID before it falls back to finding just by ID. This fixes a problem reported by Holger Schurig where the BTUART was assigned the wrong clock. Tested-by: Holger Schurig Signed-off-by: Russell King --- arch/arm/mach-pxa/clock.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index 83ef5ecaf43..df5ae2710ab 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c @@ -23,18 +23,27 @@ static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clocks_lock); +static struct clk *clk_lookup(struct device *dev, const char *id) +{ + struct clk *p; + + list_for_each_entry(p, &clocks, node) + if (strcmp(id, p->name) == 0 && p->dev == dev) + return p; + + return NULL; +} + struct clk *clk_get(struct device *dev, const char *id) { struct clk *p, *clk = ERR_PTR(-ENOENT); mutex_lock(&clocks_mutex); - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && - (p->dev == NULL || p->dev == dev)) { - clk = p; - break; - } - } + p = clk_lookup(dev, id); + if (!p) + p = clk_lookup(NULL, id); + if (p) + clk = p; mutex_unlock(&clocks_mutex); return clk; -- cgit From 59e8ce574445c5e7a65ec36f47a54803de704e96 Mon Sep 17 00:00:00 2001 From: Byron Bradley Date: Sun, 10 Feb 2008 22:31:09 +0100 Subject: [ARM] 4826/1: Orion: Register the RTC interrupt on the TS-209 The QNAP TS-209 has its RTC interrupt on GPIO 3. Setup this as an interrupt and pass it to the i2c_board_info. Signed-off-by: Byron Bradley Acked-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/mach-orion/ts209-setup.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c index 306dbcd1e37..b8cfe6813e9 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion/ts209-setup.c @@ -192,9 +192,13 @@ static struct mv643xx_eth_platform_data qnap_ts209_eth_data = { /***************************************************************************** * RTC S35390A on I2C bus ****************************************************************************/ + +#define TS209_RTC_GPIO 3 + static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = { .driver_name = "rtc-s35390a", .addr = 0x30, + .irq = 0, }; /**************************************************************************** @@ -328,7 +332,18 @@ static void __init qnap_ts209_init(void) platform_add_devices(qnap_ts209_devices, ARRAY_SIZE(qnap_ts209_devices)); + + /* Get RTC IRQ and register the chip */ + if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) { + if (gpio_direction_input(TS209_RTC_GPIO) == 0) + qnap_ts209_i2c_rtc.irq = gpio_to_irq(TS209_RTC_GPIO); + else + gpio_free(TS209_RTC_GPIO); + } + if (qnap_ts209_i2c_rtc.irq == 0) + pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); + orion_eth_init(&qnap_ts209_eth_data); orion_sata_init(&qnap_ts209_sata_data); } -- cgit From ea833f0b5a8afcc698c5ccb06237902c0e21e032 Mon Sep 17 00:00:00 2001 From: Holger Schurig Date: Mon, 11 Feb 2008 16:53:15 +0100 Subject: [ARM] 4829/1: add .get method to pxa-cpufreq to silence a warning The .get method is needed for suspend/resume. Otherwise you get this in dmesg: cpufreq: suspend failed to assert current frequency is what timing core thinks it is. cpufreq: resume failed to assert current frequency is what timing core thinks it is. Signed-off-by: Holger Schurig Signed-off-by: Russell King --- arch/arm/mach-pxa/cpu-pxa.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c index cbc583beedc..939a3867f77 100644 --- a/arch/arm/mach-pxa/cpu-pxa.c +++ b/arch/arm/mach-pxa/cpu-pxa.c @@ -134,7 +134,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, struct cpufreq_frequency_table *pxa_freqs_table; pxa_freqs_t *pxa_freq_settings; struct cpufreq_freqs freqs; - int idx; + unsigned int idx; unsigned long flags; unsigned int unused, preset_mdrefr, postset_mdrefr; void *ramstart = phys_to_virt(0xa0000000); @@ -233,6 +233,11 @@ static int pxa_set_target(struct cpufreq_policy *policy, return 0; } +static unsigned int pxa_cpufreq_get(unsigned int cpu) +{ + return get_clk_frequency_khz(0); +} + static int pxa_cpufreq_init(struct cpufreq_policy *policy) { int i; @@ -269,6 +274,7 @@ static struct cpufreq_driver pxa_cpufreq_driver = { .verify = pxa_verify_policy, .target = pxa_set_target, .init = pxa_cpufreq_init, + .get = pxa_cpufreq_get, .name = "PXA25x", }; -- cgit From c9a2c46d7f32a884510b20f0cfa79a2c6a2f1413 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Sun, 24 Feb 2008 20:03:41 +0100 Subject: ARM: OMAP: Release i2c_adapter after use (Siemens SX1) Each call to i2c_get_adapter() must be followed by a call to i2c_put_adapter() to release the grabbed reference. Otherwise the reference count grows forever and the adapter can never be unregistered. Signed-off-by: Jean Delvare Acked-by: Vladimir Ananiev Acked-by: Tony Lindgren --- arch/arm/mach-omap1/board-sx1.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 1c7f09aedf0..e473fa6d4a5 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -61,6 +61,7 @@ int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) data[0] = regoffset; /* register num */ data[1] = value; /* register data */ err = i2c_transfer(adap, msg, 1); + i2c_put_adapter(adap); if (err >= 0) return 0; return err; @@ -91,6 +92,7 @@ int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value) msg->buf = data; err = i2c_transfer(adap, msg, 1); *value = data[0]; + i2c_put_adapter(adap); if (err >= 0) return 0; -- cgit From b98d7291883f7ed27e3f4b59bc12dc963c9f72a6 Mon Sep 17 00:00:00 2001 From: Uli Luckas Date: Fri, 22 Feb 2008 16:45:18 +0100 Subject: [ARM] 4836/1: Make ATAGS_PROC depend on KEXEC On Wed, Feb 20, 2008 at 11:50:33AM +0100, Guennadi Liakhovetski wrote: > arch/arm/kernel/atags.c uses for some reason the > KEXEC_BOOT_PARAMS_SIZE macro, which is only defined if CONFIG_KEXEC > is set. So, either this macro should be defined always, or another > macro should be used, or ATAGS_PROC should depend on KEXEC. As the procfs export of ATAGS is not meant as a stable, general purpose ABI it shouldn't be an independent, general configuration option. This patch make ATAGS_PROC depend on KEXEC Signed-off-by: Uli Luckas Signed-off-by: Russell King --- arch/arm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9619c43783f..16b82e1272b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -939,7 +939,8 @@ config KEXEC config ATAGS_PROC bool "Export atags in procfs" - default n + depends on KEXEC + default y help Should the atags used to boot the kernel be exported in an "atags" file in procfs. Useful with kexec. -- cgit From c710e39cbec4f3d60acd07f5356404a61bc1959a Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 27 Feb 2008 12:11:16 -0800 Subject: [ARM] eliminate MODULE_PARM() usage Convert debug-only (and removed) MODULE_PARM() to module_param(). Compiles cleanly (with DEBUG=1). Signed-off-by: Randy Dunlap Signed-off-by: Russell King --- arch/arm/mach-pxa/cpu-pxa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c index 939a3867f77..4b21479332a 100644 --- a/arch/arm/mach-pxa/cpu-pxa.c +++ b/arch/arm/mach-pxa/cpu-pxa.c @@ -43,7 +43,7 @@ #ifdef DEBUG static unsigned int freq_debug; -MODULE_PARM(freq_debug, "i"); +module_param(freq_debug, uint, 0); MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); #else #define freq_debug 0 -- cgit From 9ae3ae0bebb9a3a348dc233229008b126014889d Mon Sep 17 00:00:00 2001 From: Alexandre Rusev Date: Tue, 26 Feb 2008 18:42:10 +0100 Subject: [ARM] 4839/1: fixes kernel Oops in /dev/mem device driver for memory map with PHYS_OFF "cat /dev/mem" may cause kernel Oops for boards with PHYS_OFFSET != 0 because character device is mapped to addresses starting from zero and there is no protection against such situation. Patch just add this. Signed-off-by: Alexandre Rusev Signed-off-by: Russell King --- arch/arm/mm/mmap.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index 2728b0e7d2b..3f6dc40b835 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -120,6 +120,8 @@ full_search: */ int valid_phys_addr_range(unsigned long addr, size_t size) { + if (addr < PHYS_OFFSET) + return 0; if (addr + size > __pa(high_memory)) return 0; -- cgit From 7a987e82cd9175215dec6339d383d64e551c8899 Mon Sep 17 00:00:00 2001 From: eric miao Date: Wed, 27 Feb 2008 02:00:26 +0100 Subject: [ARM] 4841/1: pxa: fix typo in LCD platform data definition code for zylonite Signed-off-by: eric miao Signed-off-by: Russell King --- arch/arm/mach-pxa/zylonite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 7731d50dd86..afd2cbfca0d 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -58,7 +58,7 @@ static struct platform_device smc91x_device = { .resource = smc91x_resources, }; -#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULES) +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static void zylonite_backlight_power(int on) { gpio_set_value(gpio_backlight, on); -- cgit From ceee4f98f73bb7a1f6ee6710b9ebffd0ecb8c0ca Mon Sep 17 00:00:00 2001 From: eric miao Date: Wed, 27 Feb 2008 02:01:11 +0100 Subject: [ARM] 4842/1: pxa: remove redundant IRQ saving/restoring in clk_pxa3xx_cken_* This is unnecessary since it is already protected by spin_lock_irq{save, restore} in clock.c. Signed-off-by: eric miao Signed-off-by: Russell King --- arch/arm/mach-pxa/pxa3xx.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 7cd9ef8deb0..35f25fdaeba 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -129,28 +129,20 @@ static void clk_pxa3xx_cken_enable(struct clk *clk) { unsigned long mask = 1ul << (clk->cken & 0x1f); - local_irq_disable(); - if (clk->cken < 32) CKENA |= mask; else CKENB |= mask; - - local_irq_enable(); } static void clk_pxa3xx_cken_disable(struct clk *clk) { unsigned long mask = 1ul << (clk->cken & 0x1f); - local_irq_disable(); - if (clk->cken < 32) CKENA &= ~mask; else CKENB &= ~mask; - - local_irq_enable(); } static const struct clkops clk_pxa3xx_cken_ops = { -- cgit From 0c82d83cb09a1c9fd4d24d32064ce827709c104b Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 27 Feb 2008 13:44:59 +0100 Subject: [ARM] Fix freeing of page tables for ARM in free_pgd_slow MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since 2f569af (CONFIG_HIGHPTE vs. sub-page page tables.) pte_free() calls pte_lock_deinit() and dec_zone_page_state(). So free_pgd_slow must not call the latter two when calling the first. Signed-off-by: Uwe Kleine-König Cc: Martin Schwidefsky Cc: Andrew Morton Cc: Linus Torvalds Signed-off-by: Russell King --- arch/arm/mm/pgd.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index 500c9610ab3..e0f19ab9116 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -75,7 +75,7 @@ no_pgd: void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd) { pmd_t *pmd; - struct page *pte; + pgtable_t pte; if (!pgd) return; @@ -90,10 +90,8 @@ void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd) goto free; } - pte = pmd_page(*pmd); + pte = pmd_pgtable(*pmd); pmd_clear(pmd); - dec_zone_page_state(virt_to_page((unsigned long *)pgd), NR_PAGETABLE); - pte_lock_deinit(pte); pte_free(mm, pte); pmd_free(mm, pmd); free: -- cgit From 9edddaa200df18e08fe0cf21036e8ae467b1363c Mon Sep 17 00:00:00 2001 From: Ananth N Mavinakayanahalli Date: Tue, 4 Mar 2008 14:28:37 -0800 Subject: Kprobes: indicate kretprobe support in Kconfig Add CONFIG_HAVE_KRETPROBES to the arch//Kconfig file for relevant architectures with kprobes support. This facilitates easy handling of in-kernel modules (like samples/kprobes/kretprobe_example.c) that depend on kretprobes being present in the kernel. Thanks to Sam Ravnborg for helping make the patch more lean. Per Mathieu's suggestion, added CONFIG_KRETPROBES and fixed up dependencies. Signed-off-by: Ananth N Mavinakayanahalli Acked-by: Mathieu Desnoyers Acked-by: Ingo Molnar Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 16b82e1272b..955fc53c1c0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -12,6 +12,7 @@ config ARM select SYS_SUPPORTS_APM_EMULATION select HAVE_OPROFILE select HAVE_KPROBES if (!XIP_KERNEL) + select HAVE_KRETPROBES if (HAVE_KPROBES) help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and -- cgit From 538528de0cb256f65716ab2e9613d9e920f97fe2 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Wed, 13 Feb 2008 11:47:29 +0200 Subject: ARM: OMAP: Pass logical DMA channel number always to callback handlers This makes parameter passing to DMA handlers uniform between non-chained and chained transfers and makes debugging easier. Additional data like chain_id can be always passed to handlers via callback data if needed. Signed-off-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dma.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index a46676db811..3e94683c966 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1705,14 +1705,8 @@ static int omap2_dma_handle_ch(int ch) status = OMAP_DMA_CSR_REG(ch); } - if (likely(dma_chan[ch].callback != NULL)) { - if (dma_chan[ch].chain_id != -1) - dma_chan[ch].callback(dma_chan[ch].chain_id, status, - dma_chan[ch].data); - else - dma_chan[ch].callback(ch, status, dma_chan[ch].data); - - } + if (likely(dma_chan[ch].callback != NULL)) + dma_chan[ch].callback(ch, status, dma_chan[ch].data); OMAP_DMA_CSR_REG(ch) = status; -- cgit From b8488fbe6d2f32ff4ad2f8f348a50e42389fc727 Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU Date: Thu, 30 Aug 2007 12:46:39 +0300 Subject: ARM: OMAP: Fix sleep under spinlock for cpufreq [ 10.523437] BUG: sleeping function called from invalid context at kernel/mut6 [ 10.523437] in_atomic():0, irqs_disabled():128 [ 10.523437] [] (dump_stack+0x0/0x14) from [] (__might_sl) [ 10.523437] [] (__might_sleep+0x0/0xd4) from [] (mutex_l) [ 10.523437] r5 = C02F0DE8 r4 = C02F0DF0 [ 10.523437] [] (mutex_lock+0x0/0x44) from [] (clk_get+0x) [ 10.523437] r4 = 00000000 [ 10.523437] [] (clk_get+0x0/0x128) from [] (omap_getspee) [ 10.523437] r8 = 00000002 r7 = 00000000 r6 = C031DAF8 r5 = C0473980 [ 10.523437] r4 = 00000000 [ 10.523437] [] (omap_getspeed+0x0/0x5c) from [] (cpufreq) [ 10.523437] r5 = C0473980 r4 = 00000002 Signed-off-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/cpu-omap.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c index c0d63b0c61c..d719c15daa5 100644 --- a/arch/arm/plat-omap/cpu-omap.c +++ b/arch/arm/plat-omap/cpu-omap.c @@ -33,43 +33,33 @@ #define MPU_CLK "virt_prcm_set" #endif +static struct clk *mpu_clk; + /* TODO: Add support for SDRAM timing changes */ int omap_verify_speed(struct cpufreq_policy *policy) { - struct clk * mpu_clk; - if (policy->cpu) return -EINVAL; cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); - mpu_clk = clk_get(NULL, MPU_CLK); - if (IS_ERR(mpu_clk)) - return PTR_ERR(mpu_clk); + policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000; policy->max = clk_round_rate(mpu_clk, policy->max * 1000) / 1000; cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); - clk_put(mpu_clk); - return 0; } unsigned int omap_getspeed(unsigned int cpu) { - struct clk * mpu_clk; unsigned long rate; if (cpu) return 0; - mpu_clk = clk_get(NULL, MPU_CLK); - if (IS_ERR(mpu_clk)) - return 0; rate = clk_get_rate(mpu_clk) / 1000; - clk_put(mpu_clk); - return rate; } @@ -77,14 +67,9 @@ static int omap_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) { - struct clk * mpu_clk; struct cpufreq_freqs freqs; int ret = 0; - mpu_clk = clk_get(NULL, MPU_CLK); - if (IS_ERR(mpu_clk)) - return PTR_ERR(mpu_clk); - freqs.old = omap_getspeed(0); freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000; freqs.cpu = 0; @@ -92,15 +77,12 @@ static int omap_target(struct cpufreq_policy *policy, cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); ret = clk_set_rate(mpu_clk, target_freq * 1000); cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - clk_put(mpu_clk); return ret; } static int __init omap_cpu_init(struct cpufreq_policy *policy) { - struct clk * mpu_clk; - mpu_clk = clk_get(NULL, MPU_CLK); if (IS_ERR(mpu_clk)) return PTR_ERR(mpu_clk); @@ -111,17 +93,23 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy) policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000; policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; - clk_put(mpu_clk); return 0; } +static int omap_cpu_exit(struct cpufreq_policy *policy) +{ + clk_put(mpu_clk); + return 0; +} + static struct cpufreq_driver omap_driver = { .flags = CPUFREQ_STICKY, .verify = omap_verify_speed, .target = omap_target, .get = omap_getspeed, .init = omap_cpu_init, + .exit = omap_cpu_exit, .name = "omap", }; -- cgit From 8ba55c5c139f9be26b87d3aab9998f54d8d3057a Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 26 Feb 2008 11:10:50 -0800 Subject: ARM: OMAP: fix false lockdep warnings Remove false lockdep warnings about lock recursion when declaring IRQs as being wake-capable, by marking putting GPIO irq_desc locks into their own class. (Thanks to Peter Zijlstra for helping track down such a small fix to this problem.) Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 56f4d1394d5..9030495509f 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -1277,6 +1277,11 @@ static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS]; static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; #endif +/* This lock class tells lockdep that GPIO irqs are in a different + * category than their parents, so it won't report false recursion. + */ +static struct lock_class_key gpio_lock_class; + static int __init _omap_gpio_init(void) { int i; @@ -1450,6 +1455,7 @@ static int __init _omap_gpio_init(void) #endif for (j = bank->virtual_irq_start; j < bank->virtual_irq_start + gpio_count; j++) { + lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); set_irq_chip_data(j, bank); if (bank_is_mpuio(bank)) set_irq_chip(j, &mpuio_irq_chip); -- cgit From cfa9a63a9ad25fd3d3218a4e95f5a93090669f3c Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 26 Feb 2008 11:02:30 -0800 Subject: ARM: OMAP: fix omap i2c init (regression) In mainline, the "old style" I2C registration was only removed for OMAP2, leading to init-time bugs (regressions) like: sysfs: duplicate filename 'i2c_omap.1' can not be created ------------[ cut here ]------------ WARNING: at fs/sysfs/dir.c:424 sysfs_add_one+0x40/0xd4() Modules linked in: ... deletia ... [] (omap_init_i2c+0x0/0x50) from [] (omap_init_devices+0x10/0x24) r4:c001e000 [] (omap_init_devices+0x0/0x24) from [] (do_initcalls+0x78/0x200) ... deletia ... ---[ end trace ca143223eefdc828 ]--- kobject_add_internal failed for i2c_omap.1 with -EEXIST, don't try to register things with the same name in the same directory. The fix is obvious: remove the old init code, it's no longer needed. Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/devices.c | 63 -------------------------------------------- 1 file changed, 63 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index c5dab1d6417..4a53f9ba6c4 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -88,68 +88,6 @@ EXPORT_SYMBOL(dsp_kfunc_device_register); static inline void omap_init_dsp(void) { } #endif /* CONFIG_OMAP_DSP */ -/*-------------------------------------------------------------------------*/ -#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) - -#define OMAP1_I2C_BASE 0xfffb3800 -#define OMAP2_I2C_BASE1 0x48070000 -#define OMAP_I2C_SIZE 0x3f -#define OMAP1_I2C_INT INT_I2C -#define OMAP2_I2C_INT1 56 - -static struct resource i2c_resources1[] = { - { - .start = 0, - .end = 0, - .flags = IORESOURCE_MEM, - }, - { - .start = 0, - .flags = IORESOURCE_IRQ, - }, -}; - -/* DMA not used; works around erratum writing to non-empty i2c fifo */ - -static struct platform_device omap_i2c_device1 = { - .name = "i2c_omap", - .id = 1, - .num_resources = ARRAY_SIZE(i2c_resources1), - .resource = i2c_resources1, -}; - -/* See also arch/arm/mach-omap2/devices.c for second I2C on 24xx */ -static void omap_init_i2c(void) -{ - if (cpu_is_omap24xx()) { - i2c_resources1[0].start = OMAP2_I2C_BASE1; - i2c_resources1[0].end = OMAP2_I2C_BASE1 + OMAP_I2C_SIZE; - i2c_resources1[1].start = OMAP2_I2C_INT1; - } else { - i2c_resources1[0].start = OMAP1_I2C_BASE; - i2c_resources1[0].end = OMAP1_I2C_BASE + OMAP_I2C_SIZE; - i2c_resources1[1].start = OMAP1_I2C_INT; - } - - /* FIXME define and use a boot tag, in case of boards that - * either don't wire up I2C, or chips that mux it differently... - * it can include clocking and address info, maybe more. - */ - if (cpu_is_omap24xx()) { - omap_cfg_reg(M19_24XX_I2C1_SCL); - omap_cfg_reg(L15_24XX_I2C1_SDA); - } else { - omap_cfg_reg(I2C_SCL); - omap_cfg_reg(I2C_SDA); - } - - (void) platform_device_register(&omap_i2c_device1); -} - -#else -static inline void omap_init_i2c(void) {} -#endif - /*-------------------------------------------------------------------------*/ #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE) @@ -501,7 +439,6 @@ static int __init omap_init_devices(void) * in alphabetical order so they're easier to sort through. */ omap_init_dsp(); - omap_init_i2c(); omap_init_kp(); omap_init_mmc(); omap_init_uwire(); -- cgit From 0cc0a441163b92fbda5fe1886cb6e9876cf08f40 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 28 Feb 2008 14:44:08 -0800 Subject: ARM: OMAP1: omap h3 regression and build fix Get rid of build warnings and errors in mainline for H3 boards; not all the H3 updates were correct, it seems like the OMAP1 boards are not getting proper build testing. Also, commit e27a93a944a5ba6a0112750c8243abba86d56e94 introduced a regression related to the tps65013 chip. Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-h3.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 6fc516855a8..c3ef1ee5f77 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -51,6 +52,8 @@ #include #include +#define H3_TS_GPIO 48 + static int h3_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_RIGHT), @@ -373,6 +376,17 @@ static struct platform_device h3_lcd_device = { .id = -1, }; +static struct spi_board_info h3_spi_board_info[] __initdata = { + [0] = { + .modalias = "tsc2101", + .bus_num = 2, + .chip_select = 0, + .irq = OMAP_GPIO_IRQ(H3_TS_GPIO), + .max_speed_hz = 16000000, + /* .platform_data = &tsc_platform_data, */ + }, +}; + static struct omap_mcbsp_reg_cfg mcbsp_regs = { .spcr2 = FREE | FRST | GRST | XRST | XINTM(3), .spcr1 = RINTM(3) | RRST, @@ -457,6 +471,14 @@ static struct omap_board_config_kernel h3_config[] __initdata = { { OMAP_TAG_LCD, &h3_lcd_config }, }; +static struct i2c_board_info __initdata h3_i2c_board_info[] = { + { + I2C_BOARD_INFO("tps65010", 0x48), + .type = "tps65013", + /* .irq = OMAP_GPIO_IRQ(??), */ + }, +}; + static struct omap_gpio_switch h3_gpio_switches[] __initdata = { { .name = "mmc_slot", -- cgit From 9221bb1c3a0d5e14df2cca43e22f983676795652 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 28 Feb 2008 14:40:53 -0800 Subject: ARM: OMAP1: omap h2 regression fix H2 and H3 were broken on by e27a93a944a5ba6a0112750c8243abba86d56e94, which removed declarations for their tps6501x chips. This resolves that issue for the H2. (Note that this patch *also* broke the isp1301 support on H2; it presumed a not-yet-merged new-style I2c driver.) Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-h2.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 070345ee39a..50798772001 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -350,6 +350,10 @@ static void __init h2_init_smc91x(void) static struct i2c_board_info __initdata h2_i2c_board_info[] = { { + I2C_BOARD_INFO("tps65010", 0x48), + .type = "tps65010", + .irq = OMAP_GPIO_IRQ(58), + }, { I2C_BOARD_INFO("isp1301_omap", 0x2d), .type = "isp1301_omap", .irq = OMAP_GPIO_IRQ(2), -- cgit From 02bad5f9bc9f1f42d4bb87bb8bf741d4cefe87d6 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Sun, 24 Feb 2008 19:08:26 -0800 Subject: ARM: OMAP1: omap1/pm.c build fix Build fix: arch/arm/mach-omap1/pm.c: In function 'omap_pm_init': arch/arm/mach-omap1/pm.c:720: warning: passing argument 2 of 'sysfs_create_file' from incompatible pointer type Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 8eb5dcdaead..e6c64e10b7e 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -717,7 +717,7 @@ static int __init omap_pm_init(void) #endif #ifdef CONFIG_OMAP_32K_TIMER - error = sysfs_create_file(power_kobj, &sleep_while_idle_attr); + error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr); if (error) printk(KERN_ERR "sysfs_create_file failed: %d\n", error); #endif -- cgit From a6472533e4553985af775982744b0ba088b5ff8c Mon Sep 17 00:00:00 2001 From: David Brownell Date: Mon, 3 Mar 2008 04:33:30 -0800 Subject: ARM: OMAP: gpio lockdep updates Fix some spinlock issues reported by lockdep: since the gpio bank locks can be aquired in both irq and non-irq contexts, they need to be consistent about always using the irq-safe variants. Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 59 ++++++++++++++++++++++++++++------------------- 1 file changed, 35 insertions(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 9030495509f..66a1455595f 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -333,13 +333,14 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) void omap_set_gpio_direction(int gpio, int is_input) { struct gpio_bank *bank; + unsigned long flags; if (check_gpio(gpio) < 0) return; bank = get_gpio_bank(gpio); - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); _set_gpio_direction(bank, get_gpio_index(gpio), is_input); - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); } static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) @@ -406,13 +407,14 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) void omap_set_gpio_dataout(int gpio, int enable) { struct gpio_bank *bank; + unsigned long flags; if (check_gpio(gpio) < 0) return; bank = get_gpio_bank(gpio); - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); _set_gpio_dataout(bank, get_gpio_index(gpio), enable); - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); } int omap_get_gpio_datain(int gpio) @@ -624,6 +626,7 @@ static int gpio_irq_type(unsigned irq, unsigned type) struct gpio_bank *bank; unsigned gpio; int retval; + unsigned long flags; if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); @@ -642,13 +645,13 @@ static int gpio_irq_type(unsigned irq, unsigned type) return -EINVAL; bank = get_irq_chip_data(irq); - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); if (retval == 0) { irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; irq_desc[irq].status |= type; } - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); return retval; } @@ -830,11 +833,13 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena */ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) { + unsigned long flags; + switch (bank->method) { #ifdef CONFIG_ARCH_OMAP16XX case METHOD_MPUIO: case METHOD_GPIO_1610: - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); if (enable) { bank->suspend_wakeup |= (1 << gpio); enable_irq_wake(bank->irq); @@ -842,7 +847,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) disable_irq_wake(bank->irq); bank->suspend_wakeup &= ~(1 << gpio); } - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) @@ -853,7 +858,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) (bank - gpio_bank) * 32 + gpio); return -EINVAL; } - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); if (enable) { bank->suspend_wakeup |= (1 << gpio); enable_irq_wake(bank->irq); @@ -861,7 +866,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) disable_irq_wake(bank->irq); bank->suspend_wakeup &= ~(1 << gpio); } - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif default: @@ -897,16 +902,17 @@ static int gpio_wake_enable(unsigned int irq, unsigned int enable) int omap_request_gpio(int gpio) { struct gpio_bank *bank; + unsigned long flags; if (check_gpio(gpio) < 0) return -EINVAL; bank = get_gpio_bank(gpio); - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) { printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio); dump_stack(); - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); return -1; } bank->reserved_map |= (1 << get_gpio_index(gpio)); @@ -925,7 +931,7 @@ int omap_request_gpio(int gpio) __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); } #endif - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); return 0; } @@ -933,15 +939,16 @@ int omap_request_gpio(int gpio) void omap_free_gpio(int gpio) { struct gpio_bank *bank; + unsigned long flags; if (check_gpio(gpio) < 0) return; bank = get_gpio_bank(gpio); - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); dump_stack(); - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); return; } #ifdef CONFIG_ARCH_OMAP16XX @@ -960,7 +967,7 @@ void omap_free_gpio(int gpio) #endif bank->reserved_map &= ~(1 << get_gpio_index(gpio)); _reset_gpio(bank, gpio); - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); } /* @@ -1194,11 +1201,12 @@ static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t me { struct gpio_bank *bank = platform_get_drvdata(pdev); void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; + unsigned long flags; - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); bank->saved_wakeup = __raw_readl(mask_reg); __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); return 0; } @@ -1207,10 +1215,11 @@ static int omap_mpuio_resume_early(struct platform_device *pdev) { struct gpio_bank *bank = platform_get_drvdata(pdev); void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; + unsigned long flags; - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); __raw_writel(bank->saved_wakeup, mask_reg); - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); return 0; } @@ -1495,6 +1504,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) void __iomem *wake_status; void __iomem *wake_clear; void __iomem *wake_set; + unsigned long flags; switch (bank->method) { #ifdef CONFIG_ARCH_OMAP16XX @@ -1515,11 +1525,11 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) continue; } - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); bank->saved_wakeup = __raw_readl(wake_status); __raw_writel(0xffffffff, wake_clear); __raw_writel(bank->suspend_wakeup, wake_set); - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); } return 0; @@ -1536,6 +1546,7 @@ static int omap_gpio_resume(struct sys_device *dev) struct gpio_bank *bank = &gpio_bank[i]; void __iomem *wake_clear; void __iomem *wake_set; + unsigned long flags; switch (bank->method) { #ifdef CONFIG_ARCH_OMAP16XX @@ -1554,10 +1565,10 @@ static int omap_gpio_resume(struct sys_device *dev) continue; } - spin_lock(&bank->lock); + spin_lock_irqsave(&bank->lock, flags); __raw_writel(0xffffffff, wake_clear); __raw_writel(bank->saved_wakeup, wake_set); - spin_unlock(&bank->lock); + spin_unlock_irqrestore(&bank->lock, flags); } return 0; -- cgit From d4423fd07919756342dffffac45ee068d0a7f5a5 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 6 Mar 2008 13:27:16 +0200 Subject: ARM: OMAP1: Refresh OSK defconfig Refresh OSK defconfig Signed-off-by: Tony Lindgren --- arch/arm/configs/omap_osk_5912_defconfig | 113 ++++++++++++++++++++++++------- 1 file changed, 89 insertions(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap_osk_5912_defconfig b/arch/arm/configs/omap_osk_5912_defconfig index d592a648711..600be0f0e95 100644 --- a/arch/arm/configs/omap_osk_5912_defconfig +++ b/arch/arm/configs/omap_osk_5912_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.24-rc5 -# Mon Dec 17 21:12:45 2007 +# Linux kernel version: 2.6.25-rc3 +# Mon Mar 3 03:35:17 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -21,6 +21,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_ZONE_DMA=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -39,17 +40,22 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y -CONFIG_FAIR_USER_SCHED=y -# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_CC_OPTIMIZE_FOR_SIZE=y @@ -63,17 +69,26 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 @@ -101,6 +116,8 @@ CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +# CONFIG_PREEMPT_RCU is not set # # System Type @@ -129,6 +146,7 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set @@ -138,6 +156,7 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y +# CONFIG_ARCH_MSM7X00A is not set # # TI OMAP Implementations @@ -154,6 +173,7 @@ CONFIG_OMAP_MUX=y # CONFIG_OMAP_MUX_DEBUG is not set CONFIG_OMAP_MUX_WARNINGS=y CONFIG_OMAP_MCBSP=y +# CONFIG_OMAP_MMU_FWK is not set # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 @@ -275,6 +295,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set +# CONFIG_ATAGS_PROC is not set # # CPU Frequency scaling @@ -307,9 +328,10 @@ CONFIG_PM=y # CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set CONFIG_PM_SLEEP=y -CONFIG_SUSPEND_UP_POSSIBLE=y CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y # CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y # # Networking @@ -326,6 +348,7 @@ CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y @@ -381,6 +404,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set @@ -493,11 +517,13 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=m CONFIG_BLK_DEV_IDE=m @@ -519,7 +545,6 @@ CONFIG_IDE_PROC_FS=y # # CONFIG_IDE_GENERIC is not set # CONFIG_BLK_DEV_PLATFORM is not set -# CONFIG_IDE_ARM is not set # CONFIG_BLK_DEV_IDEDMA is not set CONFIG_IDE_ARCH_OBSOLETE_INIT=y # CONFIG_BLK_DEV_HD is not set @@ -553,6 +578,7 @@ CONFIG_SMC91X=y # CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_B44 is not set CONFIG_NETDEV_1000=y +# CONFIG_E1000E_ENABLED is not set CONFIG_NETDEV_10000=y # @@ -574,7 +600,6 @@ CONFIG_PPP_MULTILINK=y # CONFIG_PPPOL2TP is not set # CONFIG_SLIP is not set CONFIG_SLHC=y -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -671,6 +696,7 @@ CONFIG_HW_RANDOM_OMAP=m # CONFIG_SYNCLINK_CS is not set # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_I2C=y @@ -698,12 +724,10 @@ CONFIG_I2C_OMAP=y # # Miscellaneous I2C Chip support # -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_DS1682 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_ISP1301_OMAP is not set CONFIG_TPS65010=y @@ -731,6 +755,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -758,6 +783,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set @@ -765,6 +791,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set @@ -780,6 +807,7 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # # CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set # # Multimedia devices @@ -865,10 +893,6 @@ CONFIG_USB_ARCH_HAS_OHCI=y # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # - -# -# USB Gadget Support -# # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set # CONFIG_NEW_LEDS is not set @@ -889,12 +913,10 @@ CONFIG_EXT2_FS=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y # CONFIG_FUSE_FS is not set @@ -948,8 +970,10 @@ CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y @@ -1019,9 +1043,6 @@ CONFIG_NLS_ISO8859_1=m # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set -CONFIG_INSTRUMENTATION=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set # # Kernel hacking @@ -1045,7 +1066,51 @@ CONFIG_FRAME_POINTER=y # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y # # Library routines -- cgit From d68a8ce8343365f8560fa9f89300fb4cd2415459 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 6 Mar 2008 13:27:16 +0200 Subject: ARM: OMAP1: Refresh H2 defconfig Refresh H2 defconfig Signed-off-by: Tony Lindgren --- arch/arm/configs/omap_h2_1610_defconfig | 71 +++++++++++++++++++++++---------- 1 file changed, 49 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig index c2345af3707..323c1deeb95 100644 --- a/arch/arm/configs/omap_h2_1610_defconfig +++ b/arch/arm/configs/omap_h2_1610_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.24-rc5 -# Mon Dec 17 20:04:38 2007 +# Linux kernel version: 2.6.25-rc3 +# Mon Mar 3 03:39:48 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -21,6 +21,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_ZONE_DMA=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -40,17 +41,22 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y -CONFIG_FAIR_USER_SCHED=y -# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_CC_OPTIMIZE_FOR_SIZE=y @@ -64,17 +70,26 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 @@ -102,6 +117,8 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y +# CONFIG_PREEMPT_RCU is not set # # System Type @@ -130,6 +147,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set @@ -139,6 +157,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y +# CONFIG_ARCH_MSM7X00A is not set # # TI OMAP Implementations @@ -155,6 +174,7 @@ CONFIG_OMAP_MUX=y # CONFIG_OMAP_MUX_DEBUG is not set CONFIG_OMAP_MUX_WARNINGS=y CONFIG_OMAP_MCBSP=y +# CONFIG_OMAP_MMU_FWK is not set # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 @@ -266,6 +286,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=0801 ro init=/bin/sh" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set +# CONFIG_ATAGS_PROC is not set # # CPU Frequency scaling @@ -311,9 +332,10 @@ CONFIG_PM=y # CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set CONFIG_PM_SLEEP=y -CONFIG_SUSPEND_UP_POSSIBLE=y CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y # CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y # # Networking @@ -330,6 +352,7 @@ CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -384,6 +407,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set @@ -421,11 +445,13 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HAVE_IDE is not set # # SCSI device support @@ -489,6 +515,7 @@ CONFIG_SMC91X=y # CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_B44 is not set CONFIG_NETDEV_1000=y +# CONFIG_E1000E_ENABLED is not set CONFIG_NETDEV_10000=y # @@ -512,7 +539,6 @@ CONFIG_SLIP_COMPRESSED=y CONFIG_SLHC=y # CONFIG_SLIP_SMART is not set # CONFIG_SLIP_MODE_SLIP6 is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -616,12 +642,10 @@ CONFIG_I2C_OMAP=y # # Miscellaneous I2C Chip support # -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_DS1682 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_ISP1301_OMAP is not set CONFIG_TPS65010=y @@ -649,6 +673,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -676,6 +701,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set @@ -683,6 +709,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set @@ -705,6 +732,7 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # # CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set # # Multimedia devices @@ -802,10 +830,6 @@ CONFIG_USB_ARCH_HAS_OHCI=y # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # - -# -# USB Gadget Support -# # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set # CONFIG_NEW_LEDS is not set @@ -826,12 +850,10 @@ CONFIG_EXT2_FS=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -CONFIG_ROMFS_FS=y +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -874,8 +896,10 @@ CONFIG_SYSFS=y # CONFIG_EFS_FS is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y @@ -946,9 +970,6 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set -CONFIG_INSTRUMENTATION=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set # # Kernel hacking @@ -975,6 +996,7 @@ CONFIG_FRAME_POINTER=y CONFIG_CRYPTO=y CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_BLKCIPHER=y +# CONFIG_CRYPTO_SEQIV is not set CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set @@ -992,6 +1014,9 @@ CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_PCBC=m # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CCM is not set # CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set @@ -1006,12 +1031,14 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_TEST is not set # CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_LZO is not set CONFIG_CRYPTO_HW=y # -- cgit From 19dc8a5b06aba0db11a600c10db5bc99839f098a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 6 Mar 2008 13:28:06 +0200 Subject: ARM: OMAP1: Compile in other 16xx boards to OSK defconfig This allows monitoring compile issues with Kautobuild for other omap1 boards until we have more board specific defconfig files. After 2.6.25, we can add a generic config_omap_generic16xx to compile in support for all 16xx boards and then remove other boards from OSK defconfig. Signed-off-by: Tony Lindgren --- arch/arm/configs/omap_osk_5912_defconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap_osk_5912_defconfig b/arch/arm/configs/omap_osk_5912_defconfig index 600be0f0e95..d4ca5e6e4ff 100644 --- a/arch/arm/configs/omap_osk_5912_defconfig +++ b/arch/arm/configs/omap_osk_5912_defconfig @@ -193,13 +193,13 @@ CONFIG_ARCH_OMAP16XX=y # # OMAP Board Type # -# CONFIG_MACH_OMAP_INNOVATOR is not set -# CONFIG_MACH_OMAP_H2 is not set -# CONFIG_MACH_OMAP_H3 is not set +CONFIG_MACH_OMAP_INNOVATOR=y +CONFIG_MACH_OMAP_H2=y +CONFIG_MACH_OMAP_H3=y CONFIG_MACH_OMAP_OSK=y # CONFIG_OMAP_OSK_MISTRAL is not set -# CONFIG_MACH_NOKIA770 is not set -# CONFIG_MACH_OMAP_GENERIC is not set +CONFIG_MACH_NOKIA770=y +CONFIG_MACH_OMAP_GENERIC=y # # OMAP CPU Speed -- cgit From 09f21ed4c1bd158a92114074c268e4a835690ca5 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Wed, 20 Feb 2008 15:30:06 -0800 Subject: ARM: OMAP2: Register the L4 io bus to boot OMAP2 This patch enables OMAP2 to boot. Signed-off-by: Kyungmin Park Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 5a4091f582e..69c8174f3aa 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -42,6 +42,12 @@ static struct map_desc omap2_io_desc[] __initdata = { .length = L3_24XX_SIZE, .type = MT_DEVICE }, + { + .virtual = L4_24XX_VIRT, + .pfn = __phys_to_pfn(L4_24XX_PHYS), + .length = L4_24XX_SIZE, + .type = MT_DEVICE + }, #ifdef CONFIG_ARCH_OMAP2430 { .virtual = L4_WK_243X_VIRT, -- cgit From be73a347ec7799aec0aa1008bd991f93dbfa80e8 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 29 Feb 2008 21:12:57 +0100 Subject: [ARM] 4845/1: Orion: Ignore memory tags with invalid data The DNS-323, Kurobox-Pro / Linkstation-Pro, QNAP TS-109/TS-209 and some other orion-based systems have several bogus memory entries in the tag table, which causes the system to crash at startup. Ignore them by resetting the tag ID to 0 in a machine fixup function. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Russell King --- arch/arm/mach-orion/common.c | 20 ++++++++++++++++++++ arch/arm/mach-orion/common.h | 6 ++++++ arch/arm/mach-orion/dns323-setup.c | 1 + arch/arm/mach-orion/kurobox_pro-setup.c | 1 + arch/arm/mach-orion/ts209-setup.c | 1 + 5 files changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index 5f0ee4b8a9b..2d6d413f023 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #include #include #include "common.h" @@ -347,3 +349,21 @@ void __init orion_init(void) platform_device_register(&orion_ehci1); platform_device_register(&orion_i2c); } + +/* + * Many orion-based systems have buggy bootloader implementations. + * This is a common fixup for bogus memory tags. + */ +void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t, + char **from, struct meminfo *meminfo) +{ + for (; t->hdr.size; t = tag_next(t)) + if (t->hdr.tag == ATAG_MEM && + (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || + t->u.mem.start & ~PAGE_MASK)) { + printk(KERN_WARNING + "Clearing invalid memory bank %dKB@0x%08x\n", + t->u.mem.size / 1024, t->u.mem.start); + t->hdr.tag = 0; + } +} diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 10154ec885d..501497cc2c4 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -83,4 +83,10 @@ struct mv_sata_platform_data; void __init orion_sata_init(struct mv_sata_platform_data *sata_data); +struct machine_desc; +struct meminfo; +struct tag; +extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, + char **, struct meminfo *); + #endif /* __ARCH_ORION_COMMON_H__ */ diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c index 02b280c2482..076e155ad51 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion/dns323-setup.c @@ -319,4 +319,5 @@ MACHINE_START(DNS323, "D-Link DNS-323") .map_io = orion_map_io, .init_irq = orion_init_irq, .timer = &orion_timer, + .fixup = tag_fixup_mem32, MACHINE_END diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c index 6817aca4aa2..785a07bdf1e 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion/kurobox_pro-setup.c @@ -240,4 +240,5 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") .map_io = orion_map_io, .init_irq = orion_init_irq, .timer = &orion_timer, + .fixup = tag_fixup_mem32, MACHINE_END diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c index b8cfe6813e9..45764dad16d 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion/ts209-setup.c @@ -357,4 +357,5 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209") .map_io = orion_map_io, .init_irq = orion_init_irq, .timer = &orion_timer, + .fixup = tag_fixup_mem32, MACHINE_END -- cgit From b24061fadc2b996fd38baaf01986eac666d0c61b Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 4 Mar 2008 21:56:21 +0100 Subject: [ARM] 4847/1: kprobes: fix compilation with CONFIG_DEBUG_FS=y Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/kernel/kprobes.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c index a22a98c43ca..13e371aad87 100644 --- a/arch/arm/kernel/kprobes.c +++ b/arch/arm/kernel/kprobes.c @@ -431,6 +431,11 @@ int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs) return 0; } +int __kprobes arch_trampoline_kprobe(struct kprobe *p) +{ + return 0; +} + static struct undef_hook kprobes_break_hook = { .instr_mask = 0xffffffff, .instr_val = KPROBE_BREAKPOINT_INSTRUCTION, -- cgit From 37aca70c626ce8f4e5848de2d4892b5ed74a6875 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Wed, 5 Mar 2008 00:08:29 +0100 Subject: [ARM] 4848/1: at91: remove false lockdep warnings Remove false lockdep warnings about lock recursion when declaring IRQs as being wake-capable, by marking putting GPIO irq_desc locks into their own class. (Thanks to Peter Zijlstra for helping track down such a small fix to this problem.) Signed-off-by: David Brownell Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/gpio.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index f629c2b5f0c..ee4964abcaf 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -490,6 +490,11 @@ postcore_initcall(at91_gpio_debugfs_init); /*--------------------------------------------------------------------------*/ +/* This lock class tells lockdep that GPIO irqs are in a different + * category than their parents, so it won't report false recursion. + */ +static struct lock_class_key gpio_lock_class; + /* * Called from the processor-specific init to enable GPIO interrupt support. */ @@ -510,6 +515,8 @@ void __init at91_gpio_irq_setup(void) __raw_writel(~0, this->regbase + PIO_IDR); for (i = 0, pin = this->chipbase; i < 32; i++, pin++) { + lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); + /* * Can use the "simple" and not "edge" handler since it's * shorter, and the AIC handles interrupts sanely. -- cgit From 9c4c9f38796faf750de8586becf43b769c76b674 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 5 Mar 2008 06:50:07 +0100 Subject: [ARM] 4849/1: move ATAGS asm definitions Move the definitions of ATAG_CORE and ATAG_CORE_SIZE in head.S to head-common.S. There is no use of these in head.S itself, but they are used in head-common.S. When building for the !CONFIG_MMU case these were not defined when compiling head-nommu.S (which includes head-common.S). Signed-off-by: Greg Ungerer Signed-off-by: Russell King --- arch/arm/kernel/head-common.S | 3 +++ arch/arm/kernel/head.S | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 024a9cf469b..50f667febe2 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -11,6 +11,9 @@ * */ +#define ATAG_CORE 0x54410001 +#define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2) + .type __switch_data, %object __switch_data: .long __mmap_switched diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 7898cbc9861..bff4c6e90dd 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -29,9 +29,6 @@ #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) #define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET) -#define ATAG_CORE 0x54410001 -#define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2) - /* * swapper_pg_dir is the virtual address of the initial page table. -- cgit From 8e86f4271aaac7685923b80cf57972be41afbc1d Mon Sep 17 00:00:00 2001 From: Harvey Harrison Date: Tue, 4 Mar 2008 15:08:02 -0800 Subject: [ARM] replace remaining __FUNCTION__ occurrences __FUNCTION__ is gcc-specific, use __func__ Signed-off-by: Harvey Harrison Signed-off-by: Andrew Morton Signed-off-by: Russell King --- arch/arm/common/it8152.c | 6 ++-- arch/arm/mach-h720x/common.c | 12 +++---- arch/arm/mach-imx/dma.c | 12 +++---- arch/arm/mach-imx/irq.c | 6 ++-- arch/arm/mach-iop13xx/iq81340mc.c | 2 +- arch/arm/mach-iop13xx/iq81340sc.c | 2 +- arch/arm/mach-iop13xx/pci.c | 8 ++--- arch/arm/mach-iop13xx/setup.c | 2 +- arch/arm/mach-ixp4xx/common-pci.c | 2 +- arch/arm/mach-ixp4xx/gtwx5715-pci.c | 2 +- arch/arm/mach-netx/generic.c | 6 ++-- arch/arm/mach-orion/gpio.c | 12 +++---- arch/arm/mach-pnx4008/clock.c | 2 +- arch/arm/mach-pnx4008/dma.c | 2 +- arch/arm/mach-pxa/cm-x270-pci.c | 2 +- arch/arm/mach-pxa/cm-x270.c | 4 +-- arch/arm/mach-pxa/dma.c | 2 +- arch/arm/mach-pxa/em-x270.c | 2 +- arch/arm/mach-pxa/mainstone.c | 4 +-- arch/arm/mach-pxa/trizeps4.c | 8 ++--- arch/arm/mach-sa1100/badge4.c | 6 ++-- arch/arm/mach-sa1100/cpu-sa1100.c | 2 +- arch/arm/mach-sa1100/dma.c | 8 ++--- arch/arm/mach-sa1100/h3600.c | 14 ++++---- arch/arm/plat-iop/pci.c | 2 +- arch/arm/plat-omap/dma.c | 4 +-- arch/arm/plat-omap/dmtimer.c | 2 +- arch/arm/plat-s3c24xx/dma.c | 64 ++++++++++++++++++------------------- 28 files changed, 100 insertions(+), 100 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index 97b7dc13d9a..53826224148 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -274,7 +274,7 @@ static int it8152_pci_platform_notify_remove(struct device *dev) int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) { dev_dbg(dev, "%s: dma_addr %08x, size %08x\n", - __FUNCTION__, dma_addr, size); + __func__, dma_addr, size); return (dev->bus == &pci_bus_type) && ((dma_addr + size - PHYS_OFFSET) >= SZ_64M); } @@ -289,7 +289,7 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) */ int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { - dev_dbg(&dev->dev, "%s: %llx\n", __FUNCTION__, mask); + dev_dbg(&dev->dev, "%s: %llx\n", __func__, mask); if (mask >= PHYS_OFFSET + SZ_64M - 1) return 0; @@ -299,7 +299,7 @@ int pci_set_dma_mask(struct pci_dev *dev, u64 mask) int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) { - dev_dbg(&dev->dev, "%s: %llx\n", __FUNCTION__, mask); + dev_dbg(&dev->dev, "%s: %llx\n", __func__, mask); if (mask >= PHYS_OFFSET + SZ_64M - 1) return 0; diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index 7f31816896a..45144ad2bed 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c @@ -103,7 +103,7 @@ static void h720x_gpio_handler(unsigned int mask, unsigned int irq, struct irq_desc *desc) { - IRQDBG("%s irq: %d\n",__FUNCTION__,irq); + IRQDBG("%s irq: %d\n", __func__, irq); desc = irq_desc + irq; while (mask) { if (mask & 1) { @@ -123,7 +123,7 @@ h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc) mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT); irq = IRQ_CHAINED_GPIOA(0); - IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); + IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); h720x_gpio_handler(mask, irq, desc); } @@ -133,7 +133,7 @@ h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc) unsigned int mask, irq; mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); irq = IRQ_CHAINED_GPIOB(0); - IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); + IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); h720x_gpio_handler(mask, irq, desc); } @@ -144,7 +144,7 @@ h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc) mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT); irq = IRQ_CHAINED_GPIOC(0); - IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); + IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); h720x_gpio_handler(mask, irq, desc); } @@ -155,7 +155,7 @@ h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc) mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT); irq = IRQ_CHAINED_GPIOD(0); - IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); + IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); h720x_gpio_handler(mask, irq, desc); } @@ -167,7 +167,7 @@ h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc) mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT); irq = IRQ_CHAINED_GPIOE(0); - IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); + IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); h720x_gpio_handler(mask, irq, desc); } #endif diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c index bc6fb02d213..a59ff2987cb 100644 --- a/arch/arm/mach-imx/dma.c +++ b/arch/arm/mach-imx/dma.c @@ -54,7 +54,7 @@ static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount) if (!imxdma->name) { printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __FUNCTION__, dma_ch); + __func__, dma_ch); return 0; } @@ -288,7 +288,7 @@ imx_dma_setup_handlers(imx_dmach_t dma_ch, if (!imxdma->name) { printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __FUNCTION__, dma_ch); + __func__, dma_ch); return -ENODEV; } @@ -321,7 +321,7 @@ void imx_dma_enable(imx_dmach_t dma_ch) if (!imxdma->name) { printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __FUNCTION__, dma_ch); + __func__, dma_ch); return; } @@ -365,7 +365,7 @@ int imx_dma_request(imx_dmach_t dma_ch, const char *name) if (dma_ch >= IMX_DMA_CHANNELS) { printk(KERN_CRIT "%s: called for non-existed channel %d\n", - __FUNCTION__, dma_ch); + __func__, dma_ch); return -EINVAL; } @@ -396,7 +396,7 @@ void imx_dma_free(imx_dmach_t dma_ch) if (!imxdma->name) { printk(KERN_CRIT "%s: trying to free channel %d which is already freed\n", - __FUNCTION__, dma_ch); + __func__, dma_ch); return; } @@ -456,7 +456,7 @@ imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name, } } - printk(KERN_ERR "%s: no free DMA channel found\n", __FUNCTION__); + printk(KERN_ERR "%s: no free DMA channel found\n", __func__); return -ENODEV; } diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c index a7465db8489..e6695c4e623 100644 --- a/arch/arm/mach-imx/irq.c +++ b/arch/arm/mach-imx/irq.c @@ -160,21 +160,21 @@ imx_gpio_irq_type(unsigned int _irq, unsigned int type) static void imx_gpio_ack_irq(unsigned int irq) { - DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq); + DEBUG_IRQ("%s: irq %d\n", __func__, irq); ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32); } static void imx_gpio_mask_irq(unsigned int irq) { - DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq); + DEBUG_IRQ("%s: irq %d\n", __func__, irq); IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32)); } static void imx_gpio_unmask_irq(unsigned int irq) { - DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq); + DEBUG_IRQ("%s: irq %d\n", __func__, irq); IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32); } diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index 268a8d84999..77b24cd1d88 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -81,7 +81,7 @@ static void __init iq81340mc_init(void) static void __init iq81340mc_timer_init(void) { unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); - printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq); + printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq); iop_init_time(bus_freq); } diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index a51ffd2683e..e8522b3b816 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -83,7 +83,7 @@ static void __init iq81340sc_init(void) static void __init iq81340sc_timer_init(void) { unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); - printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq); + printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq); iop_init_time(bus_freq); } diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 99d94cb1baf..7825c1aaa27 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -94,13 +94,13 @@ void iop13xx_map_pci_memory(void) , 0, iop13xx_atux_mem_size, MT_DEVICE); if (!iop13xx_atux_mem_base) { printk("%s: atux allocation " - "failed\n", __FUNCTION__); + "failed\n", __func__); BUG(); } } else iop13xx_atux_mem_size = 0; PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", - __FUNCTION__, atu, iop13xx_atux_mem_size, + __func__, atu, iop13xx_atux_mem_size, iop13xx_atux_mem_base); break; case 1: @@ -120,13 +120,13 @@ void iop13xx_map_pci_memory(void) , 0, iop13xx_atue_mem_size, MT_DEVICE); if (!iop13xx_atue_mem_base) { printk("%s: atue allocation " - "failed\n", __FUNCTION__); + "failed\n", __func__); BUG(); } } else iop13xx_atue_mem_size = 0; PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", - __FUNCTION__, atu, iop13xx_atue_mem_size, + __func__, atu, iop13xx_atue_mem_size, iop13xx_atue_mem_base); break; } diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index bfe0c87e339..246f6d47872 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c @@ -519,7 +519,7 @@ void __init iop13xx_platform_init(void) if (iq8134x_flash_resource.end > iq8134x_flash_resource.start) iop13xx_devices[plat_idx++] = &iq8134x_flash; else - printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__); + printk(KERN_ERR "%s: Failed to probe flash size\n", __func__); #endif platform_add_devices(iop13xx_devices, plat_idx); diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index bf04121d1a3..64be341109b 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -87,7 +87,7 @@ static inline int check_master_abort(void) if (isr & PCI_ISR_PFE) { /* make sure the Master Abort bit is reset */ *PCI_ISR = PCI_ISR_PFE; - pr_debug("%s failed\n", __FUNCTION__); + pr_debug("%s failed\n", __func__); return 1; } diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 0d5a4245582..49dec786880 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -65,7 +65,7 @@ static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin) else rc = gtwx5715_irqmap[slot][pin-1]; - printk("%s: Mapped slot %d pin %d to IRQ %d\n", __FUNCTION__,slot, pin, rc); + printk("%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc); return(rc); } diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index b9ca8f98265..fd7537f7d11 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -133,7 +133,7 @@ netx_hif_ack_irq(unsigned int _irq) val &= ~((1 << 24) << irq); writel(val, NETX_DPMAS_INT_EN); - DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq); + DEBUG_IRQ("%s: irq %d\n", __func__, _irq); } static void @@ -145,7 +145,7 @@ netx_hif_mask_irq(unsigned int _irq) val = readl(NETX_DPMAS_INT_EN); val &= ~((1 << 24) << irq); writel(val, NETX_DPMAS_INT_EN); - DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq); + DEBUG_IRQ("%s: irq %d\n", __func__, _irq); } static void @@ -157,7 +157,7 @@ netx_hif_unmask_irq(unsigned int _irq) val = readl(NETX_DPMAS_INT_EN); val |= (1 << 24) << irq; writel(val, NETX_DPMAS_INT_EN); - DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq); + DEBUG_IRQ("%s: irq %d\n", __func__, _irq); } static struct irq_chip netx_hif_chip = { diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c index d5f00c86d61..f713818c66a 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion/gpio.c @@ -36,7 +36,7 @@ int gpio_direction_input(unsigned pin) unsigned long flags; if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin); + pr_debug("%s: invalid GPIO %d\n", __func__, pin); return -EINVAL; } @@ -62,7 +62,7 @@ int gpio_direction_output(unsigned pin, int value) int mask; if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin); + pr_debug("%s: invalid GPIO %d\n", __func__, pin); return -EINVAL; } @@ -141,7 +141,7 @@ int gpio_request(unsigned pin, const char *label) unsigned long flags; if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin); + pr_debug("%s: invalid GPIO %d\n", __func__, pin); return -EINVAL; } @@ -149,7 +149,7 @@ int gpio_request(unsigned pin, const char *label) if (gpio_label[pin]) { pr_debug("%s: GPIO %d already used as %s\n", - __FUNCTION__, pin, gpio_label[pin]); + __func__, pin, gpio_label[pin]); ret = -EBUSY; } else gpio_label[pin] = label ? label : "?"; @@ -162,12 +162,12 @@ EXPORT_SYMBOL(gpio_request); void gpio_free(unsigned pin) { if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin); + pr_debug("%s: invalid GPIO %d\n", __func__, pin); return; } if (!gpio_label[pin]) - pr_warning("%s: GPIO %d already freed\n", __FUNCTION__, pin); + pr_warning("%s: GPIO %d already freed\n", __func__, pin); else gpio_label[pin] = NULL; } diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c index daa8d3d98ef..8e00ed43fb9 100644 --- a/arch/arm/mach-pnx4008/clock.c +++ b/arch/arm/mach-pnx4008/clock.c @@ -976,7 +976,7 @@ static int __init clk_init(void) (*clkp)->set_parent((*clkp), (*clkp)->parent); } pr_debug("%s: clock %s, rate %ld\n", - __FUNCTION__, (*clkp)->name, (*clkp)->rate); + __func__, (*clkp)->name, (*clkp)->rate); } local_clk_use(&ck_pll4); diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c index f7009d845be..fe152e82590 100644 --- a/arch/arm/mach-pnx4008/dma.c +++ b/arch/arm/mach-pnx4008/dma.c @@ -192,7 +192,7 @@ void pnx4008_free_channel(int ch) if (!dma_channels[ch].name) { printk(KERN_CRIT "%s: trying to free channel %d which is already freed\n", - __FUNCTION__, ch); + __func__, ch); return; } diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c index 15c4e0df3e1..fcda7d5cb69 100644 --- a/arch/arm/mach-pxa/cm-x270-pci.c +++ b/arch/arm/mach-pxa/cm-x270-pci.c @@ -104,7 +104,7 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; - dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __FUNCTION__, slot, pin); + dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __func__, slot, pin); irq = it8152_pci_map_irq(dev, slot, pin); if (irq) diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index 6012177a29a..ecdbc96a4de 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -504,11 +504,11 @@ static void cmx270_mci_setpower(struct device *dev, unsigned int vdd) struct pxamci_platform_data *p_d = dev->platform_data; if ((1 << vdd) & p_d->ocr_mask) { - printk(KERN_DEBUG "%s: on\n", __FUNCTION__); + printk(KERN_DEBUG "%s: on\n", __func__); GPCR(105) = GPIO_bit(105); } else { GPSR(105) = GPIO_bit(105); - printk(KERN_DEBUG "%s: off\n", __FUNCTION__); + printk(KERN_DEBUG "%s: off\n", __func__); } } diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c index 93c4f31f127..3215316d7b0 100644 --- a/arch/arm/mach-pxa/dma.c +++ b/arch/arm/mach-pxa/dma.c @@ -81,7 +81,7 @@ void pxa_free_dma (int dma_ch) if (!dma_channels[dma_ch].name) { printk (KERN_CRIT "%s: trying to free channel %d which is already freed\n", - __FUNCTION__, dma_ch); + __func__, dma_ch); return; } diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 3d0ad5065ee..3bb31314429 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -264,7 +264,7 @@ static int em_x270_mci_init(struct device *dev, "MMC card detect", data); if (err) { printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n", - __FUNCTION__, err); + __func__, err); return err; } diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 345c3deeb02..72a436fb9a2 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -390,11 +390,11 @@ static void mainstone_mci_setpower(struct device *dev, unsigned int vdd) struct pxamci_platform_data* p_d = dev->platform_data; if (( 1 << vdd) & p_d->ocr_mask) { - printk(KERN_DEBUG "%s: on\n", __FUNCTION__); + printk(KERN_DEBUG "%s: on\n", __func__); MST_MSCWR1 |= MST_MSCWR1_MMC_ON; MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL; } else { - printk(KERN_DEBUG "%s: off\n", __FUNCTION__); + printk(KERN_DEBUG "%s: off\n", __func__); MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON; } } diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 853fc943375..f207fcd30cd 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -217,7 +217,7 @@ void board_pcmcia_power(int power) ConXS_BCR = trizeps_conxs_bcr; } - pr_debug("%s: o%s 0x%x\n", __FUNCTION__, power ? "n": "ff", trizeps_conxs_bcr); + pr_debug("%s: o%s 0x%x\n", __func__, power ? "n": "ff", trizeps_conxs_bcr); } /* backlight power switching for LCD panel */ @@ -228,7 +228,7 @@ static void board_backlight_power(int on) } else { trizeps_conxs_bcr &= ~ConXS_BCR_L_DISP; } - pr_debug("%s: o%s 0x%x\n", __FUNCTION__, on ? "n" : "ff", trizeps_conxs_bcr); + pr_debug("%s: o%s 0x%x\n", __func__, on ? "n" : "ff", trizeps_conxs_bcr); ConXS_BCR = trizeps_conxs_bcr; } @@ -238,10 +238,10 @@ static void board_mci_power(struct device *dev, unsigned int vdd) struct pxamci_platform_data* p_d = dev->platform_data; if (( 1 << vdd) & p_d->ocr_mask) { - pr_debug("%s: on\n", __FUNCTION__); + pr_debug("%s: on\n", __func__); /* FIXME fill in values here */ } else { - pr_debug("%s: off\n", __FUNCTION__); + pr_debug("%s: off\n", __func__); /* FIXME fill in values here */ } } diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c index f60b7a66dfa..842d9e6dc5f 100644 --- a/arch/arm/mach-sa1100/badge4.c +++ b/arch/arm/mach-sa1100/badge4.c @@ -206,7 +206,7 @@ static int __init badge4_init(void) if (ret < 0) printk(KERN_ERR "%s: SA-1111 initialization failed (%d)\n", - __FUNCTION__, ret); + __func__, ret); /* maybe turn on 5v0 from the start */ @@ -240,11 +240,11 @@ void badge4_set_5V(unsigned subsystem, int on) /* detect on->off and off->on transitions */ if ((!old_5V_bitmap) && (badge4_5V_bitmap)) { /* was off, now on */ - printk(KERN_INFO "%s: enabling 5V supply rail\n", __FUNCTION__); + printk(KERN_INFO "%s: enabling 5V supply rail\n", __func__); GPSR = BADGE4_GPIO_PCMEN5V; } else if ((old_5V_bitmap) && (!badge4_5V_bitmap)) { /* was on, now off */ - printk(KERN_INFO "%s: disabling 5V supply rail\n", __FUNCTION__); + printk(KERN_INFO "%s: disabling 5V supply rail\n", __func__); GPCR = BADGE4_GPIO_PCMEN5V; } diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index d68630b74d7..343368aa82d 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c @@ -139,7 +139,7 @@ static void sa1100_update_dram_timings(int current_speed, int new_speed) if (settings->speed == 0) { panic("%s: couldn't find dram setting for speed %d\n", - __FUNCTION__, new_speed); + __func__, new_speed); } /* No risk, no fun: run with interrupts on! */ diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c index 1fbe053e8b5..e5080286060 100644 --- a/arch/arm/mach-sa1100/dma.c +++ b/arch/arm/mach-sa1100/dma.c @@ -129,7 +129,7 @@ int sa1100_request_dma (dma_device_t device, const char *device_id, if (err) { printk(KERN_ERR "%s: unable to request IRQ %d for %s\n", - __FUNCTION__, IRQ_DMA0 + i, device_id); + __func__, IRQ_DMA0 + i, device_id); dma->device = 0; return err; } @@ -165,12 +165,12 @@ void sa1100_free_dma(dma_regs_t *regs) if (regs == (dma_regs_t *)&DDAR(i)) break; if (i >= SA1100_DMA_CHANNELS) { - printk(KERN_ERR "%s: bad DMA identifier\n", __FUNCTION__); + printk(KERN_ERR "%s: bad DMA identifier\n", __func__); return; } if (!dma_chan[i].device) { - printk(KERN_ERR "%s: Trying to free free DMA\n", __FUNCTION__); + printk(KERN_ERR "%s: Trying to free free DMA\n", __func__); return; } @@ -329,7 +329,7 @@ void sa1100_reset_dma(dma_regs_t *regs) if (regs == (dma_regs_t *)&DDAR(i)) break; if (i >= SA1100_DMA_CHANNELS) { - printk(KERN_ERR "%s: bad DMA identifier\n", __FUNCTION__); + printk(KERN_ERR "%s: bad DMA identifier\n", __func__); return; } diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c index b72fee0f253..8473c37b77d 100644 --- a/arch/arm/mach-sa1100/h3600.c +++ b/arch/arm/mach-sa1100/h3600.c @@ -596,7 +596,7 @@ static void h3800_control_egpio(enum ipaq_egpio_type x, int setp) case IPAQ_EGPIO_CODEC_NRESET: case IPAQ_EGPIO_AUDIO_ON: case IPAQ_EGPIO_QMUTE: - printk("%s: error - should not be called\n", __FUNCTION__); + printk("%s: error - should not be called\n", __func__); break; case IPAQ_EGPIO_OPT_NVRAM_ON: SET_ASIC2(GPIO2_OPT_ON_NVRAM); @@ -638,7 +638,7 @@ static int h3800_pm_callback(int req) static u16 asic2_data; int result = 0; - printk("%s %d\n", __FUNCTION__, req); + printk("%s %d\n", __func__, req); switch (req) { case PM_RESUME: @@ -666,7 +666,7 @@ static int h3800_pm_callback(int req) asic2_data = H3800_ASIC2_GPIOPIOD; break; default: - printk("%s: unrecognized PM callback\n", __FUNCTION__); + printk("%s: unrecognized PM callback\n", __func__); break; } return result; @@ -706,7 +706,7 @@ static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc) { int i; - if (0) printk("%s: interrupt received\n", __FUNCTION__); + if (0) printk("%s: interrupt received\n", __func__); desc->chip->ack(irq); @@ -716,21 +716,21 @@ static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc) /* KPIO */ irq = H3800_ASIC2_KPIINTFLAG; - if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq); + if (0) printk("%s KPIO 0x%08X\n", __func__, irq); for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++) if (irq & kpio_irq_mask[j]) handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j); /* GPIO2 */ irq = H3800_ASIC2_GPIINTFLAG; - if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq); + if (0) printk("%s GPIO 0x%08X\n", __func__, irq); for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++) if (irq & gpio_irq_mask[j]) handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j); } if (i >= MAX_ASIC_ISR_LOOPS) - printk("%s: interrupt processing overrun\n", __FUNCTION__); + printk("%s: interrupt processing overrun\n", __func__); /* For level-based interrupts */ desc->chip->unmask(irq); diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 2b5aa1135b1..98d01517b56 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -371,7 +371,7 @@ static int __init iop3xx_init_atu_setup(char *str) default: printk(KERN_DEBUG "\"%s\" malformed at " "character: \'%c\'", - __FUNCTION__, + __func__, *str); *(str + 1) = '\0'; } diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index a46676db811..9255a4598c7 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -137,7 +137,7 @@ static void omap_disable_channel_irq(int lch); static inline void omap_enable_channel_irq(int lch); #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ - __FUNCTION__); + __func__); #ifdef CONFIG_ARCH_OMAP15XX /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ @@ -699,7 +699,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) u32 reg; if (!cpu_class_is_omap2()) { - printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __FUNCTION__); + printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); return; } diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index e719d0eeb5c..302ad8dff2c 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -268,7 +268,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) { spin_unlock_irqrestore(&dm_timer_lock, flags); printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n", - __FILE__, __LINE__, __FUNCTION__, id); + __FILE__, __LINE__, __func__, id); dump_stack(); return NULL; } diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index ac9ff1666fc..60f162dc4fa 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -130,8 +130,8 @@ dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan) dmadbg_dumpregs(fname, line, chan, &state); } -#define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan)) -#define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan)) +#define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan)) +#define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan)) #else #define dbg_showregs(chan) do { } while(0) #define dbg_showchan(chan) do { } while(0) @@ -403,7 +403,7 @@ static int s3c2410_dma_start(struct s3c2410_dma_chan *chan) if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { pr_debug("%s: buff not yet loaded, no more todo\n", - __FUNCTION__); + __func__); } else { chan->load_state = S3C2410_DMALOAD_1RUNNING; s3c2410_dma_loadbuffer(chan, chan->next); @@ -463,16 +463,16 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id, return -EINVAL; pr_debug("%s: id=%p, data=%08x, size=%d\n", - __FUNCTION__, id, (unsigned int)data, size); + __func__, id, (unsigned int)data, size); buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); if (buf == NULL) { pr_debug("%s: out of memory (%ld alloc)\n", - __FUNCTION__, (long)sizeof(*buf)); + __func__, (long)sizeof(*buf)); return -ENOMEM; } - //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); + //pr_debug("%s: new buffer %p\n", __func__, buf); //dbg_showchan(chan); buf->next = NULL; @@ -486,18 +486,18 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id, if (chan->curr == NULL) { /* we've got nothing loaded... */ pr_debug("%s: buffer %p queued onto empty channel\n", - __FUNCTION__, buf); + __func__, buf); chan->curr = buf; chan->end = buf; chan->next = NULL; } else { pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n", - chan->number, __FUNCTION__, buf); + chan->number, __func__, buf); if (chan->end == NULL) pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n", - chan->number, __FUNCTION__, chan); + chan->number, __func__, chan); chan->end->next = buf; chan->end = buf; @@ -572,7 +572,7 @@ s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { /* flag error? */ printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", - chan->number, __FUNCTION__); + chan->number, __func__); return; } break; @@ -658,7 +658,7 @@ s3c2410_dma_irq(int irq, void *devpw) if (buf->magic != BUF_MAGIC) { printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n", - chan->number, __FUNCTION__, buf); + chan->number, __func__, buf); return IRQ_HANDLED; } @@ -692,7 +692,7 @@ s3c2410_dma_irq(int irq, void *devpw) if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { /* flag error? */ printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", - chan->number, __FUNCTION__); + chan->number, __func__); return IRQ_HANDLED; } @@ -759,7 +759,7 @@ int s3c2410_dma_request(unsigned int channel, if (!chan->irq_claimed) { pr_debug("dma%d: %s : requesting irq %d\n", - channel, __FUNCTION__, chan->irq); + channel, __func__, chan->irq); chan->irq_claimed = 1; local_irq_restore(flags); @@ -786,7 +786,7 @@ int s3c2410_dma_request(unsigned int channel, /* need to setup */ - pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan); + pr_debug("%s: channel initialised, %p\n", __func__, chan); return chan->number | DMACH_LOW_LEVEL; } @@ -823,7 +823,7 @@ int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) if (chan->state != S3C2410_DMA_IDLE) { pr_debug("%s: need to stop dma channel %p\n", - __FUNCTION__, chan); + __func__, chan); /* possibly flush the channel */ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP); @@ -852,7 +852,7 @@ static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan) unsigned long flags; unsigned long tmp; - pr_debug("%s:\n", __FUNCTION__); + pr_debug("%s:\n", __func__); dbg_showchan(chan); @@ -907,14 +907,14 @@ static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan) struct s3c2410_dma_buf *buf, *next; unsigned long flags; - pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number); + pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number); dbg_showchan(chan); local_irq_save(flags); if (chan->state != S3C2410_DMA_IDLE) { - pr_debug("%s: stopping channel...\n", __FUNCTION__ ); + pr_debug("%s: stopping channel...\n", __func__ ); s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP); } @@ -929,7 +929,7 @@ static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan) next = buf->next; pr_debug("%s: free buffer %p, next %p\n", - __FUNCTION__, buf, buf->next); + __func__, buf, buf->next); s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT); s3c2410_dma_freebuf(buf); @@ -976,7 +976,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan) if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { pr_debug("%s: buff not yet loaded, no more todo\n", - __FUNCTION__); + __func__); } else { chan->load_state = S3C2410_DMALOAD_1RUNNING; s3c2410_dma_loadbuffer(chan, chan->next); @@ -1050,16 +1050,16 @@ int s3c2410_dma_config(dmach_t channel, struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", - __FUNCTION__, channel, xferunit, dcon); + __func__, channel, xferunit, dcon); if (chan == NULL) return -EINVAL; - pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon); + pr_debug("%s: Initial dcon is %08x\n", __func__, dcon); dcon |= chan->dcon & dma_sel.dcon_mask; - pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon); + pr_debug("%s: New dcon is %08x\n", __func__, dcon); switch (xferunit) { case 1: @@ -1075,14 +1075,14 @@ int s3c2410_dma_config(dmach_t channel, break; default: - pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit); + pr_debug("%s: bad transfer size %d\n", __func__, xferunit); return -EINVAL; } dcon |= S3C2410_DCON_HWTRIG; dcon |= S3C2410_DCON_INTREQ; - pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon); + pr_debug("%s: dcon now %08x\n", __func__, dcon); chan->dcon = dcon; chan->xfer_unit = xferunit; @@ -1099,7 +1099,7 @@ int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) if (chan == NULL) return -EINVAL; - pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags); + pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags); chan->flags = flags; @@ -1120,7 +1120,7 @@ int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) if (chan == NULL) return -EINVAL; - pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn); + pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn); chan->op_fn = rtn; @@ -1136,7 +1136,7 @@ int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) if (chan == NULL) return -EINVAL; - pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn); + pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn); chan->callback_fn = rtn; @@ -1170,7 +1170,7 @@ int s3c2410_dma_devconfig(int channel, return -EINVAL; pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", - __FUNCTION__, (int)source, hwcfg, devaddr); + __func__, (int)source, hwcfg, devaddr); chan->source = source; chan->dev_addr = devaddr; @@ -1180,7 +1180,7 @@ int s3c2410_dma_devconfig(int channel, case S3C2410_DMASRC_HW: /* source is hardware */ pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n", - __FUNCTION__, devaddr, hwcfg); + __func__, devaddr, hwcfg); dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3); dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr); dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0)); @@ -1190,8 +1190,8 @@ int s3c2410_dma_devconfig(int channel, case S3C2410_DMASRC_MEM: /* source is memory */ - pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n", - __FUNCTION__, devaddr, hwcfg); + pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n", + __func__, devaddr, hwcfg); dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0)); dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr); dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3); -- cgit From 6bb68f8867348257e757de9c30ada4e90fe695d9 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Tue, 4 Mar 2008 15:08:02 -0800 Subject: [ARM] AT91: correct at91sam9263ek LCD power gpio pin Correct GPIO pin assignment for the LCD power control (PCI) Signed-off-by: Nicolas Ferre Cc: David Brownell Cc: Andrew Victor Signed-off-by: Andrew Morton Signed-off-by: Russell King --- arch/arm/mach-at91/board-sam9263ek.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 38313abef65..bf103b24c93 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -245,10 +245,7 @@ static struct fb_monspecs at91fb_default_monspecs = { static void at91_lcdc_power_control(int on) { - if (on) - at91_set_gpio_value(AT91_PIN_PD12, 0); /* power up */ - else - at91_set_gpio_value(AT91_PIN_PD12, 1); /* power down */ + at91_set_gpio_value(AT91_PIN_PA30, on); } /* Driver datas */ -- cgit From ac5bbf21bf38b3f5eaa8cb1e17f7513dc354afda Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 6 Mar 2008 16:21:42 +0100 Subject: [ARM] 4851/1: ns9xxx: fix size of gpiores MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GPIO_MAX is the number of the last gpio, not the number of gpios. So the bitmap must provide GPIO_MAX + 1 bits. Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King --- arch/arm/mach-ns9xxx/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c index b2230213b98..5286e9fc1d3 100644 --- a/arch/arm/mach-ns9xxx/gpio.c +++ b/arch/arm/mach-ns9xxx/gpio.c @@ -31,7 +31,7 @@ static spinlock_t gpio_lock = __SPIN_LOCK_UNLOCKED(gpio_lock); /* only access gpiores with atomic ops */ -static DECLARE_BITMAP(gpiores, GPIO_MAX); +static DECLARE_BITMAP(gpiores, GPIO_MAX + 1); static inline int ns9xxx_valid_gpio(unsigned gpio) { -- cgit From a4f14bace8ddf0cc26fc2d658b6dd37c71178770 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 6 Mar 2008 16:22:17 +0100 Subject: [ARM] 4853/1: include uImage target in make help MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King --- arch/arm/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 7b8ff66febe..1a4649667ec 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -251,6 +251,7 @@ define archhelp echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)' echo ' Image - Uncompressed kernel image (arch/$(ARCH)/boot/Image)' echo '* xipImage - XIP kernel image, if configured (arch/$(ARCH)/boot/xipImage)' + echo ' uImage - U-Boot wrapped zImage' echo ' bootpImage - Combined zImage and initial RAM disk' echo ' (supply initrd image via make variable INITRD=)' echo ' install - Install uncompressed kernel' -- cgit From 88603f1dc1bf414dc21a0361693d1270231a6c59 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Fri, 7 Mar 2008 11:41:18 +0100 Subject: [ARM] 4855/1: Orion: use correct ethernet unit address range Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-orion/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index 2d6d413f023..bbc2b4ec932 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -179,8 +179,8 @@ static struct platform_device orion_ehci1 = { static struct resource orion_eth_shared_resources[] = { { - .start = ORION_ETH_PHYS_BASE, - .end = ORION_ETH_PHYS_BASE + 0xffff, + .start = ORION_ETH_PHYS_BASE + 0x2000, + .end = ORION_ETH_PHYS_BASE + 0x3fff, .flags = IORESOURCE_MEM, }, }; -- cgit From 4c91363dc01310dc34f1621ef00d680b4404f71c Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Fri, 7 Mar 2008 11:47:23 +0100 Subject: [ARM] 4856/1: Orion: initialise the sixth PCIe MBUS mapping window as well Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-orion/addr-map.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 2e2fd63643c..58cc3c0333b 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -97,14 +97,20 @@ #define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) #define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) #define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) -#define PCIE_WIN_CTRL(n) ORION_PCIE_REG(0x1820 + ((n) << 4)) -#define PCIE_WIN_BASE(n) ORION_PCIE_REG(0x1824 + ((n) << 4)) -#define PCIE_WIN_REMAP(n) ORION_PCIE_REG(0x182c + ((n) << 4)) +#define PCIE_WIN_CTRL(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ + ORION_PCIE_REG(0x1880)) +#define PCIE_WIN_BASE(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ + ORION_PCIE_REG(0x1884)) +#define PCIE_WIN_REMAP(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x182c + ((n) << 4)) : \ + ORION_PCIE_REG(0x188c)) #define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0) #define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0) #define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4) #define PCIE_MAX_BARS 3 -#define PCIE_MAX_WINS 5 +#define PCIE_MAX_WINS 6 /* * Use PCIE BAR '1' for all DDR banks -- cgit From 06cad098d28e02d2ee3ed587bb261377e4ae2f17 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 18 Oct 2007 23:04:43 -0700 Subject: ARM: OMAP: Fix clockevent support for hrtimers One-shot mode was broken in MPU-timer support for OMAP1 due to a typo. Also, ensure timer is stopped before changing the auto-reload flag. The TRM says changing the AR flag when timer is running is undefined. Also set GENERIC_CLOCKEVENTS for all omaps. Signed-off-by: Tim Bird Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/Kconfig | 1 + arch/arm/mach-omap1/time.c | 10 +++++++++- arch/arm/plat-omap/Kconfig | 1 - 3 files changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 955fc53c1c0..4039a133006 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -469,6 +469,7 @@ config ARCH_OMAP bool "TI OMAP" select GENERIC_GPIO select GENERIC_TIME + select GENERIC_CLOCKEVENTS help Support for TI's OMAP platform (OMAP1 and OMAP2). diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 237651ebae5..572a2dbc72a 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -132,13 +132,20 @@ static inline void omap_mpu_timer_start(int nr, unsigned long load_val, timer->cntl = timerflags; } +static inline void omap_mpu_timer_stop(int nr) +{ + volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); + + timer->cntl &= ~MPU_TIMER_ST; +} + /* * --------------------------------------------------------------------------- * MPU timer 1 ... count down to zero, interrupt, reload * --------------------------------------------------------------------------- */ static int omap_mpu_set_next_event(unsigned long cycles, - struct clock_event_device *evt) + struct clock_event_device *evt) { omap_mpu_timer_start(0, cycles, 0); return 0; @@ -152,6 +159,7 @@ static void omap_mpu_set_mode(enum clock_event_mode mode, omap_mpu_set_autoreset(0); break; case CLOCK_EVT_MODE_ONESHOT: + omap_mpu_timer_stop(0); omap_mpu_remove_autoreset(0); break; case CLOCK_EVT_MODE_UNUSED: diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index c1f7e5a819a..b917206ee90 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -11,7 +11,6 @@ choice config ARCH_OMAP1 bool "TI OMAP1" - select GENERIC_CLOCKEVENTS config ARCH_OMAP2 bool "TI OMAP2" -- cgit From 4de8c75b00181db8169438e9fa4fb7bdf0db72d5 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 16 Jan 2008 21:56:14 -0800 Subject: ARM: OMAP: Fix GPIO IRQ unmask GPIO IRQ unmask doesn't actually do anything useful. The problem is hidden by a separate explicit mass unmask at the end of the chained bank handler. Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 66a1455595f..8c78e4e57b5 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -1134,10 +1134,9 @@ static void gpio_mask_irq(unsigned int irq) static void gpio_unmask_irq(unsigned int irq) { unsigned int gpio = irq - IH_GPIO_BASE; - unsigned int gpio_idx = get_gpio_index(gpio); struct gpio_bank *bank = get_irq_chip_data(irq); - _set_gpio_irqenable(bank, gpio_idx, 1); + _set_gpio_irqenable(bank, gpio, 1); } static struct irq_chip gpio_irq_chip = { -- cgit From 271c487e9110760c208758ba72971a531f675362 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 13 Mar 2008 15:03:36 +0200 Subject: ARM: OMAP: Fix missing makefile options Although audio and dsp drivers are not integrated yet, allow compiling in mailbox and mcbsp to see any build warnings. Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/Makefile | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index ce17df31b84..8f56c255d1e 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -14,9 +14,14 @@ obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o # OCPI interconnect support for 1710, 1610 and 5912 obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o +obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_CPU_FREQ) += cpu-omap.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o obj-$(CONFIG_I2C_OMAP) += i2c.o + +# OMAP mailbox framework +obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o + -- cgit From f4b6a7ef6c64d84e252d32df631813bd09ea3756 Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Tue, 11 Mar 2008 01:10:35 +0530 Subject: ARM: OMAP: Fix chain_a_transfer return value This patch changes the return value of omap_dma_chain_a_transfer to 0 on success instead of the flag 'start_dma', which wasn't really useful for anything. Signed-off-by: Anand Gadiyar Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 91004a3c479..06293bfcc83 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1248,7 +1248,7 @@ EXPORT_SYMBOL(omap_dma_chain_status); * @param frame_count * @param callbk_data - channel callback parameter data. * - * @return - Success : start_dma status + * @return - Success : 0 * Failure: -EINVAL/-EBUSY */ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, @@ -1367,7 +1367,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } } - return start_dma; + return 0; } EXPORT_SYMBOL(omap_dma_chain_a_transfer); -- cgit From 026a6fef55da7239ca0970000eb62b9eab5ba281 Mon Sep 17 00:00:00 2001 From: "Gadiyar, Anand" Date: Sat, 8 Mar 2008 05:49:13 -0800 Subject: ARM: OMAP: Fix DMA CLINK mask, clear spurious interrupt Fix CLINK mask, clear spurious interrupt. Signed-off-by: Gadiyar, Anand Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dma.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 06293bfcc83..793740686be 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1020,12 +1020,12 @@ static void create_dma_lch_chain(int lch_head, int lch_queue) } w = OMAP_DMA_CLNK_CTRL_REG(lch_head); - w &= ~(0x0f); + w &= ~(0x1f); w |= lch_queue; OMAP_DMA_CLNK_CTRL_REG(lch_head) = w; w = OMAP_DMA_CLNK_CTRL_REG(lch_queue); - w &= ~(0x0f); + w &= ~(0x1f); w |= (dma_chan[lch_queue].next_linked_ch); OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w; } @@ -1663,6 +1663,7 @@ static int omap2_dma_handle_ch(int ch) if (!status) { if (printk_ratelimit()) printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch); + omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); return 0; } if (unlikely(dma_chan[ch].dev_id == -1)) { -- cgit From c6b349ed8a288f1f69fdd560d509d81351cafd89 Mon Sep 17 00:00:00 2001 From: Will Newton Date: Tue, 11 Mar 2008 09:47:43 +0000 Subject: ARM: OMAP1: Fix typo in OMAP1 MPU clock source initialization Fix typo in OMAP1 MPU clock source initialization. Signed-off-by: Will Newton Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 572a2dbc72a..a4f8b205543 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -171,7 +171,7 @@ static void omap_mpu_set_mode(enum clock_event_mode mode, static struct clock_event_device clockevent_mpu_timer1 = { .name = "mpu_timer1", - .features = CLOCK_EVT_FEAT_PERIODIC, CLOCK_EVT_FEAT_ONESHOT, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .shift = 32, .set_next_event = omap_mpu_set_next_event, .set_mode = omap_mpu_set_mode, -- cgit From 391c569daa6e4e999592966e29c146dfc4de9a9c Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Thu, 13 Mar 2008 09:53:21 +0100 Subject: [ARM] 4864/1: Enable write buffer coalescing on IOP Some bootloaders are disabling write buffer coalescing. Enable it back under linux. Signed-off-by: Arnaud Patard Signed-off-by: Russell King --- arch/arm/mm/proc-xscale.S | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index c156ddab9a2..016690b9d56 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -114,6 +114,10 @@ clean_addr: .word CLEAN_ADDR * Nothing too exciting at the moment */ ENTRY(cpu_xscale_proc_init) + @ enable write buffer coalescing. Some bootloader disable it + mrc p15, 0, r1, c1, c0, 1 + bic r1, r1, #1 + mcr p15, 0, r1, c1, c0, 1 mov pc, lr /* -- cgit From 4e7ffb6ab4c42740eaf8b8d905e95f106d9eb022 Mon Sep 17 00:00:00 2001 From: Gordon Farquharson Date: Fri, 14 Mar 2008 04:07:46 +0100 Subject: [ARM] 4865/1: Register the F75375 device in the GLAN Tank platform code This patch adds the code required to register the F75375 device on the GLAN Tank. Signed-off-by: Gordon Farquharson Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/glantank.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 74c65ce221d..d2a7b04f1cb 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -14,8 +14,10 @@ #include #include +#include #include #include +#include #include #include #include @@ -167,11 +169,21 @@ static struct platform_device glantank_serial_device = { .resource = &glantank_uart_resource, }; +static struct f75375s_platform_data glantank_f75375s = { + .pwm = { 255, 255 }, + .pwm_enable = { 0, 0 }, +}; + static struct i2c_board_info __initdata glantank_i2c_devices[] = { { I2C_BOARD_INFO("rtc-rs5c372", 0x32), .type = "rs5c372a", }, + { + I2C_BOARD_INFO("f75375", 0x2e), + .type = "f75375", + .platform_data = &glantank_f75375s, + }, }; static void glantank_power_off(void) -- cgit From ee4cd588a3d9f81b5b13b76a498c3118a61f1dd2 Mon Sep 17 00:00:00 2001 From: janboe Date: Wed, 19 Mar 2008 03:34:23 +0100 Subject: [ARM] 4870/1: fix signal return code when enable CONFIG_OABI_COMPAT fix signal return code when enable CONFIG_OABI_COMPAT Signed-off-by: Janboe Ye Signed-off-by: Russell King --- arch/arm/kernel/signal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 54cdf1aeefc..ef2f86a5e78 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -26,8 +26,8 @@ /* * For ARM syscalls, we encode the syscall number into the instruction. */ -#define SWI_SYS_SIGRETURN (0xef000000|(__NR_sigreturn)) -#define SWI_SYS_RT_SIGRETURN (0xef000000|(__NR_rt_sigreturn)) +#define SWI_SYS_SIGRETURN (0xef000000|(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE)) +#define SWI_SYS_RT_SIGRETURN (0xef000000|(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE)) /* * With EABI, the syscall number has to be loaded into r7. -- cgit From c3a1c9c75b986e5a2c5d878ef0700a1ca6bb895a Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 26 Mar 2008 18:42:10 -0700 Subject: iop: Make IOP ATU window debug readable Make the inbound and outbound memory windows debugging meaningful to those who don't know what the register names for the ATU mean. IOW, use plain english rather than register jargon. Cc: Lennert Buytenhek Acked-by: Dan Williams Signed-off-by: Russell King --- arch/arm/plat-iop/pci.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 98d01517b56..9e83066cc05 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -329,23 +329,28 @@ void __init iop3xx_pci_preinit(void) iop3xx_atu_setup(); } - DBG("PCI: Intel 803xx PCI init code.\n"); + DBG("PCI: Intel IOP3xx PCI init.\n"); + DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", + *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); + DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n", + *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1); + DBG("PCI: Outbound IO window: PCI 0x%08x\n", + *IOP3XX_OIOWTVR); + + DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", + *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); + DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n", + *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1); + DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", + *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); + DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", + *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); + + DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", + 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); + DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); - DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n", - *IOP3XX_OMWTVR0, - *IOP3XX_OIOWTVR); DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); - DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n", - *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); - DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0); - DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n", - *IOP3XX_IABAR1, *IOP3XX_IALR1); - DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n", - *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); - DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n", - *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); - DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n", - *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); } -- cgit From 27eedbf557f511efbe5651fa2fbfa0e4e8315ab7 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 26 Mar 2008 18:44:58 -0700 Subject: iop: when scanning PCI bus, translate the PCI addresses according to the outbound window settings ... otherwise we end up trying to access peripherals using wrong PCI addresses. Cc: Lennert Buytenhek Acked-by: Dan Williams Signed-off-by: Russell King --- arch/arm/plat-iop/pci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 9e83066cc05..ee6deaabf9b 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -209,8 +209,11 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) res[1].flags = IORESOURCE_MEM; request_resource(&iomem_resource, &res[1]); - sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA; - sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA; + /* + * Use whatever translation is already setup. + */ + sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; + sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; sys->resource[0] = &res[0]; sys->resource[1] = &res[1]; -- cgit From 97c46048ce73c27fd2734299f07a8c06c8156a2e Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 26 Mar 2008 18:46:42 -0700 Subject: iop: Program outbound windows using the correct definitions The outbound translate registers should be programmed with the bus addresses that are defined in the header files, rather than the physical address. Currently it doesn't matter because they're identical, but the headers currently allow them to be different, and not using the right macros here means that people are in for a surprise if they change them. Cc: Lennert Buytenhek Acked-by: Dan Williams Signed-off-by: Russell King --- arch/arm/plat-iop/pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index ee6deaabf9b..6ed374fa408 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -253,11 +253,11 @@ void __init iop3xx_atu_setup(void) *IOP3XX_IATVR2 = PHYS_OFFSET; /* Outbound window 0 */ - *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA; + *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA; *IOP3XX_OUMWTVR0 = 0; /* Outbound window 1 */ - *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE; + *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE; *IOP3XX_OUMWTVR1 = 0; /* BAR 3 ( Disabled ) */ @@ -268,7 +268,7 @@ void __init iop3xx_atu_setup(void) /* Setup the I/O Bar */ - *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;; + *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA; /* Enable inbound and outbound cycles */ -- cgit From c34002c102880bfac5b449b41e5313dcda186db8 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 26 Mar 2008 19:12:38 -0700 Subject: iop: unconditionally initialize the ATU on platforms known to be 'hosts' Platforms like iq80321 and iq80331 which may be host-bus-adapters require 'iop3xx_init_atu=y' to be specified on the kernel command line. Signed-off-by: Dan Williams --- arch/arm/mach-iop32x/Kconfig | 8 -------- arch/arm/mach-iop32x/iq31244.c | 11 ++++------- arch/arm/mach-iop32x/iq80321.c | 2 +- arch/arm/mach-iop33x/Kconfig | 8 -------- arch/arm/mach-iop33x/iq80331.c | 2 +- arch/arm/mach-iop33x/iq80332.c | 2 +- arch/arm/plat-iop/pci.c | 33 +++++++++++++++++++++++++++------ 7 files changed, 34 insertions(+), 32 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index dbe07c9472e..5e8c6f7dfab 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig @@ -34,14 +34,6 @@ config MACH_N2100 Say Y here if you want to run your kernel on the Thecus n2100 NAS appliance. -config IOP3XX_ATU - bool "Enable the PCI Controller" - default y - help - Say Y here if you want the IOP to initialize its PCI Controller. - Say N if the IOP is an add in card, the host system owns the PCI - bus in this case. - config MACH_EM7210 bool "Enable support for the Lanner EM7210" help diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 98cfa1cd6bd..4a89823bceb 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -178,10 +178,9 @@ static struct hw_pci iq31244_pci __initdata = { static int __init iq31244_pci_init(void) { - if (is_ep80219()) { - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) - pci_common_init(&ep80219_pci); - } else if (machine_is_iq31244()) { + if (is_ep80219()) + pci_common_init(&ep80219_pci); + else if (machine_is_iq31244()) { if (is_80219()) { printk("note: iq31244 board type has been selected\n"); printk("note: to select ep80219 operation:\n"); @@ -190,9 +189,7 @@ static int __init iq31244_pci_init(void) printk("\t2/ update boot loader to pass" " the ep80219 id: %d\n", MACH_TYPE_EP80219); } - - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) - pci_common_init(&iq31244_pci); + pci_common_init(&iq31244_pci); } return 0; diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 18ad29f213b..1da3c911edd 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -106,7 +106,7 @@ static struct hw_pci iq80321_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, + .preinit = iop3xx_pci_preinit_cond, .scan = iop3xx_pci_scan_bus, .map_irq = iq80321_pci_map_irq, }; diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig index 45598e09689..9aa016bb18f 100644 --- a/arch/arm/mach-iop33x/Kconfig +++ b/arch/arm/mach-iop33x/Kconfig @@ -16,14 +16,6 @@ config MACH_IQ80332 Say Y here if you want to run your kernel on the Intel IQ80332 evaluation kit for the IOP332 chipset. -config IOP3XX_ATU - bool "Enable the PCI Controller" - default y - help - Say Y here if you want the IOP to initialize its PCI Controller. - Say N if the IOP is an add in card, the host system owns the PCI - bus in this case. - endmenu endif diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index 433188ebff2..de39fd77857 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -89,7 +89,7 @@ static struct hw_pci iq80331_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, + .preinit = iop3xx_pci_preinit_cond, .scan = iop3xx_pci_scan_bus, .map_irq = iq80331_pci_map_irq, }; diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 416c09564cc..4904fd78445 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -89,7 +89,7 @@ static struct hw_pci iq80332_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, + .preinit = iop3xx_pci_preinit_cond, .scan = iop3xx_pci_scan_bus, .map_irq = iq80332_pci_map_irq, }; diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 6ed374fa408..d9bc15a69e5 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -24,6 +24,7 @@ #include #include #include +#include // #define DEBUG @@ -325,13 +326,16 @@ void __init iop3xx_atu_disable(void) /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ int init_atu; -void __init iop3xx_pci_preinit(void) -{ - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { - iop3xx_atu_disable(); - iop3xx_atu_setup(); - } +int iop3xx_get_init_atu(void) { + /* check if default has been overridden */ + if (init_atu != IOP3XX_INIT_ATU_DEFAULT) + return init_atu; + else + return IOP3XX_INIT_ATU_DISABLE; +} +static void __init iop3xx_atu_debug(void) +{ DBG("PCI: Intel IOP3xx PCI init.\n"); DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); @@ -358,6 +362,23 @@ void __init iop3xx_pci_preinit(void) hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); } +/* for platforms that might be host-bus-adapters */ +void __init iop3xx_pci_preinit_cond(void) +{ + if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { + iop3xx_atu_disable(); + iop3xx_atu_setup(); + iop3xx_atu_debug(); + } +} + +void __init iop3xx_pci_preinit(void) +{ + iop3xx_atu_disable(); + iop3xx_atu_setup(); + iop3xx_atu_debug(); +} + /* allow init_atu to be user overridden */ static int __init iop3xx_init_atu_setup(char *str) { -- cgit From 83b6d822e4237052371e771b1f994823615a5341 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: Orion: initialise mbus DRAM target info on boot Initialise orion_mbus_dram_info on boot, and prepare for passing this info into peripheral drivers. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 29 +++++++++++++++++++++++++++++ arch/arm/mach-orion/common.c | 1 + arch/arm/mach-orion/common.h | 1 + 3 files changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 58cc3c0333b..ab4484cc14b 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -12,6 +12,7 @@ #include #include +#include #include #include "common.h" @@ -168,6 +169,9 @@ #define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) #define SATA_MAX_WIN 4 + +struct mbus_dram_target_info orion_mbus_dram_info; + static int __init orion_cpu_win_can_remap(u32 win) { u32 dev, rev; @@ -257,6 +261,7 @@ void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, in void __init orion_setup_cpu_wins(void) { int i; + int cs; /* * First, disable and clear windows @@ -281,6 +286,30 @@ void __init orion_setup_cpu_wins(void) ORION_PCIE_MEM_SIZE, -1); orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE, -1); + + /* + * Setup MBUS dram target info. + */ + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(DDR_BASE_CS(i)); + u32 size = readl(DDR_SIZE_CS(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &orion_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xff000000; + w->size = (size | 0x00ffffff) + 1; + } + } + orion_mbus_dram_info.num_cs = cs; } /* diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index bbc2b4ec932..cd9aa43bb47 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 501497cc2c4..2718245ec4a 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -29,6 +29,7 @@ enum orion_target { ORION_MAX_TARGETS }; +extern struct mbus_dram_target_info orion_mbus_dram_info; void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); void orion_setup_cpu_wins(void); void orion_setup_eth_wins(void); -- cgit From 1f2223b12b62a97d66e39199db50ed3fae9222c0 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: Orion: make PCIe/PCI support use mbus DRAM info Make the Orion PCIe/PCI code initialise MBUS decode windows based on mbus_dram_target_info instead of reading the info from the Orion DDR unit decode registers directly, and move the window code with the other PCI code, where it can be called as part of the generic PCIe/PCI init process. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 148 ----------------------------------- arch/arm/mach-orion/common.c | 2 - arch/arm/mach-orion/common.h | 5 -- arch/arm/mach-orion/pci.c | 171 ++++++++++++++++++++++++++++++++++++++++- 4 files changed, 168 insertions(+), 158 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index ab4484cc14b..69cd0876f6b 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -92,56 +92,6 @@ #define CPU_WIN_DEV_CS1 6 #define CPU_WIN_DEV_CS2 7 -/* - * PCIE Address Decode Windows registers - */ -#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) -#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) -#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) -#define PCIE_WIN_CTRL(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ - ORION_PCIE_REG(0x1880)) -#define PCIE_WIN_BASE(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ - ORION_PCIE_REG(0x1884)) -#define PCIE_WIN_REMAP(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x182c + ((n) << 4)) : \ - ORION_PCIE_REG(0x188c)) -#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0) -#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0) -#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4) -#define PCIE_MAX_BARS 3 -#define PCIE_MAX_WINS 6 - -/* - * Use PCIE BAR '1' for all DDR banks - */ -#define PCIE_DRAM_BAR 1 - -/* - * PCI Address Decode Windows registers - */ -#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ - ((n) == 1) ? ORION_PCI_REG(0xd08) : \ - ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) -#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ - ((n) == 1) ? ORION_PCI_REG(0xd48) : \ - ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) -#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) -#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4)) -#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4)) -#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4)) -#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) - -/* - * PCI configuration heleprs for BAR settings - */ -#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) -#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) -#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) - /* * Gigabit Ethernet Address Decode Windows registers */ @@ -312,104 +262,6 @@ void __init orion_setup_cpu_wins(void) orion_mbus_dram_info.num_cs = cs; } -/* - * Setup PCIE BARs and Address Decode Wins: - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks - * WIN[0-3] -> DRAM bank[0-3] - */ -void __init orion_setup_pcie_wins(void) -{ - u32 base, size, i; - - /* - * First, disable and clear BARs and windows - */ - for (i = 1; i < PCIE_MAX_BARS; i++) { - orion_write(PCIE_BAR_CTRL(i), 0); - orion_write(PCIE_BAR_LO(i), 0); - orion_write(PCIE_BAR_HI(i), 0); - } - - for (i = 0; i < PCIE_MAX_WINS; i++) { - orion_write(PCIE_WIN_CTRL(i), 0); - orion_write(PCIE_WIN_BASE(i), 0); - orion_write(PCIE_WIN_REMAP(i), 0); - } - - /* - * Setup windows for DDR banks. Count total DDR size on the fly. - */ - base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0))); - size = 0; - for (i = 0; i < DDR_MAX_CS; i++) { - u32 bank_base, bank_size; - bank_size = orion_read(DDR_SIZE_CS(i)); - bank_base = orion_read(DDR_BASE_CS(i)); - if (bank_size & DDR_BANK_EN) { - bank_size = DDR_REG_TO_SIZE(bank_size); - bank_base = DDR_REG_TO_BASE(bank_base); - orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000); - orion_write(PCIE_WIN_REMAP(i), 0); - orion_write(PCIE_WIN_CTRL(i), - ((bank_size-1) & 0xffff0000) | - (ATTR_DDR_CS(i) << 8) | - (TARGET_DDR << 4) | - (PCIE_DRAM_BAR << 1) | WIN_EN); - size += bank_size; - } - } - - /* - * Setup BAR[1] to all DRAM banks - */ - orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000); - orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0); - orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR), - ((size - 1) & 0xffff0000) | WIN_EN); -} - -void __init orion_setup_pci_wins(void) -{ - u32 base, size, i; - - /* - * First, disable windows - */ - orion_write(PCI_BAR_ENABLE, 0xffffffff); - - /* - * Setup windows for DDR banks. - */ - for (i = 0; i < DDR_MAX_CS; i++) { - base = orion_read(DDR_BASE_CS(i)); - size = orion_read(DDR_SIZE_CS(i)); - if (size & DDR_BANK_EN) { - u32 bus, dev, func, reg, val; - size = DDR_REG_TO_SIZE(size); - base = DDR_REG_TO_BASE(base); - bus = orion_pci_local_bus_nr(); - dev = orion_pci_local_dev_nr(); - func = PCI_CONF_FUNC_BAR_CS(i); - reg = PCI_CONF_REG_BAR_LO_CS(i); - orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); - orion_pci_hw_wr_conf(bus, dev, func, reg, 4, - (base & 0xfffff000) | (val & 0xfff)); - reg = PCI_CONF_REG_BAR_HI_CS(i); - orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); - orion_write(PCI_BAR_SIZE_DDR_CS(i), - (size - 1) & 0xfffff000); - orion_write(PCI_BAR_REMAP_DDR_CS(i), - base & 0xfffff000); - orion_clrbits(PCI_BAR_ENABLE, (1 << i)); - } - } - - /* - * Disable automatic update of address remaping when writing to BARs - */ - orion_setbits(PCI_ADDR_DECODE_CTRL, 1); -} - void __init orion_setup_usb_wins(void) { int i; diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index cd9aa43bb47..cc16588e8c0 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -336,8 +336,6 @@ void __init orion_init(void) orion_setup_cpu_wins(); orion_setup_usb_wins(); orion_setup_eth_wins(); - orion_setup_pci_wins(); - orion_setup_pcie_wins(); if (dev == MV88F5182_DEV_ID) orion_setup_sata_wins(); diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 2718245ec4a..961daaa0b91 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -34,8 +34,6 @@ void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap void orion_setup_cpu_wins(void); void orion_setup_eth_wins(void); void orion_setup_usb_wins(void); -void orion_setup_pci_wins(void); -void orion_setup_pcie_wins(void); void orion_setup_sata_wins(void); /* @@ -49,11 +47,8 @@ struct pci_bus; void orion_pcie_id(u32 *dev, u32 *rev); u32 orion_pcie_local_bus_nr(void); u32 orion_pci_local_bus_nr(void); -u32 orion_pci_local_dev_nr(void); int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); -int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val); -int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val); /* * Valid GPIO pins according to MPP setup, used by machine-setup. diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index b109bb46681..cfd3d064c20 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -12,6 +12,7 @@ #include #include +#include #include #include "common.h" @@ -58,6 +59,29 @@ #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) #define PCIE_CONF_ADDR_EN (1 << 31) +/* + * PCIE Address Decode Windows registers + */ +#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) +#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) +#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) +#define PCIE_WIN_CTRL(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ + ORION_PCIE_REG(0x1880)) +#define PCIE_WIN_BASE(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ + ORION_PCIE_REG(0x1884)) +#define PCIE_WIN_REMAP(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x182c + ((n) << 4)) : \ + ORION_PCIE_REG(0x188c)) +#define PCIE_MAX_BARS 3 +#define PCIE_MAX_WINS 6 + +/* + * Use PCIE BAR '1' for all DDR banks + */ +#define PCIE_DRAM_BAR 1 + /* * PCIE config cycles are done by programming the PCIE_CONF_ADDR register * and then reading the PCIE_CONF_DATA register. Need to make sure these @@ -95,6 +119,56 @@ static void orion_pcie_set_bus_nr(int nr) orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS); } +/* + * Setup PCIE BARs and Address Decode Wins: + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks + * WIN[0-3] -> DRAM bank[0-3] + */ +static void orion_setup_pcie_wins(struct mbus_dram_target_info *dram) +{ + u32 size; + int i; + + /* + * First, disable and clear BARs and windows + */ + for (i = 1; i < PCIE_MAX_BARS; i++) { + writel(0, PCIE_BAR_CTRL(i)); + writel(0, PCIE_BAR_LO(i)); + writel(0, PCIE_BAR_HI(i)); + } + + for (i = 0; i < PCIE_MAX_WINS; i++) { + writel(0, PCIE_WIN_CTRL(i)); + writel(0, PCIE_WIN_BASE(i)); + writel(0, PCIE_WIN_REMAP(i)); + } + + /* + * Setup windows for DDR banks. Count total DDR size on the fly. + */ + size = 0; + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + + writel(cs->base & 0xffff0000, PCIE_WIN_BASE(i)); + writel(0, PCIE_WIN_REMAP(i)); + writel(((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | + (PCIE_DRAM_BAR << 1) | 1, PCIE_WIN_CTRL(i)); + + size += cs->size; + } + + /* + * Setup BAR[1] to all DRAM banks + */ + writel(dram->cs[0].base, PCIE_BAR_LO(PCIE_DRAM_BAR)); + writel(0, PCIE_BAR_HI(PCIE_DRAM_BAR)); + writel(((size - 1) & 0xffff0000) | 1, PCIE_BAR_CTRL(PCIE_DRAM_BAR)); +} + static void orion_pcie_master_slave_enable(void) { orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER | @@ -219,6 +293,11 @@ static int orion_pcie_setup(struct pci_sys_data *sys) { struct resource *res; + /* + * Point PCIe unit MBUS decode windows to DRAM space. + */ + orion_setup_pcie_wins(&orion_mbus_dram_info); + /* * Master + Slave enable */ @@ -310,6 +389,27 @@ static int orion_pcie_setup(struct pci_sys_data *sys) #define PCIX_STAT_BUS_OFFS 8 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) +/* + * PCI Address Decode Windows registers + */ +#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ + ((n) == 1) ? ORION_PCI_REG(0xd08) : \ + ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ + ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) +#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ + ((n) == 1) ? ORION_PCI_REG(0xd48) : \ + ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ + ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) +#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) +#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) + +/* + * PCI configuration helpers for BAR settings + */ +#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) +#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) +#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) + /* * PCI config cycles are done by programming the PCI_CONF_ADDR register * and then reading the PCI_CONF_DATA register. Need to make sure these @@ -323,13 +423,13 @@ u32 orion_pci_local_bus_nr(void) return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } -u32 orion_pci_local_dev_nr(void) +static u32 orion_pci_local_dev_nr(void) { u32 conf = orion_read(PCI_P2P_CONF); return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); } -int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, +static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val) { unsigned long flags; @@ -351,7 +451,7 @@ int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, return PCIBIOS_SUCCESSFUL; } -int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, +static int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val) { unsigned long flags; @@ -451,10 +551,75 @@ static void orion_pci_master_slave_enable(void) orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); } +static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) +{ + u32 win_enable; + u32 bus; + u32 dev; + int i; + + /* + * First, disable windows. + */ + win_enable = 0xffffffff; + orion_write(PCI_BAR_ENABLE, win_enable); + + /* + * Setup windows for DDR banks. + */ + bus = orion_pci_local_bus_nr(); + dev = orion_pci_local_dev_nr(); + + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); + u32 reg; + u32 val; + + /* + * Write DRAM bank base address register. + */ + reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); + orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); + val = (cs->base & 0xfffff000) | (val & 0xfff); + orion_pci_hw_wr_conf(bus, dev, func, reg, 4, val); + + /* + * Write DRAM bank size register. + */ + reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); + orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); + orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), + (cs->size - 1) & 0xfffff000); + orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), + cs->base & 0xfffff000); + + /* + * Enable decode window for this chip select. + */ + win_enable &= ~(1 << cs->cs_index); + } + + /* + * Re-enable decode windows. + */ + orion_write(PCI_BAR_ENABLE, win_enable); + + /* + * Disable automatic update of address remaping when writing to BARs. + */ + orion_setbits(PCI_ADDR_DECODE_CTRL, 1); +} + static int orion_pci_setup(struct pci_sys_data *sys) { struct resource *res; + /* + * Point PCI unit MBUS decode windows to DRAM space. + */ + orion_setup_pci_wins(&orion_mbus_dram_info); + /* * Master + Slave enable */ -- cgit From 92aecfa95523384923b52c8ddaf948fc02a53e82 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: ehci-orion: mbus decode window support Make it possible to pass mbus_dram_target_info to the ehci-orion driver via the platform data, make the ehci-orion driver program the window registers based on this data if it is passed in, and make the Orion platform setup code use this method instead of programming the EHCI mbus window registers by hand. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 49 ------------------------------------------ arch/arm/mach-orion/common.c | 8 ++++++- arch/arm/mach-orion/common.h | 1 - 3 files changed, 7 insertions(+), 51 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 69cd0876f6b..40bcb986ab9 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -103,15 +103,6 @@ #define ETH_MAX_WIN 6 #define ETH_MAX_REMAP_WIN 4 -/* - * USB Address Decode Windows registers - */ -#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \ - : ORION_USB1_REG(0x320 + ((w) << 4))) -#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \ - : ORION_USB1_REG(0x324 + ((w) << 4))) -#define USB_MAX_WIN 4 - /* * SATA Address Decode Windows registers */ @@ -262,46 +253,6 @@ void __init orion_setup_cpu_wins(void) orion_mbus_dram_info.num_cs = cs; } -void __init orion_setup_usb_wins(void) -{ - int i; - u32 usb_if, dev, rev; - u32 max_usb_if = 1; - - orion_pcie_id(&dev, &rev); - if (dev == MV88F5182_DEV_ID) - max_usb_if = 2; - - for (usb_if = 0; usb_if < max_usb_if; usb_if++) { - /* - * First, disable and clear windows - */ - for (i = 0; i < USB_MAX_WIN; i++) { - orion_write(USB_WIN_BASE(usb_if, i), 0); - orion_write(USB_WIN_CTRL(usb_if, i), 0); - } - - /* - * Setup windows for DDR banks. - */ - for (i = 0; i < DDR_MAX_CS; i++) { - u32 base, size; - size = orion_read(DDR_SIZE_CS(i)); - base = orion_read(DDR_BASE_CS(i)); - if (size & DDR_BANK_EN) { - base = DDR_REG_TO_BASE(base); - size = DDR_REG_TO_SIZE(size); - orion_write(USB_WIN_CTRL(usb_if, i), - ((size-1) & 0xffff0000) | - (ATTR_DDR_CS(i) << 8) | - (TARGET_DDR << 4) | WIN_EN); - orion_write(USB_WIN_BASE(usb_if, i), - base & 0xffff0000); - } - } - } -} - void __init orion_setup_eth_wins(void) { int i; diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index cc16588e8c0..d33c01dfc3f 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "common.h" /***************************************************************************** @@ -149,6 +150,10 @@ static struct resource orion_ehci1_resources[] = { }, }; +static struct orion_ehci_data orion_ehci_data = { + .dram = &orion_mbus_dram_info, +}; + static u64 ehci_dmamask = 0xffffffffUL; static struct platform_device orion_ehci0 = { @@ -157,6 +162,7 @@ static struct platform_device orion_ehci0 = { .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, + .platform_data = &orion_ehci_data, }, .resource = orion_ehci0_resources, .num_resources = ARRAY_SIZE(orion_ehci0_resources), @@ -168,6 +174,7 @@ static struct platform_device orion_ehci1 = { .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, + .platform_data = &orion_ehci_data, }, .resource = orion_ehci1_resources, .num_resources = ARRAY_SIZE(orion_ehci1_resources), @@ -334,7 +341,6 @@ void __init orion_init(void) * Setup Orion address map */ orion_setup_cpu_wins(); - orion_setup_usb_wins(); orion_setup_eth_wins(); if (dev == MV88F5182_DEV_ID) orion_setup_sata_wins(); diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 961daaa0b91..c100355754f 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -33,7 +33,6 @@ extern struct mbus_dram_target_info orion_mbus_dram_info; void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); void orion_setup_cpu_wins(void); void orion_setup_eth_wins(void); -void orion_setup_usb_wins(void); void orion_setup_sata_wins(void); /* -- cgit From 15a32632d94011911497052a96cdbf3b905b325d Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: sata_mv: mbus decode window support Make it possible to pass mbus_dram_target_info to the sata_mv driver via the platform data, make the sata_mv driver program the window registers based on this data if it is passed in, and make the Orion platform setup code use this method instead of programming the SATA mbus window registers by hand. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 39 --------------------------------------- arch/arm/mach-orion/common.c | 4 ++-- arch/arm/mach-orion/common.h | 1 - 3 files changed, 2 insertions(+), 42 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 40bcb986ab9..3de5de9ac65 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -103,13 +103,6 @@ #define ETH_MAX_WIN 6 #define ETH_MAX_REMAP_WIN 4 -/* - * SATA Address Decode Windows registers - */ -#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10)) -#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) -#define SATA_MAX_WIN 4 - struct mbus_dram_target_info orion_mbus_dram_info; @@ -288,35 +281,3 @@ void __init orion_setup_eth_wins(void) } } } - -void __init orion_setup_sata_wins(void) -{ - int i; - - /* - * First, disable and clear windows - */ - for (i = 0; i < SATA_MAX_WIN; i++) { - orion_write(SATA_WIN_BASE(i), 0); - orion_write(SATA_WIN_CTRL(i), 0); - } - - /* - * Setup windows for DDR banks. - */ - for (i = 0; i < DDR_MAX_CS; i++) { - u32 base, size; - size = orion_read(DDR_SIZE_CS(i)); - base = orion_read(DDR_BASE_CS(i)); - if (size & DDR_BANK_EN) { - base = DDR_REG_TO_BASE(base); - size = DDR_REG_TO_SIZE(size); - orion_write(SATA_WIN_CTRL(i), - ((size-1) & 0xffff0000) | - (ATTR_DDR_CS(i) << 8) | - (TARGET_DDR << 4) | WIN_EN); - orion_write(SATA_WIN_BASE(i), - base & 0xffff0000); - } - } -} diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index d33c01dfc3f..a32fe8e108b 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -289,6 +290,7 @@ static struct platform_device orion_sata = { void __init orion_sata_init(struct mv_sata_platform_data *sata_data) { + sata_data->dram = &orion_mbus_dram_info; orion_sata.dev.platform_data = sata_data; platform_device_register(&orion_sata); } @@ -342,8 +344,6 @@ void __init orion_init(void) */ orion_setup_cpu_wins(); orion_setup_eth_wins(); - if (dev == MV88F5182_DEV_ID) - orion_setup_sata_wins(); /* * REgister devices diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index c100355754f..b676be0a4a8 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -33,7 +33,6 @@ extern struct mbus_dram_target_info orion_mbus_dram_info; void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); void orion_setup_cpu_wins(void); void orion_setup_eth_wins(void); -void orion_setup_sata_wins(void); /* * Shared code used internally by other Orion core functions. -- cgit From 69b02f6a9639af89c099d06d5f2c4c66a1b03ebf Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: plat-orion: introduce Create arch/arm/plat-orion/, for peripherals shared between various Marvell Orion SoCs. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/Kconfig | 4 ++++ arch/arm/Makefile | 1 + arch/arm/plat-orion/Makefile | 8 ++++++++ 3 files changed, 13 insertions(+) create mode 100644 arch/arm/plat-orion/Makefile (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4039a133006..845f96e9f0d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -384,6 +384,7 @@ config ARCH_ORION select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS + select PLAT_ORION help Support for Marvell Orion System on Chip family. @@ -563,6 +564,9 @@ config ARCH_ACORN config PLAT_IOP bool +config PLAT_ORION + bool + source arch/arm/mm/Kconfig config IWMMXT diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1a4649667ec..27866cf0c18 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -185,6 +185,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/ # If we have a common platform directory, then include it in the build. core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ +core-$(CONFIG_PLAT_ORION) += arch/arm/plat-orion/ core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/ diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile new file mode 100644 index 00000000000..2327762133f --- /dev/null +++ b/arch/arm/plat-orion/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +obj-y := +obj-m := +obj-n := +obj- := -- cgit From 01eb569823792ab83b2810fcb31fa38560b08951 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: plat-orion: share IRQ handling code Split off Orion IRQ handling code into plat-orion/, and add support for multiple sets of (32) interrupts. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/irq.c | 35 ++---------------------- arch/arm/plat-orion/Makefile | 2 +- arch/arm/plat-orion/irq.c | 64 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 34 deletions(-) create mode 100644 arch/arm/plat-orion/irq.c (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c index df7e12ad378..855793afcca 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion/irq.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "common.h" /***************************************************************************** @@ -197,41 +198,9 @@ static void __init orion_init_gpio_irq(void) /***************************************************************************** * Orion Main IRQ ****************************************************************************/ -static void orion_main_irq_mask(u32 irq) -{ - orion_clrbits(MAIN_IRQ_MASK, 1 << irq); -} - -static void orion_main_irq_unmask(u32 irq) -{ - orion_setbits(MAIN_IRQ_MASK, 1 << irq); -} - -static struct irq_chip orion_main_irq_chip = { - .name = "Orion-IRQ-Main", - .ack = orion_main_irq_mask, - .mask = orion_main_irq_mask, - .unmask = orion_main_irq_unmask, -}; - static void __init orion_init_main_irq(void) { - int i; - - /* - * Mask and clear Main IRQ interrupts - */ - orion_write(MAIN_IRQ_MASK, 0x0); - orion_write(MAIN_IRQ_CAUSE, 0x0); - - /* - * Register level handler for Main IRQs - */ - for (i = 0; i < IRQ_ORION_GPIO_START; i++) { - set_irq_chip(i, &orion_main_irq_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } + orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); } void __init orion_init_irq(void) diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index 2327762133f..ea4ce342a19 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := +obj-y := irq.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c new file mode 100644 index 00000000000..c5b669d234b --- /dev/null +++ b/arch/arm/plat-orion/irq.c @@ -0,0 +1,64 @@ +/* + * arch/arm/plat-orion/irq.c + * + * Marvell Orion SoC IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +static void orion_irq_mask(u32 irq) +{ + void __iomem *maskaddr = get_irq_chip_data(irq); + u32 mask; + + mask = readl(maskaddr); + mask &= ~(1 << (irq & 31)); + writel(mask, maskaddr); +} + +static void orion_irq_unmask(u32 irq) +{ + void __iomem *maskaddr = get_irq_chip_data(irq); + u32 mask; + + mask = readl(maskaddr); + mask |= 1 << (irq & 31); + writel(mask, maskaddr); +} + +static struct irq_chip orion_irq_chip = { + .name = "orion_irq", + .ack = orion_irq_mask, + .mask = orion_irq_mask, + .unmask = orion_irq_unmask, +}; + +void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) +{ + unsigned int i; + + /* + * Mask all interrupts initially. + */ + writel(0, maskaddr); + + /* + * Register IRQ sources. + */ + for (i = 0; i < 32; i++) { + unsigned int irq = irq_start + i; + + set_irq_chip(irq, &orion_irq_chip); + set_irq_chip_data(irq, maskaddr); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } +} -- cgit From abc0197d7a74e51a1581ce9971d7c2c0f2adadaf Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: plat-orion: share PCIe handling code Split off Orion PCIe handling code into plat-orion/. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/common.h | 4 +- arch/arm/mach-orion/pci.c | 343 +++++++++++-------------------------------- arch/arm/plat-orion/Makefile | 2 +- arch/arm/plat-orion/pcie.c | 245 +++++++++++++++++++++++++++++++ 4 files changed, 334 insertions(+), 260 deletions(-) create mode 100644 arch/arm/plat-orion/pcie.c (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index b676be0a4a8..9a5afefac4d 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -43,8 +43,8 @@ struct pci_sys_data; struct pci_bus; void orion_pcie_id(u32 *dev, u32 *rev); -u32 orion_pcie_local_bus_nr(void); -u32 orion_pci_local_bus_nr(void); +int orion_pcie_local_bus_nr(void); +int orion_pci_local_bus_nr(void); int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index cfd3d064c20..5240a245c7e 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "common.h" /***************************************************************************** @@ -32,288 +33,136 @@ /***************************************************************************** * PCIE controller ****************************************************************************/ -#define PCIE_CTRL ORION_PCIE_REG(0x1a00) -#define PCIE_STAT ORION_PCIE_REG(0x1a04) -#define PCIE_DEV_ID ORION_PCIE_REG(0x0000) -#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004) -#define PCIE_DEV_REV ORION_PCIE_REG(0x0008) -#define PCIE_MASK ORION_PCIE_REG(0x1910) -#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8) -#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc) - -/* - * PCIE_STAT bits - */ -#define PCIE_STAT_LINK_DOWN 1 -#define PCIE_STAT_BUS_OFFS 8 -#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS) -#define PCIE_STAT_DEV_OFFS 20 -#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS) - -/* - * PCIE_CONF_ADDR bits - */ -#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc)) -#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) -#define PCIE_CONF_ADDR_EN (1 << 31) - -/* - * PCIE Address Decode Windows registers - */ -#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) -#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) -#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) -#define PCIE_WIN_CTRL(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ - ORION_PCIE_REG(0x1880)) -#define PCIE_WIN_BASE(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ - ORION_PCIE_REG(0x1884)) -#define PCIE_WIN_REMAP(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x182c + ((n) << 4)) : \ - ORION_PCIE_REG(0x188c)) -#define PCIE_MAX_BARS 3 -#define PCIE_MAX_WINS 6 - -/* - * Use PCIE BAR '1' for all DDR banks - */ -#define PCIE_DRAM_BAR 1 - -/* - * PCIE config cycles are done by programming the PCIE_CONF_ADDR register - * and then reading the PCIE_CONF_DATA register. Need to make sure these - * transactions are atomic. - */ -static DEFINE_SPINLOCK(orion_pcie_lock); +#define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) void orion_pcie_id(u32 *dev, u32 *rev) { - *dev = orion_read(PCIE_DEV_ID) >> 16; - *rev = orion_read(PCIE_DEV_REV) & 0xff; -} - -u32 orion_pcie_local_bus_nr(void) -{ - u32 stat = orion_read(PCIE_STAT); - return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS); -} - -static u32 orion_pcie_local_dev_nr(void) -{ - u32 stat = orion_read(PCIE_STAT); - return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS); -} - -static u32 orion_pcie_no_link(void) -{ - u32 stat = orion_read(PCIE_STAT); - return(stat & PCIE_STAT_LINK_DOWN); -} - -static void orion_pcie_set_bus_nr(int nr) -{ - orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK); - orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS); + *dev = orion_pcie_dev_id(PCIE_BASE); + *rev = orion_pcie_rev(PCIE_BASE); } -/* - * Setup PCIE BARs and Address Decode Wins: - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks - * WIN[0-3] -> DRAM bank[0-3] - */ -static void orion_setup_pcie_wins(struct mbus_dram_target_info *dram) +int orion_pcie_local_bus_nr(void) { - u32 size; - int i; - - /* - * First, disable and clear BARs and windows - */ - for (i = 1; i < PCIE_MAX_BARS; i++) { - writel(0, PCIE_BAR_CTRL(i)); - writel(0, PCIE_BAR_LO(i)); - writel(0, PCIE_BAR_HI(i)); - } - - for (i = 0; i < PCIE_MAX_WINS; i++) { - writel(0, PCIE_WIN_CTRL(i)); - writel(0, PCIE_WIN_BASE(i)); - writel(0, PCIE_WIN_REMAP(i)); - } - - /* - * Setup windows for DDR banks. Count total DDR size on the fly. - */ - size = 0; - for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; - - writel(cs->base & 0xffff0000, PCIE_WIN_BASE(i)); - writel(0, PCIE_WIN_REMAP(i)); - writel(((cs->size - 1) & 0xffff0000) | - (cs->mbus_attr << 8) | - (dram->mbus_dram_target_id << 4) | - (PCIE_DRAM_BAR << 1) | 1, PCIE_WIN_CTRL(i)); - - size += cs->size; - } - - /* - * Setup BAR[1] to all DRAM banks - */ - writel(dram->cs[0].base, PCIE_BAR_LO(PCIE_DRAM_BAR)); - writel(0, PCIE_BAR_HI(PCIE_DRAM_BAR)); - writel(((size - 1) & 0xffff0000) | 1, PCIE_BAR_CTRL(PCIE_DRAM_BAR)); + return orion_pcie_get_local_bus_nr(PCIE_BASE); } -static void orion_pcie_master_slave_enable(void) -{ - orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER | - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY); -} - -static void orion_pcie_enable_interrupts(void) -{ - /* - * Enable interrupts lines - * INTA[24] INTB[25] INTC[26] INTD[27] - */ - orion_setbits(PCIE_MASK, 0xf<<24); -} - -static int orion_pcie_valid_config(u32 bus, u32 dev) +static int pcie_valid_config(int bus, int dev) { /* * Don't go out when trying to access -- - * 1. our own device + * 1. our own device / nonexisting device on local bus * 2. where there's no device connected (no link) - * 3. nonexisting devices on local bus */ - - if ((orion_pcie_local_bus_nr() == bus) && - (orion_pcie_local_dev_nr() == dev)) - return 0; - - if (orion_pcie_no_link()) + if (bus == 0 && dev != 1) return 0; - if (bus == orion_pcie_local_bus_nr()) - if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) || - ((orion_pcie_local_dev_nr() != 0) && (dev != 0))) + if (!orion_pcie_link_up(PCIE_BASE)) return 0; return 1; } -static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) + +/* + * PCIE config cycles are done by programming the PCIE_CONF_ADDR register + * and then reading the PCIE_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(orion_pcie_lock); + +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) { unsigned long flags; - unsigned int dev, rev, pcie_addr; + int ret; - if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } spin_lock_irqsave(&orion_pcie_lock, flags); + ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&orion_pcie_lock, flags); - orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); + return ret; +} - orion_pcie_id(&dev, &rev); - if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { - /* extended register space */ - pcie_addr = ORION_PCIE_WA_VIRT_BASE; - pcie_addr |= PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where); - *val = orion_read(pcie_addr); - } else - *val = orion_read(PCIE_CONF_DATA); +static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, + int where, int size, u32 *val) +{ + int ret; - if (size == 1) - *val = (*val >> (8*(where & 0x3))) & 0xff; - else if (size == 2) - *val = (*val >> (8*(where & 0x3))) & 0xffff; + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } - spin_unlock_irqrestore(&orion_pcie_lock, flags); + /* + * We only support access to the non-extended configuration + * space when using the WA access method (or we would have to + * sacrifice 256M of CPU virtual address space.) + */ + if (where >= 0x100) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } - return PCIBIOS_SUCCESSFUL; -} + ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE, + bus, devfn, where, size, val); + return ret; +} -static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 val) +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) { unsigned long flags; int ret; - if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) return PCIBIOS_DEVICE_NOT_FOUND; spin_lock_irqsave(&orion_pcie_lock, flags); - - ret = PCIBIOS_SUCCESSFUL; - - orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); - - if (size == 4) { - __raw_writel(val, PCIE_CONF_DATA); - } else if (size == 2) { - __raw_writew(val, PCIE_CONF_DATA + (where & 0x3)); - } else if (size == 1) { - __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3)); - } else { - ret = PCIBIOS_BAD_REGISTER_NUMBER; - } - + ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); spin_unlock_irqrestore(&orion_pcie_lock, flags); return ret; } -struct pci_ops orion_pcie_ops = { - .read = orion_pcie_rd_conf, - .write = orion_pcie_wr_conf, +struct pci_ops pcie_ops = { + .read = pcie_rd_conf, + .write = pcie_wr_conf, }; -static int orion_pcie_setup(struct pci_sys_data *sys) +static int pcie_setup(struct pci_sys_data *sys) { struct resource *res; + int dev; /* - * Point PCIe unit MBUS decode windows to DRAM space. - */ - orion_setup_pcie_wins(&orion_mbus_dram_info); - - /* - * Master + Slave enable + * Generic PCIe unit setup. */ - orion_pcie_master_slave_enable(); + orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info); /* - * Enable interrupts lines A-D + * Check whether to apply Orion-1/Orion-NAS PCIe config + * read transaction workaround. */ - orion_pcie_enable_interrupts(); + dev = orion_pcie_dev_id(PCIE_BASE); + if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { + printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " + "read transaction workaround\n"); + pcie_ops.read = pcie_rd_conf_wa; + } /* - * Request resource + * Request resources. */ res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); if (!res) - panic("orion_pci_setup unable to alloc resources"); + panic("pcie_setup unable to alloc resources"); /* * IORESOURCE_IO @@ -417,19 +266,19 @@ static int orion_pcie_setup(struct pci_sys_data *sys) */ static DEFINE_SPINLOCK(orion_pci_lock); -u32 orion_pci_local_bus_nr(void) +int orion_pci_local_bus_nr(void) { u32 conf = orion_read(PCI_P2P_CONF); return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } -static u32 orion_pci_local_dev_nr(void) +static int orion_pci_local_dev_nr(void) { u32 conf = orion_read(PCI_P2P_CONF); return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); } -static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, +static int orion_pci_hw_rd_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 *val) { unsigned long flags; @@ -451,7 +300,7 @@ static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, return PCIBIOS_SUCCESSFUL; } -static int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, +static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 val) { unsigned long flags; @@ -508,7 +357,7 @@ static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, PCI_FUNC(devfn), where, size, val); } -struct pci_ops orion_pci_ops = { +struct pci_ops pci_ops = { .read = orion_pci_rd_conf, .write = orion_pci_wr_conf, }; @@ -540,7 +389,8 @@ static void orion_pci_set_bus_nr(int nr) static void orion_pci_master_slave_enable(void) { - u32 bus_nr, dev_nr, func, reg, val; + int bus_nr, dev_nr, func, reg; + u32 val; bus_nr = orion_pci_local_bus_nr(); dev_nr = orion_pci_local_dev_nr(); @@ -554,8 +404,8 @@ static void orion_pci_master_slave_enable(void) static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) { u32 win_enable; - u32 bus; - u32 dev; + int bus; + int dev; int i; /* @@ -611,7 +461,7 @@ static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) orion_setbits(PCI_ADDR_DECODE_CTRL, 1); } -static int orion_pci_setup(struct pci_sys_data *sys) +static int pci_setup(struct pci_sys_data *sys) { struct resource *res; @@ -635,7 +485,7 @@ static int orion_pci_setup(struct pci_sys_data *sys) */ res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); if (!res) - panic("orion_pci_setup unable to alloc resources"); + panic("pci_setup unable to alloc resources"); /* * IORESOURCE_IO @@ -674,16 +524,11 @@ int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) int ret = 0; if (nr == 0) { - /* - * PCIE setup - */ - orion_pcie_set_bus_nr(0); - ret = orion_pcie_setup(sys); + orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); + ret = pcie_setup(sys); } else if (nr == 1) { - /* - * PCI setup - */ - ret = orion_pci_setup(sys); + orion_pci_set_bus_nr(sys->busnr); + ret = pci_setup(sys); } return ret; @@ -691,31 +536,15 @@ int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) { - struct pci_ops *ops; struct pci_bus *bus; - if (nr == 0) { - u32 pci_bus; - /* - * PCIE scan - */ - ops = &orion_pcie_ops; - bus = pci_scan_bus(sys->busnr, ops, sys); - /* - * Set local PCI bus number to follow PCIE bridges (if any) - */ - pci_bus = bus->number + bus->subordinate - bus->secondary + 1; - orion_pci_set_bus_nr(pci_bus); + bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); } else if (nr == 1) { - /* - * PCI scan - */ - ops = &orion_pci_ops; - bus = pci_scan_bus(sys->busnr, ops, sys); + bus = pci_scan_bus(sys->busnr, &pci_ops, sys); } else { - BUG(); bus = NULL; + BUG(); } return bus; diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index ea4ce342a19..b33ecb60183 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o +obj-y := irq.o pcie.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c new file mode 100644 index 00000000000..f01966a330e --- /dev/null +++ b/arch/arm/plat-orion/pcie.c @@ -0,0 +1,245 @@ +/* + * arch/arm/plat-orion/pcie.c + * + * Marvell Orion SoC PCIe handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +/* + * PCIe unit register offsets. + */ +#define PCIE_DEV_ID_OFF 0x0000 +#define PCIE_CMD_OFF 0x0004 +#define PCIE_DEV_REV_OFF 0x0008 +#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) +#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) +#define PCIE_HEADER_LOG_4_OFF 0x0128 +#define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4)) +#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) +#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) +#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) +#define PCIE_WIN5_CTRL_OFF 0x1880 +#define PCIE_WIN5_BASE_OFF 0x1884 +#define PCIE_WIN5_REMAP_OFF 0x188c +#define PCIE_CONF_ADDR_OFF 0x18f8 +#define PCIE_CONF_ADDR_EN 0x80000000 +#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) +#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) +#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) +#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) +#define PCIE_CONF_DATA_OFF 0x18fc +#define PCIE_MASK_OFF 0x1910 +#define PCIE_CTRL_OFF 0x1a00 +#define PCIE_STAT_OFF 0x1a04 +#define PCIE_STAT_DEV_OFFS 20 +#define PCIE_STAT_DEV_MASK 0x1f +#define PCIE_STAT_BUS_OFFS 8 +#define PCIE_STAT_BUS_MASK 0xff +#define PCIE_STAT_LINK_DOWN 1 + + +u32 __init orion_pcie_dev_id(void __iomem *base) +{ + return readl(base + PCIE_DEV_ID_OFF) >> 16; +} + +u32 __init orion_pcie_rev(void __iomem *base) +{ + return readl(base + PCIE_DEV_REV_OFF) & 0xff; +} + +int __init orion_pcie_link_up(void __iomem *base) +{ + return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); +} + +int __init orion_pcie_get_local_bus_nr(void __iomem *base) +{ + u32 stat = readl(base + PCIE_STAT_OFF); + + return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK; +} + +void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) +{ + u32 stat; + + stat = readl(base + PCIE_STAT_OFF); + stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS); + stat |= nr << PCIE_STAT_BUS_OFFS; + writel(stat, base + PCIE_STAT_OFF); +} + +/* + * Setup PCIE BARs and Address Decode Wins: + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks + * WIN[0-3] -> DRAM bank[0-3] + */ +static void __init orion_pcie_setup_wins(void __iomem *base, + struct mbus_dram_target_info *dram) +{ + u32 size; + int i; + + /* + * First, disable and clear BARs and windows. + */ + for (i = 1; i <= 2; i++) { + writel(0, base + PCIE_BAR_CTRL_OFF(i)); + writel(0, base + PCIE_BAR_LO_OFF(i)); + writel(0, base + PCIE_BAR_HI_OFF(i)); + } + + for (i = 0; i < 5; i++) { + writel(0, base + PCIE_WIN04_CTRL_OFF(i)); + writel(0, base + PCIE_WIN04_BASE_OFF(i)); + writel(0, base + PCIE_WIN04_REMAP_OFF(i)); + } + + writel(0, base + PCIE_WIN5_CTRL_OFF); + writel(0, base + PCIE_WIN5_BASE_OFF); + writel(0, base + PCIE_WIN5_REMAP_OFF); + + /* + * Setup windows for DDR banks. Count total DDR size on the fly. + */ + size = 0; + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + + writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); + writel(0, base + PCIE_WIN04_REMAP_OFF(i)); + writel(((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + base + PCIE_WIN04_CTRL_OFF(i)); + + size += cs->size; + } + + /* + * Setup BAR[1] to all DRAM banks. + */ + writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); + writel(0, base + PCIE_BAR_HI_OFF(1)); + writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); +} + +void __init orion_pcie_setup(void __iomem *base, + struct mbus_dram_target_info *dram) +{ + u16 cmd; + u32 mask; + + /* + * Point PCIe unit MBUS decode windows to DRAM space. + */ + orion_pcie_setup_wins(base, dram); + + /* + * Master + slave enable. + */ + cmd = readw(base + PCIE_CMD_OFF); + cmd |= PCI_COMMAND_IO; + cmd |= PCI_COMMAND_MEMORY; + cmd |= PCI_COMMAND_MASTER; + writew(cmd, base + PCIE_CMD_OFF); + + /* + * Enable interrupt lines A-D. + */ + mask = readl(base + PCIE_MASK_OFF); + mask |= 0x0f000000; + writel(mask, base + PCIE_MASK_OFF); +} + +int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val) +{ + writel(PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, + base + PCIE_CONF_ADDR_OFF); + + *val = readl(base + PCIE_CONF_DATA_OFF); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xffff; + + return PCIBIOS_SUCCESSFUL; +} + +int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val) +{ + writel(PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, + base + PCIE_CONF_ADDR_OFF); + + *val = readl(base + PCIE_CONF_DATA_OFF); + + if (bus->number != orion_pcie_get_local_bus_nr(base) || + PCI_FUNC(devfn) != 0) + *val = readl(base + PCIE_HEADER_LOG_4_OFF); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xffff; + + return PCIBIOS_SUCCESSFUL; +} + +int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val) +{ + *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where))); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xffff; + + return PCIBIOS_SUCCESSFUL; +} + +int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 val) +{ + int ret = PCIBIOS_SUCCESSFUL; + + writel(PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, + base + PCIE_CONF_ADDR_OFF); + + if (size == 4) { + writel(val, base + PCIE_CONF_DATA_OFF); + } else if (size == 2) { + writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); + } else if (size == 1) { + writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3)); + } else { + ret = PCIBIOS_BAD_REGISTER_NUMBER; + } + + return ret; +} -- cgit From 2bac1de2031aa4cad88a437d4410ec289da4f7dc Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: plat-orion: share time handling code Split off Orion time handling code into plat-orion/. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/Makefile | 2 +- arch/arm/mach-orion/common.c | 16 ++++ arch/arm/mach-orion/common.h | 6 +- arch/arm/mach-orion/time.c | 181 -------------------------------------- arch/arm/plat-orion/Makefile | 2 +- arch/arm/plat-orion/time.c | 203 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 222 insertions(+), 188 deletions(-) delete mode 100644 arch/arm/mach-orion/time.c create mode 100644 arch/arm/plat-orion/time.c (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion/Makefile index f91d937a73e..d894caa5060 100644 --- a/arch/arm/mach-orion/Makefile +++ b/arch/arm/mach-orion/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o +obj-y += common.o addr-map.o pci.o gpio.o irq.o obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index a32fe8e108b..86d7f7ccfae 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -23,8 +23,11 @@ #include #include #include +#include #include +#include #include +#include #include "common.h" /***************************************************************************** @@ -295,6 +298,19 @@ void __init orion_sata_init(struct mv_sata_platform_data *sata_data) platform_device_register(&orion_sata); } +/***************************************************************************** + * Time handling + ****************************************************************************/ + +static void orion_timer_init(void) +{ + orion_time_init(IRQ_ORION_BRIDGE, ORION_TCLK); +} + +struct sys_timer orion_timer = { + .init = orion_timer_init, +}; + /***************************************************************************** * General ****************************************************************************/ diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 9a5afefac4d..3898e1b78ee 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -8,6 +8,7 @@ void __init orion_map_io(void); void __init orion_init_irq(void); void __init orion_init(void); +extern struct sys_timer orion_timer; /* * Enumerations and functions for Orion windows mapping. Used by Orion core @@ -56,11 +57,6 @@ struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); void __init orion_gpio_set_valid_pins(u32 pins); void gpio_display(void); /* debug */ -/* - * Orion system timer (clocksource + clockevnt, /mach-orion/time.c) - */ -extern struct sys_timer orion_timer; - /* * Pull in Orion Ethernet platform_data, used by machine-setup */ diff --git a/arch/arm/mach-orion/time.c b/arch/arm/mach-orion/time.c deleted file mode 100644 index bd4262da4f4..00000000000 --- a/arch/arm/mach-orion/time.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * arch/arm/mach-orion/time.c - * - * Core time functions for Marvell Orion System On Chip - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include "common.h" - -/* - * Timer0: clock_event_device, Tick. - * Timer1: clocksource, Free running. - * WatchDog: Not used. - * - * Timers are counting down. - */ -#define CLOCKEVENT 0 -#define CLOCKSOURCE 1 - -/* - * Timers bits - */ -#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1)) -#define TIMER_EN(x) (1 << ((x) * 2)) -#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1)) -#define BRIDGE_INT_TIMER_WD (1 << 3) -#define TIMER_WD_EN (1 << 4) -#define TIMER_WD_RELOAD_EN (1 << 5) - -static cycle_t orion_clksrc_read(void) -{ - return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE))); -} - -static struct clocksource orion_clksrc = { - .name = "orion_clocksource", - .shift = 20, - .rating = 300, - .read = orion_clksrc_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int -orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) -{ - unsigned long flags; - - if (delta == 0) - return -ETIME; - - local_irq_save(flags); - - /* - * Clear and enable timer interrupt bit - */ - orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); - - /* - * Setup new timer value - */ - orion_write(TIMER_VAL(CLOCKEVENT), delta); - - /* - * Disable auto reload and kickoff the timer - */ - orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT)); - orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT)); - - local_irq_restore(flags); - - return 0; -} - -static void -orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) -{ - unsigned long flags; - - local_irq_save(flags); - - if (mode == CLOCK_EVT_MODE_PERIODIC) { - /* - * Setup latch cycles in timer and enable reload interrupt. - */ - orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH); - orion_write(TIMER_VAL(CLOCKEVENT), LATCH); - orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | - TIMER_EN(CLOCKEVENT)); - } else { - /* - * Disable timer and interrupt - */ - orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | - TIMER_EN(CLOCKEVENT)); - } - - local_irq_restore(flags); -} - -static struct clock_event_device orion_clkevt = { - .name = "orion_tick", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .rating = 300, - .cpumask = CPU_MASK_CPU0, - .set_next_event = orion_clkevt_next_event, - .set_mode = orion_clkevt_mode, -}; - -static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) -{ - /* - * Clear cause bit and do event - */ - orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_clkevt.event_handler(&orion_clkevt); - return IRQ_HANDLED; -} - -static struct irqaction orion_timer_irq = { - .name = "orion_tick", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = orion_timer_interrupt -}; - -static void orion_timer_init(void) -{ - /* - * Setup clocksource free running timer (no interrupt on reload) - */ - orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff); - orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff); - orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE)); - orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) | - TIMER_EN(CLOCKSOURCE)); - - /* - * Register clocksource - */ - orion_clksrc.mult = - clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift); - - clocksource_register(&orion_clksrc); - - /* - * Connect and enable tick handler - */ - setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq); - - /* - * Register clockevent - */ - orion_clkevt.mult = - div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift); - orion_clkevt.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &orion_clkevt); - orion_clkevt.min_delta_ns = - clockevent_delta2ns(1, &orion_clkevt); - - clockevents_register_device(&orion_clkevt); -} - -struct sys_timer orion_timer = { - .init = orion_timer_init, -}; diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index b33ecb60183..198f3dde2be 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o pcie.o +obj-y := irq.o pcie.o time.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c new file mode 100644 index 00000000000..28b5285446e --- /dev/null +++ b/arch/arm/plat-orion/time.c @@ -0,0 +1,203 @@ +/* + * arch/arm/plat-orion/time.c + * + * Marvell Orion SoC timer handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Timer 0 is used as free-running clocksource, while timer 1 is + * used as clock_event_device. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Number of timer ticks per jiffy. + */ +static u32 ticks_per_jiffy; + + +/* + * Timer block registers. + */ +#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) +#define TIMER0_EN 0x0001 +#define TIMER0_RELOAD_EN 0x0002 +#define TIMER1_EN 0x0004 +#define TIMER1_RELOAD_EN 0x0008 +#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010) +#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014) +#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018) +#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c) + + +/* + * Clocksource handling. + */ +static cycle_t orion_clksrc_read(void) +{ + return 0xffffffff - readl(TIMER0_VAL); +} + +static struct clocksource orion_clksrc = { + .name = "orion_clocksource", + .shift = 20, + .rating = 300, + .read = orion_clksrc_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + + + +/* + * Clockevent handling. + */ +static int +orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) +{ + unsigned long flags; + u32 u; + + if (delta == 0) + return -ETIME; + + local_irq_save(flags); + + /* + * Clear and enable clockevent timer interrupt. + */ + writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + + u = readl(BRIDGE_MASK); + u |= BRIDGE_INT_TIMER1; + writel(u, BRIDGE_MASK); + + /* + * Setup new clockevent timer value. + */ + writel(delta, TIMER1_VAL); + + /* + * Enable the timer. + */ + u = readl(TIMER_CTRL); + u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; + writel(u, TIMER_CTRL); + + local_irq_restore(flags); + + return 0; +} + +static void +orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) +{ + unsigned long flags; + u32 u; + + local_irq_save(flags); + if (mode == CLOCK_EVT_MODE_PERIODIC) { + /* + * Setup timer to fire at 1/HZ intervals. + */ + writel(ticks_per_jiffy - 1, TIMER1_RELOAD); + writel(ticks_per_jiffy - 1, TIMER1_VAL); + + /* + * Enable timer interrupt. + */ + u = readl(BRIDGE_MASK); + writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK); + + /* + * Enable timer. + */ + u = readl(TIMER_CTRL); + writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL); + } else { + /* + * Disable timer. + */ + u = readl(TIMER_CTRL); + writel(u & ~TIMER1_EN, TIMER_CTRL); + + /* + * Disable timer interrupt. + */ + u = readl(BRIDGE_MASK); + writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK); + + /* + * ACK pending timer interrupt. + */ + writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + + } + local_irq_restore(flags); +} + +static struct clock_event_device orion_clkevt = { + .name = "orion_tick", + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .shift = 32, + .rating = 300, + .cpumask = CPU_MASK_CPU0, + .set_next_event = orion_clkevt_next_event, + .set_mode = orion_clkevt_mode, +}; + +static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) +{ + /* + * ACK timer interrupt and call event handler. + */ + writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + orion_clkevt.event_handler(&orion_clkevt); + + return IRQ_HANDLED; +} + +static struct irqaction orion_timer_irq = { + .name = "orion_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = orion_timer_interrupt +}; + +void __init orion_time_init(unsigned int irq, unsigned int tclk) +{ + u32 u; + + ticks_per_jiffy = (tclk + HZ/2) / HZ; + + + /* + * Setup free-running clocksource timer (interrupts + * disabled.) + */ + writel(0xffffffff, TIMER0_VAL); + writel(0xffffffff, TIMER0_RELOAD); + u = readl(BRIDGE_MASK); + writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); + u = readl(TIMER_CTRL); + writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); + orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); + clocksource_register(&orion_clksrc); + + + /* + * Setup clockevent timer (interrupt-driven.) + */ + setup_irq(irq, &orion_timer_irq); + orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); + orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); + orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); + clockevents_register_device(&orion_clkevt); +} -- cgit From 705a752162768fed3e2c26fba5bffdd3a3bd04f2 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: plat-orion: make ehci-orion available for all Orion families Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/common.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index 86d7f7ccfae..1e124b7b0bd 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "common.h" -- cgit From 5d4294c524fc53746b5ec138d2e90f9d34d754b0 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: plat-orion: make orion_nand available for all Orion families Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/common.c | 2 +- arch/arm/mach-orion/db88f5281-setup.c | 2 +- arch/arm/mach-orion/dns323-setup.c | 1 - arch/arm/mach-orion/kurobox_pro-setup.c | 2 +- arch/arm/mach-orion/rd88f5182-setup.c | 1 - arch/arm/mach-orion/ts209-setup.c | 1 - 6 files changed, 3 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index 1e124b7b0bd..1b5ed72899e 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -26,8 +26,8 @@ #include #include #include -#include #include +#include #include #include "common.h" diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c index 5ef44e1a2d3..5cf65fedfae 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion/db88f5281-setup.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include "common.h" /***************************************************************************** diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c index 076e155ad51..38593784d76 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion/dns323-setup.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "common.h" #define DNS323_GPIO_LED_RIGHT_AMBER 1 diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c index 785a07bdf1e..feae4839830 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion/kurobox_pro-setup.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include "common.h" /***************************************************************************** diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c index e851b8ca5ac..e3cc757a4ca 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion/rd88f5182-setup.c @@ -25,7 +25,6 @@ #include #include #include -#include #include "common.h" /***************************************************************************** diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c index 45764dad16d..86583e4856a 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion/ts209-setup.c @@ -27,7 +27,6 @@ #include #include #include -#include #include "common.h" #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 -- cgit From 98f79d1ea0459b907f95846bad5e967a06b7a0d5 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: Orion: revamp cpu mbus window handling Instead of forcing all device bus window setup through one function with some enum as the first argument, create separate window setup functions for each of the four possible targets, and do the demux internally. This allows getting rid of the window identifier enum and the big switch statement in orion_setup_cpu_win(). Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 144 +++++++++++--------------------- arch/arm/mach-orion/common.c | 2 +- arch/arm/mach-orion/common.h | 23 ++--- arch/arm/mach-orion/db88f5281-setup.c | 13 ++- arch/arm/mach-orion/dns323-setup.c | 7 +- arch/arm/mach-orion/kurobox_pro-setup.c | 12 ++- arch/arm/mach-orion/rd88f5182-setup.c | 11 +-- arch/arm/mach-orion/ts209-setup.c | 8 +- 8 files changed, 76 insertions(+), 144 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 3de5de9ac65..ca641db6214 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -25,10 +25,10 @@ * CPU address decoding -- * Linux assumes that it is the boot loader that already setup the access to * DDR and internal registers. - * Setup access to PCI and PCI-E IO/MEM space is issued by core.c. + * Setup access to PCI and PCI-E IO/MEM space is issued by this file. * Setup access to various devices located on the device bus interface (e.g. * flashes, RTC, etc) should be issued by machine-setup.c according to - * specific board population (by using orion_setup_cpu_win()). + * specific board population (by using orion_setup_*_win()). * * Non-CPU Masters address decoding -- * Unlike the CPU, we setup the access from Orion's master interfaces to DDR @@ -53,6 +53,7 @@ ((n) == 3) ? 0x7 : 0xf) #define ATTR_PCIE_MEM 0x59 #define ATTR_PCIE_IO 0x51 +#define ATTR_PCIE_WA 0x79 #define ATTR_PCI_MEM 0x59 #define ATTR_PCI_IO 0x51 #define ATTR_DEV_CS0 0x1e @@ -78,19 +79,6 @@ #define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) #define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) #define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) -#define CPU_MAX_WIN 8 - -/* - * Use this CPU address decode windows allocation - */ -#define CPU_WIN_PCIE_IO 0 -#define CPU_WIN_PCI_IO 1 -#define CPU_WIN_PCIE_MEM 2 -#define CPU_WIN_PCI_MEM 3 -#define CPU_WIN_DEV_BOOT 4 -#define CPU_WIN_DEV_CS0 5 -#define CPU_WIN_DEV_CS1 6 -#define CPU_WIN_DEV_CS2 7 /* * Gigabit Ethernet Address Decode Windows registers @@ -106,7 +94,7 @@ struct mbus_dram_target_info orion_mbus_dram_info; -static int __init orion_cpu_win_can_remap(u32 win) +static int __init orion_cpu_win_can_remap(int win) { u32 dev, rev; @@ -119,88 +107,31 @@ static int __init orion_cpu_win_can_remap(u32 win) return 0; } -void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap) +static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) { - u32 win, attr, ctrl; - - switch (target) { - case ORION_PCIE_IO: - target = TARGET_PCIE; - attr = ATTR_PCIE_IO; - win = CPU_WIN_PCIE_IO; - break; - case ORION_PCI_IO: - target = TARGET_PCI; - attr = ATTR_PCI_IO; - win = CPU_WIN_PCI_IO; - break; - case ORION_PCIE_MEM: - target = TARGET_PCIE; - attr = ATTR_PCIE_MEM; - win = CPU_WIN_PCIE_MEM; - break; - case ORION_PCI_MEM: - target = TARGET_PCI; - attr = ATTR_PCI_MEM; - win = CPU_WIN_PCI_MEM; - break; - case ORION_DEV_BOOT: - target = TARGET_DEV_BUS; - attr = ATTR_DEV_BOOT; - win = CPU_WIN_DEV_BOOT; - break; - case ORION_DEV0: - target = TARGET_DEV_BUS; - attr = ATTR_DEV_CS0; - win = CPU_WIN_DEV_CS0; - break; - case ORION_DEV1: - target = TARGET_DEV_BUS; - attr = ATTR_DEV_CS1; - win = CPU_WIN_DEV_CS1; - break; - case ORION_DEV2: - target = TARGET_DEV_BUS; - attr = ATTR_DEV_CS2; - win = CPU_WIN_DEV_CS2; - break; - case ORION_DDR: - case ORION_REGS: - /* - * Must be mapped by bootloader. - */ - default: - target = attr = win = -1; - BUG(); - } - - base &= 0xffff0000; - ctrl = (((size - 1) & 0xffff0000) | (attr << 8) | - (target << 4) | WIN_EN); - - orion_write(CPU_WIN_BASE(win), base); - orion_write(CPU_WIN_CTRL(win), ctrl); + orion_write(CPU_WIN_BASE(win), base & 0xffff0000); + orion_write(CPU_WIN_CTRL(win), + ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); if (orion_cpu_win_can_remap(win)) { - if (remap >= 0) { - orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); - orion_write(CPU_WIN_REMAP_HI(win), 0); - } else { - orion_write(CPU_WIN_REMAP_LO(win), base); - orion_write(CPU_WIN_REMAP_HI(win), 0); - } + if (remap < 0) + remap = base; + + orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); + orion_write(CPU_WIN_REMAP_HI(win), 0); } } -void __init orion_setup_cpu_wins(void) +void __init orion_setup_cpu_mbus_bridge(void) { int i; int cs; /* - * First, disable and clear windows + * First, disable and clear windows. */ - for (i = 0; i < CPU_MAX_WIN; i++) { + for (i = 0; i < 8; i++) { orion_write(CPU_WIN_BASE(i), 0); orion_write(CPU_WIN_CTRL(i), 0); if (orion_cpu_win_can_remap(i)) { @@ -212,14 +143,14 @@ void __init orion_setup_cpu_wins(void) /* * Setup windows for PCI+PCIe IO+MEM space. */ - orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, - ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); - orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, - ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); - orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, - ORION_PCIE_MEM_SIZE, -1); - orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, - ORION_PCI_MEM_SIZE, -1); + setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE); + setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE, + TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE); + setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, -1); + setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE, + TARGET_PCI, ATTR_PCI_MEM, -1); /* * Setup MBUS dram target info. @@ -246,6 +177,31 @@ void __init orion_setup_cpu_wins(void) orion_mbus_dram_info.num_cs = cs; } +void __init orion_setup_dev_boot_win(u32 base, u32 size) +{ + setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); +} + +void __init orion_setup_dev0_win(u32 base, u32 size) +{ + setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); +} + +void __init orion_setup_dev1_win(u32 base, u32 size) +{ + setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); +} + +void __init orion_setup_dev2_win(u32 base, u32 size) +{ + setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); +} + +void __init orion_setup_pcie_wa_win(u32 base, u32 size) +{ + setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); +} + void __init orion_setup_eth_wins(void) { int i; diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index 1b5ed72899e..e271994d27f 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -359,7 +359,7 @@ void __init orion_init(void) /* * Setup Orion address map */ - orion_setup_cpu_wins(); + orion_setup_cpu_mbus_bridge(); orion_setup_eth_wins(); /* diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 3898e1b78ee..74f23e61c40 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -15,24 +15,13 @@ extern struct sys_timer orion_timer; * functions to map its interfaces and by the machine-setup to map its on- * board devices. Details in /mach-orion/addr-map.c */ - -enum orion_target { - ORION_DEV_BOOT = 0, - ORION_DEV0, - ORION_DEV1, - ORION_DEV2, - ORION_PCIE_MEM, - ORION_PCIE_IO, - ORION_PCI_MEM, - ORION_PCI_IO, - ORION_DDR, - ORION_REGS, - ORION_MAX_TARGETS -}; - extern struct mbus_dram_target_info orion_mbus_dram_info; -void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); -void orion_setup_cpu_wins(void); +void orion_setup_cpu_mbus_bridge(void); +void orion_setup_dev_boot_win(u32 base, u32 size); +void orion_setup_dev0_win(u32 base, u32 size); +void orion_setup_dev1_win(u32 base, u32 size); +void orion_setup_dev2_win(u32 base, u32 size); +void orion_setup_pcie_wa_win(u32 base, u32 size); void orion_setup_eth_wins(void); /* diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c index 5cf65fedfae..aad62efa1da 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion/db88f5281-setup.c @@ -317,14 +317,11 @@ static void __init db88f5281_init(void) /* * Setup the CPU address decode windows for our on-board devices */ - orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE, -1); - orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE, - DB88F5281_7SEG_SIZE, -1); - orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE, - DB88F5281_NOR_SIZE, -1); - orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE, - DB88F5281_NAND_SIZE, -1); + orion_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, + DB88F5281_NOR_BOOT_SIZE); + orion_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); + orion_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); + orion_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); /* * Setup Multiplexing Pins: diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c index 38593784d76..88991f76479 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion/dns323-setup.c @@ -251,16 +251,13 @@ static void __init dns323_init(void) /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 */ - orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE, - DNS323_NOR_BOOT_SIZE, -1); + orion_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE * * Open a special address decode windows for the PCIE WA. */ - orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); - orion_write(ORION_REGS_VIRT_BASE | 0x20070, - (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ orion_write(MPP_0_7_CTRL, 0); diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c index feae4839830..bf7034df8a6 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion/kurobox_pro-setup.c @@ -193,16 +193,14 @@ static void __init kurobox_pro_init(void) /* * Setup the CPU address decode windows for our devices */ - orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE, - KUROBOX_PRO_NOR_BOOT_SIZE, -1); - orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE, - KUROBOX_PRO_NAND_SIZE, -1); + orion_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, + KUROBOX_PRO_NOR_BOOT_SIZE); + orion_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); + /* * Open a special address decode windows for the PCIE WA. */ - orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); - orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | - (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c index e3cc757a4ca..662c097ca33 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion/rd88f5182-setup.c @@ -254,17 +254,14 @@ static void __init rd88f5182_init(void) /* * Setup the CPU address decode windows for our devices */ - orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE, -1); - orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE, - RD88F5182_NOR_SIZE, -1); + orion_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, + RD88F5182_NOR_BOOT_SIZE); + orion_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); - orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | - (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c index 86583e4856a..8eca070006f 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion/ts209-setup.c @@ -288,15 +288,13 @@ static void __init qnap_ts209_init(void) /* * Setup flash mapping */ - orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE, - QNAP_TS209_NOR_BOOT_SIZE, -1); + orion_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); - orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | - (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- -- cgit From b590bc5cd0ced1019f02ca7c9b8594482304987f Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: Orion: move I/O macros out of orion.h Move the Orion register accessor macros out of orion.h, to prevent them from ending up in the decompressor image (Orion uncompress.h includes orion.h.) Move them into io.h, which seems a better place for this kind of stuff. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 1 + arch/arm/mach-orion/gpio.c | 1 + arch/arm/mach-orion/irq.c | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index ca641db6214..ecca987b57e 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "common.h" /* diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c index f713818c66a..5a7d9cc9b80 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion/gpio.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "common.h" diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c index 855793afcca..dc8cb15a817 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion/irq.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include "common.h" -- cgit From a99842704a031ac23d4f7344e412a44bb3beb3b3 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: Orion: add __init attribute to all boot time-only functions Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/common.c | 2 +- arch/arm/mach-orion/pci.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index e271994d27f..aae157d360e 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -319,7 +319,7 @@ struct sys_timer orion_timer = { /* * Identify device ID and rev from PCIE configuration header space '0'. */ -static void orion_id(u32 *dev, u32 *rev, char **dev_name) +static void __init orion_id(u32 *dev, u32 *rev, char **dev_name) { orion_pcie_id(dev, rev); diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index 5240a245c7e..18cdf3b505a 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -35,7 +35,7 @@ ****************************************************************************/ #define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) -void orion_pcie_id(u32 *dev, u32 *rev) +void __init orion_pcie_id(u32 *dev, u32 *rev) { *dev = orion_pcie_dev_id(PCIE_BASE); *rev = orion_pcie_rev(PCIE_BASE); @@ -136,7 +136,7 @@ struct pci_ops pcie_ops = { }; -static int pcie_setup(struct pci_sys_data *sys) +static int __init pcie_setup(struct pci_sys_data *sys) { struct resource *res; int dev; @@ -362,7 +362,7 @@ struct pci_ops pci_ops = { .write = orion_pci_wr_conf, }; -static void orion_pci_set_bus_nr(int nr) +static void __init orion_pci_set_bus_nr(int nr) { u32 p2p = orion_read(PCI_P2P_CONF); @@ -387,7 +387,7 @@ static void orion_pci_set_bus_nr(int nr) } } -static void orion_pci_master_slave_enable(void) +static void __init orion_pci_master_slave_enable(void) { int bus_nr, dev_nr, func, reg; u32 val; @@ -401,7 +401,7 @@ static void orion_pci_master_slave_enable(void) orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); } -static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) +static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) { u32 win_enable; int bus; @@ -461,7 +461,7 @@ static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) orion_setbits(PCI_ADDR_DECODE_CTRL, 1); } -static int pci_setup(struct pci_sys_data *sys) +static int __init pci_setup(struct pci_sys_data *sys) { struct resource *res; @@ -519,7 +519,7 @@ static int pci_setup(struct pci_sys_data *sys) /***************************************************************************** * General PCIE + PCI ****************************************************************************/ -int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) +int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) { int ret = 0; @@ -534,7 +534,7 @@ int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) return ret; } -struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus __init *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; -- cgit From d50c60a87a95a42f1bc984150d3eebc77a0b0c14 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: Orion: enable access to local config space This patch enables access to the local PCIe/PCI configuration space, and is necessary for such things as PCI Advanced Error Recovery to work. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/pci.c | 58 +++++++++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 25 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index 18cdf3b505a..e3aab14b943 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -50,15 +50,18 @@ static int pcie_valid_config(int bus, int dev) { /* * Don't go out when trying to access -- - * 1. our own device / nonexisting device on local bus + * 1. nonexisting device on local bus * 2. where there's no device connected (no link) */ - if (bus == 0 && dev != 1) - return 0; + if (bus == 0 && dev == 0) + return 1; if (!orion_pcie_link_up(PCIE_BASE)) return 0; + if (bus == 0 && dev != 1) + return 0; + return 1; } @@ -272,12 +275,6 @@ int orion_pci_local_bus_nr(void) return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } -static int orion_pci_local_dev_nr(void) -{ - u32 conf = orion_read(PCI_P2P_CONF); - return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); -} - static int orion_pci_hw_rd_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 *val) { @@ -333,8 +330,8 @@ static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, /* * Don't go out for local device */ - if ((orion_pci_local_bus_nr() == bus->number) && - (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) { + if (bus->number == orion_pci_local_bus_nr() && + PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } @@ -346,11 +343,8 @@ static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - /* - * Don't go out for local device - */ - if ((orion_pci_local_bus_nr() == bus->number) && - (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) + if (bus->number == orion_pci_local_bus_nr() && + PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) return PCIBIOS_DEVICE_NOT_FOUND; return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), @@ -389,23 +383,21 @@ static void __init orion_pci_set_bus_nr(int nr) static void __init orion_pci_master_slave_enable(void) { - int bus_nr, dev_nr, func, reg; + int bus_nr, func, reg; u32 val; bus_nr = orion_pci_local_bus_nr(); - dev_nr = orion_pci_local_dev_nr(); func = PCI_CONF_FUNC_STAT_CMD; reg = PCI_CONF_REG_STAT_CMD; - orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val); + orion_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); + orion_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); } static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) { u32 win_enable; int bus; - int dev; int i; /* @@ -418,7 +410,6 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) * Setup windows for DDR banks. */ bus = orion_pci_local_bus_nr(); - dev = orion_pci_local_dev_nr(); for (i = 0; i < dram->num_cs; i++) { struct mbus_dram_window *cs = dram->cs + i; @@ -430,15 +421,15 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) * Write DRAM bank base address register. */ reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); - orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); + orion_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); val = (cs->base & 0xfffff000) | (val & 0xfff); - orion_pci_hw_wr_conf(bus, dev, func, reg, 4, val); + orion_pci_hw_wr_conf(bus, 0, func, reg, 4, val); /* * Write DRAM bank size register. */ reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); - orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); + orion_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), (cs->size - 1) & 0xfffff000); orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), @@ -519,6 +510,23 @@ static int __init pci_setup(struct pci_sys_data *sys) /***************************************************************************** * General PCIE + PCI ****************************************************************************/ +static void __devinit rc_pci_fixup(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root complex. + */ + if (dev->bus->parent == NULL && dev->devfn == 0) { + int i; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); + int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) { int ret = 0; -- cgit From 159ffb3a04f6bc619643af680df406faafd0199d Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: Orion: general cleanup Various Orion cleanups: - Unify GPL license banner format across all files. - Unify naming of .h double inclusion guard preprocessor macros. - Unify spelling of "PCIe" (variants seen: PCIE, PCIe, PCI-EX.) - Various typo fixes. - Remove __init attributes from prototypes declared in headers. - Remove trailing comments from #endif statements. - Mark a couple of locally-used-only structs static. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 8 ++++---- arch/arm/mach-orion/common.c | 6 +++--- arch/arm/mach-orion/common.h | 19 ++++++++++--------- arch/arm/mach-orion/db88f5281-setup.c | 4 ++-- arch/arm/mach-orion/gpio.c | 4 ++-- arch/arm/mach-orion/irq.c | 2 +- arch/arm/mach-orion/kurobox_pro-setup.c | 4 ++-- arch/arm/mach-orion/pci.c | 32 ++++++++++++++++---------------- arch/arm/mach-orion/rd88f5182-setup.c | 4 ++-- 9 files changed, 42 insertions(+), 41 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index ecca987b57e..738de617e3c 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -5,8 +5,8 @@ * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -45,9 +45,9 @@ * Generic Address Decode Windows bit settings */ #define TARGET_DDR 0 +#define TARGET_DEV_BUS 1 #define TARGET_PCI 3 #define TARGET_PCIE 4 -#define TARGET_DEV_BUS 1 #define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ ((n) == 1) ? 0xd : \ ((n) == 2) ? 0xb : \ @@ -64,7 +64,7 @@ #define WIN_EN 1 /* - * Helpers to get DDR banks info + * Helpers to get DDR bank info */ #define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) #define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index aae157d360e..85c8f18268a 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -5,8 +5,8 @@ * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -363,7 +363,7 @@ void __init orion_init(void) orion_setup_eth_wins(); /* - * REgister devices + * Register devices. */ platform_device_register(&orion_uart); platform_device_register(&orion_ehci0); diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 74f23e61c40..bcc31adaca1 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -1,13 +1,13 @@ -#ifndef __ARCH_ORION_COMMON_H__ -#define __ARCH_ORION_COMMON_H__ +#ifndef __ARCH_ORION_COMMON_H +#define __ARCH_ORION_COMMON_H /* * Basic Orion init functions used early by machine-setup. */ -void __init orion_map_io(void); -void __init orion_init_irq(void); -void __init orion_init(void); +void orion_map_io(void); +void orion_init_irq(void); +void orion_init(void); extern struct sys_timer orion_timer; /* @@ -43,7 +43,7 @@ struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); * (/mach-orion/gpio.c). */ -void __init orion_gpio_set_valid_pins(u32 pins); +void orion_gpio_set_valid_pins(u32 pins); void gpio_display(void); /* debug */ /* @@ -52,7 +52,7 @@ void gpio_display(void); /* debug */ struct mv643xx_eth_platform_data; -void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); +void orion_eth_init(struct mv643xx_eth_platform_data *eth_data); /* * Orion Sata platform_data, used by machine-setup @@ -60,7 +60,7 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); struct mv_sata_platform_data; -void __init orion_sata_init(struct mv_sata_platform_data *sata_data); +void orion_sata_init(struct mv_sata_platform_data *sata_data); struct machine_desc; struct meminfo; @@ -68,4 +68,5 @@ struct tag; extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, char **, struct meminfo *); -#endif /* __ARCH_ORION_COMMON_H__ */ + +#endif diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c index aad62efa1da..a0a9e4851b5 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion/db88f5281-setup.c @@ -5,8 +5,8 @@ * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c index 5a7d9cc9b80..afc7be08b30 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion/gpio.c @@ -5,8 +5,8 @@ * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c index dc8cb15a817..7033cc1360e 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion/irq.c @@ -6,7 +6,7 @@ * Maintainer: Tzachi Perelstein * * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c index bf7034df8a6..be417e7f423 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion/kurobox_pro-setup.c @@ -3,8 +3,8 @@ * * Maintainer: Ronen Shitrit * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index e3aab14b943..59684cc329b 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -1,12 +1,12 @@ /* * arch/arm/mach-orion/pci.c * - * PCI and PCIE functions for Marvell Orion System On Chip + * PCI and PCIe functions for Marvell Orion System On Chip * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -18,12 +18,12 @@ #include "common.h" /***************************************************************************** - * Orion has one PCIE controller and one PCI controller. + * Orion has one PCIe controller and one PCI controller. * - * Note1: The local PCIE bus number is '0'. The local PCI bus number - * follows the scanned PCIE bridged busses, if any. + * Note1: The local PCIe bus number is '0'. The local PCI bus number + * follows the scanned PCIe bridged busses, if any. * - * Note2: It is possible for PCI/PCIE agents to access many subsystem's + * Note2: It is possible for PCI/PCIe agents to access many subsystem's * space, by configuring BARs and Address Decode Windows, e.g. flashes on * device bus, Orion registers, etc. However this code only enable the * access to DDR banks. @@ -31,7 +31,7 @@ /***************************************************************************** - * PCIE controller + * PCIe controller ****************************************************************************/ #define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) @@ -67,7 +67,7 @@ static int pcie_valid_config(int bus, int dev) /* - * PCIE config cycles are done by programming the PCIE_CONF_ADDR register + * PCIe config cycles are done by programming the PCIE_CONF_ADDR register * and then reading the PCIE_CONF_DATA register. Need to make sure these * transactions are atomic. */ @@ -133,7 +133,7 @@ static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, return ret; } -struct pci_ops pcie_ops = { +static struct pci_ops pcie_ops = { .read = pcie_rd_conf, .write = pcie_wr_conf, }; @@ -170,23 +170,23 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * IORESOURCE_IO */ - res[0].name = "PCI-EX I/O Space"; + res[0].name = "PCIe I/O Space"; res[0].flags = IORESOURCE_IO; res[0].start = ORION_PCIE_IO_BUS_BASE; res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; if (request_resource(&ioport_resource, &res[0])) - panic("Request PCIE IO resource failed\n"); + panic("Request PCIe IO resource failed\n"); sys->resource[0] = &res[0]; /* * IORESOURCE_MEM */ - res[1].name = "PCI-EX Memory Space"; + res[1].name = "PCIe Memory Space"; res[1].flags = IORESOURCE_MEM; res[1].start = ORION_PCIE_MEM_PHYS_BASE; res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; if (request_resource(&iomem_resource, &res[1])) - panic("Request PCIE Memory resource failed\n"); + panic("Request PCIe Memory resource failed\n"); sys->resource[1] = &res[1]; sys->resource[2] = NULL; @@ -351,7 +351,7 @@ static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, PCI_FUNC(devfn), where, size, val); } -struct pci_ops pci_ops = { +static struct pci_ops pci_ops = { .read = orion_pci_rd_conf, .write = orion_pci_wr_conf, }; @@ -508,7 +508,7 @@ static int __init pci_setup(struct pci_sys_data *sys) /***************************************************************************** - * General PCIE + PCI + * General PCIe + PCI ****************************************************************************/ static void __devinit rc_pci_fixup(struct pci_dev *dev) { diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c index 662c097ca33..f3e38ecda1c 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion/rd88f5182-setup.c @@ -5,8 +5,8 @@ * * Maintainer: Ronen Shitrit * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -- cgit From 9dd0b194bf6804b1998f0fe261b2606ec7b58d72 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: Orion: orion -> orion5x rename Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e. not the plat-orion bits.) Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Saeed Bishara Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/Kconfig | 7 +- arch/arm/Makefile | 2 +- arch/arm/configs/orion5x_defconfig | 1383 +++++++++++++++++++++++++++++ arch/arm/configs/orion_defconfig | 1383 ----------------------------- arch/arm/mach-orion/Kconfig | 41 - arch/arm/mach-orion/Makefile | 6 - arch/arm/mach-orion/Makefile.boot | 3 - arch/arm/mach-orion/addr-map.c | 240 ----- arch/arm/mach-orion/common.c | 391 -------- arch/arm/mach-orion/common.h | 72 -- arch/arm/mach-orion/db88f5281-setup.c | 361 -------- arch/arm/mach-orion/dns323-setup.c | 319 ------- arch/arm/mach-orion/gpio.c | 226 ----- arch/arm/mach-orion/irq.c | 211 ----- arch/arm/mach-orion/kurobox_pro-setup.c | 242 ----- arch/arm/mach-orion/pci.c | 559 ------------ arch/arm/mach-orion/rd88f5182-setup.c | 311 ------- arch/arm/mach-orion/ts209-setup.c | 358 -------- arch/arm/mach-orion5x/Kconfig | 41 + arch/arm/mach-orion5x/Makefile | 6 + arch/arm/mach-orion5x/Makefile.boot | 3 + arch/arm/mach-orion5x/addr-map.c | 240 +++++ arch/arm/mach-orion5x/common.c | 391 ++++++++ arch/arm/mach-orion5x/common.h | 72 ++ arch/arm/mach-orion5x/db88f5281-setup.c | 361 ++++++++ arch/arm/mach-orion5x/dns323-setup.c | 320 +++++++ arch/arm/mach-orion5x/gpio.c | 226 +++++ arch/arm/mach-orion5x/irq.c | 211 +++++ arch/arm/mach-orion5x/kurobox_pro-setup.c | 243 +++++ arch/arm/mach-orion5x/pci.c | 559 ++++++++++++ arch/arm/mach-orion5x/rd88f5182-setup.c | 312 +++++++ arch/arm/mach-orion5x/ts209-setup.c | 359 ++++++++ arch/arm/mm/Kconfig | 2 +- 33 files changed, 4733 insertions(+), 4728 deletions(-) create mode 100644 arch/arm/configs/orion5x_defconfig delete mode 100644 arch/arm/configs/orion_defconfig delete mode 100644 arch/arm/mach-orion/Kconfig delete mode 100644 arch/arm/mach-orion/Makefile delete mode 100644 arch/arm/mach-orion/Makefile.boot delete mode 100644 arch/arm/mach-orion/addr-map.c delete mode 100644 arch/arm/mach-orion/common.c delete mode 100644 arch/arm/mach-orion/common.h delete mode 100644 arch/arm/mach-orion/db88f5281-setup.c delete mode 100644 arch/arm/mach-orion/dns323-setup.c delete mode 100644 arch/arm/mach-orion/gpio.c delete mode 100644 arch/arm/mach-orion/irq.c delete mode 100644 arch/arm/mach-orion/kurobox_pro-setup.c delete mode 100644 arch/arm/mach-orion/pci.c delete mode 100644 arch/arm/mach-orion/rd88f5182-setup.c delete mode 100644 arch/arm/mach-orion/ts209-setup.c create mode 100644 arch/arm/mach-orion5x/Kconfig create mode 100644 arch/arm/mach-orion5x/Makefile create mode 100644 arch/arm/mach-orion5x/Makefile.boot create mode 100644 arch/arm/mach-orion5x/addr-map.c create mode 100644 arch/arm/mach-orion5x/common.c create mode 100644 arch/arm/mach-orion5x/common.h create mode 100644 arch/arm/mach-orion5x/db88f5281-setup.c create mode 100644 arch/arm/mach-orion5x/dns323-setup.c create mode 100644 arch/arm/mach-orion5x/gpio.c create mode 100644 arch/arm/mach-orion5x/irq.c create mode 100644 arch/arm/mach-orion5x/kurobox_pro-setup.c create mode 100644 arch/arm/mach-orion5x/pci.c create mode 100644 arch/arm/mach-orion5x/rd88f5182-setup.c create mode 100644 arch/arm/mach-orion5x/ts209-setup.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 845f96e9f0d..2f4fb773f3e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -377,7 +377,7 @@ config ARCH_MXC help Support for Freescale MXC/iMX-based family of processors -config ARCH_ORION +config ARCH_ORION5X bool "Marvell Orion" depends on MMU select PCI @@ -386,7 +386,8 @@ config ARCH_ORION select GENERIC_CLOCKEVENTS select PLAT_ORION help - Support for Marvell Orion System on Chip family. + Support for the following Marvell Orion 5x series SoCs: + Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" @@ -517,7 +518,7 @@ source "arch/arm/mach-omap1/Kconfig" source "arch/arm/mach-omap2/Kconfig" -source "arch/arm/mach-orion/Kconfig" +source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 27866cf0c18..6f997505375 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -139,7 +139,7 @@ endif machine-$(CONFIG_ARCH_KS8695) := ks8695 incdir-$(CONFIG_ARCH_MXC) := mxc machine-$(CONFIG_ARCH_MX3) := mx3 - machine-$(CONFIG_ARCH_ORION) := orion + machine-$(CONFIG_ARCH_ORION5X) := orion5x machine-$(CONFIG_ARCH_MSM7X00A) := msm ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig new file mode 100644 index 00000000000..52cd99bd52f --- /dev/null +++ b/arch/arm/configs/orion5x_defconfig @@ -0,0 +1,1383 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24 +# Thu Feb 7 14:10:30 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +# CONFIG_PREEMPT_RCU is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +CONFIG_ARCH_ORION5X=y +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM7X00A is not set + +# +# Orion Implementations +# +CONFIG_MACH_DB88F5281=y +CONFIG_MACH_RD88F5182=y +CONFIG_MACH_KUROBOX_PRO=y +CONFIG_MACH_DNS323=y +CONFIG_MACH_TS209=y + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_FEROCEON=y +CONFIG_CPU_FEROCEON_OLD_ID=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_LEDS=y +CONFIG_LEDS_CPU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_ATAGS_PROC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +CONFIG_NFTL=y +# CONFIG_NFTL_RW is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0 +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_ORION=y +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +CONFIG_SATA_MV=y +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000E is not set +# CONFIG_E1000E_ENABLED is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +CONFIG_SKGE=y +CONFIG_SKY2=y +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_TIGON3=y +# CONFIG_BNX2 is not set +CONFIG_MV643XX_ETH=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +CONFIG_I2C_MV64XXX=y + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_GPIO is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_RS5C372=y +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +CONFIG_RTC_DRV_M41T80=y +# CONFIG_RTC_DRV_M41T80_WDT is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_FRAME_POINTER=y +# CONFIG_SAMPLES is not set +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +# CONFIG_CRYPTO_SEQIV is not set +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion_defconfig deleted file mode 100644 index 1e5aaa645fc..00000000000 --- a/arch/arm/configs/orion_defconfig +++ /dev/null @@ -1,1383 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.24 -# Thu Feb 7 14:10:30 2008 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_FAIR_USER_SCHED=y -# CONFIG_FAIR_CGROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -# CONFIG_RELAY is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_COMPAT_BRK=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_ANON_INODES=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set -# CONFIG_BLK_DEV_BSG is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_CLASSIC_RCU=y -# CONFIG_PREEMPT_RCU is not set - -# -# System Type -# -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_MXC is not set -CONFIG_ARCH_ORION=y -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM7X00A is not set - -# -# Orion Implementations -# -CONFIG_MACH_DB88F5281=y -CONFIG_MACH_RD88F5182=y -CONFIG_MACH_KUROBOX_PRO=y -CONFIG_MACH_DNS323=y -CONFIG_MACH_TS209=y - -# -# Boot options -# - -# -# Power management -# - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_FEROCEON=y -CONFIG_CPU_FEROCEON_OLD_ID=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_OUTER_CACHE is not set - -# -# Bus support -# -CONFIG_PCI=y -CONFIG_PCI_SYSCALL=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_PCI_LEGACY=y -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_PREEMPT=y -CONFIG_HZ=100 -CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y -CONFIG_VIRT_TO_BUS=y -CONFIG_LEDS=y -CONFIG_LEDS_CPU=y -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set -# CONFIG_ATAGS_PROC is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -# CONFIG_FPE_FASTFPE is not set -CONFIG_VFP=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -# CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -CONFIG_NET_PKTGEN=m -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -CONFIG_FTL=y -CONFIG_NFTL=y -# CONFIG_NFTL_RW is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -CONFIG_MTD_CFI_I4=y -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0x0 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_BANKWIDTH=0 -# CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_IMPA7 is not set -# CONFIG_MTD_INTEL_VR_NOR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_CAFE is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -CONFIG_MTD_NAND_ORION=y -# CONFIG_MTD_ONENAND is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_UB is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -CONFIG_MISC_DEVICES=y -# CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_PROC_FS is not set - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=m -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_CHR_DEV_SG=m -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_AIC94XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_STEX is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_SRP is not set -CONFIG_ATA=y -# CONFIG_ATA_NONSTANDARD is not set -# CONFIG_SATA_AHCI is not set -# CONFIG_SATA_SVW is not set -# CONFIG_ATA_PIIX is not set -CONFIG_SATA_MV=y -# CONFIG_SATA_NV is not set -# CONFIG_PDC_ADMA is not set -# CONFIG_SATA_QSTOR is not set -# CONFIG_SATA_PROMISE is not set -# CONFIG_SATA_SX4 is not set -# CONFIG_SATA_SIL is not set -# CONFIG_SATA_SIL24 is not set -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set -# CONFIG_SATA_INIC162X is not set -# CONFIG_PATA_ALI is not set -# CONFIG_PATA_AMD is not set -# CONFIG_PATA_ARTOP is not set -# CONFIG_PATA_ATIIXP is not set -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CS5520 is not set -# CONFIG_PATA_CS5530 is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_ATA_GENERIC is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_OLDPIIX is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_NS87415 is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_OPTIDMA is not set -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RZ1000 is not set -# CONFIG_PATA_SC1200 is not set -# CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set -# CONFIG_PATA_PLATFORM is not set -# CONFIG_MD is not set -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_FIREWIRE is not set -# CONFIG_IEEE1394 is not set -# CONFIG_I2O is not set -CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_ARCNET is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_EEPRO100 is not set -CONFIG_E100=y -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_R6040 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_SC92031 is not set -CONFIG_NETDEV_1000=y -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -CONFIG_E1000=y -CONFIG_E1000_NAPI=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set -# CONFIG_E1000E is not set -# CONFIG_E1000E_ENABLED is not set -# CONFIG_IP1000 is not set -# CONFIG_IGB is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -CONFIG_SKGE=y -CONFIG_SKY2=y -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -CONFIG_TIGON3=y -# CONFIG_BNX2 is not set -CONFIG_MV643XX_ETH=y -# CONFIG_QLA3XXX is not set -# CONFIG_ATL1 is not set -CONFIG_NETDEV_10000=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_IXGBE is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_NIU is not set -# CONFIG_MLX4_CORE is not set -# CONFIG_TEHUTI is not set -# CONFIG_BNX2X is not set -# CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_NOZOMI is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=16 -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=m -# CONFIG_NVRAM is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_DEVPORT=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y - -# -# I2C Algorithms -# -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# -# I2C Hardware Bus support -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TINY_USB is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_VOODOO3 is not set -CONFIG_I2C_MV64XXX=y - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_TPS65010 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_I5K_AMB is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set -# CONFIG_WATCHDOG is not set - -# -# Sonics Silicon Backplane -# -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -CONFIG_DAB=y -# CONFIG_USB_DABUSB is not set - -# -# Graphics support -# -# CONFIG_DRM is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set -# CONFIG_USB_HIDDEV is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set - -# -# USB Host Controller Drivers -# -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_UHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -CONFIG_USB_PRINTER=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# may also be needed; see USB_STORAGE Help for more information -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -CONFIG_USB_STORAGE_DATAFAB=y -CONFIG_USB_STORAGE_FREECOM=y -# CONFIG_USB_STORAGE_ISD200 is not set -CONFIG_USB_STORAGE_DPCM=y -# CONFIG_USB_STORAGE_USBAT is not set -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_JUMPSHOT=y -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_GADGET is not set -# CONFIG_MMC is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -# CONFIG_LEDS_GPIO is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_DRV_DS1307=y -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -CONFIG_RTC_DRV_RS5C372=y -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -CONFIG_RTC_DRV_M41T80=y -# CONFIG_RTC_DRV_M41T80_WDT is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_ZISOFS is not set -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -CONFIG_CRAMFS=y -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_SUNRPC_BIND34 is not set -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_LDM_DEBUG=y -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -CONFIG_SUN_PARTITION=y -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=y -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_FRAME_POINTER=y -# CONFIG_SAMPLES is not set -CONFIG_DEBUG_USER=y - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=m -CONFIG_CRYPTO_BLKCIPHER=m -# CONFIG_CRYPTO_SEQIV is not set -CONFIG_CRYPTO_MANAGER=m -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_GF128MUL is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_LZO is not set -CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_DEV_HIFN_795X is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion/Kconfig deleted file mode 100644 index 1dcbb6ac5a3..00000000000 --- a/arch/arm/mach-orion/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -if ARCH_ORION - -menu "Orion Implementations" - -config MACH_DB88F5281 - bool "Marvell Orion-2 Development Board" - select I2C_BOARDINFO - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-2 (88F5281) Development Board - -config MACH_RD88F5182 - bool "Marvell Orion-NAS Reference Design" - select I2C_BOARDINFO - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-NAS (88F5182) RD2 - -config MACH_KUROBOX_PRO - bool "KuroBox Pro" - select I2C_BOARDINFO - help - Say 'Y' here if you want your kernel to support the - KuroBox Pro platform. - -config MACH_DNS323 - bool "D-Link DNS-323" - select I2C_BOARDINFO - help - Say 'Y' here if you want your kernel to support the - D-Link DNS-323 platform. - -config MACH_TS209 - bool "QNAP TS-109/TS-209" - help - Say 'Y' here if you want your kernel to support the - QNAP TS-109/TS-209 platform. - -endmenu - -endif diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion/Makefile deleted file mode 100644 index d894caa5060..00000000000 --- a/arch/arm/mach-orion/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -obj-y += common.o addr-map.o pci.o gpio.o irq.o -obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o -obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o -obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o -obj-$(CONFIG_MACH_DNS323) += dns323-setup.o -obj-$(CONFIG_MACH_TS209) += ts209-setup.o diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion/Makefile.boot deleted file mode 100644 index 67039c3e0c4..00000000000 --- a/arch/arm/mach-orion/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c deleted file mode 100644 index 738de617e3c..00000000000 --- a/arch/arm/mach-orion/addr-map.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * arch/arm/mach-orion/addr-map.c - * - * Address map functions for Marvell Orion System On Chip - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "common.h" - -/* - * The Orion has fully programable address map. There's a separate address - * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, - * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own - * address decode windows that allow it to access any of the Orion resources. - * - * CPU address decoding -- - * Linux assumes that it is the boot loader that already setup the access to - * DDR and internal registers. - * Setup access to PCI and PCI-E IO/MEM space is issued by this file. - * Setup access to various devices located on the device bus interface (e.g. - * flashes, RTC, etc) should be issued by machine-setup.c according to - * specific board population (by using orion_setup_*_win()). - * - * Non-CPU Masters address decoding -- - * Unlike the CPU, we setup the access from Orion's master interfaces to DDR - * banks only (the typical use case). - * Setup access for each master to DDR is issued by common.c. - * - * Note: although orion_setbits() and orion_clrbits() are not atomic - * no locking is necessary here since code in this file is only called - * at boot time when there is no concurrency issues. - */ - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DDR 0 -#define TARGET_DEV_BUS 1 -#define TARGET_PCI 3 -#define TARGET_PCIE 4 -#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ - ((n) == 1) ? 0xd : \ - ((n) == 2) ? 0xb : \ - ((n) == 3) ? 0x7 : 0xf) -#define ATTR_PCIE_MEM 0x59 -#define ATTR_PCIE_IO 0x51 -#define ATTR_PCIE_WA 0x79 -#define ATTR_PCI_MEM 0x59 -#define ATTR_PCI_IO 0x51 -#define ATTR_DEV_CS0 0x1e -#define ATTR_DEV_CS1 0x1d -#define ATTR_DEV_CS2 0x1b -#define ATTR_DEV_BOOT 0xf -#define WIN_EN 1 - -/* - * Helpers to get DDR bank info - */ -#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) -#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) -#define DDR_MAX_CS 4 -#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) -#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) -#define DDR_BANK_EN 1 - -/* - * CPU Address Decode Windows registers - */ -#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4)) -#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) -#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) -#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) - -/* - * Gigabit Ethernet Address Decode Windows registers - */ -#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8)) -#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8)) -#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4)) -#define ETH_WIN_EN ORION_ETH_REG(0x290) -#define ETH_WIN_PROT ORION_ETH_REG(0x294) -#define ETH_MAX_WIN 6 -#define ETH_MAX_REMAP_WIN 4 - - -struct mbus_dram_target_info orion_mbus_dram_info; - -static int __init orion_cpu_win_can_remap(int win) -{ - u32 dev, rev; - - orion_pcie_id(&dev, &rev); - if ((dev == MV88F5281_DEV_ID && win < 4) - || (dev == MV88F5182_DEV_ID && win < 2) - || (dev == MV88F5181_DEV_ID && win < 2)) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - orion_write(CPU_WIN_BASE(win), base & 0xffff0000); - orion_write(CPU_WIN_CTRL(win), - ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); - - if (orion_cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); - orion_write(CPU_WIN_REMAP_HI(win), 0); - } -} - -void __init orion_setup_cpu_mbus_bridge(void) -{ - int i; - int cs; - - /* - * First, disable and clear windows. - */ - for (i = 0; i < 8; i++) { - orion_write(CPU_WIN_BASE(i), 0); - orion_write(CPU_WIN_CTRL(i), 0); - if (orion_cpu_win_can_remap(i)) { - orion_write(CPU_WIN_REMAP_LO(i), 0); - orion_write(CPU_WIN_REMAP_HI(i), 0); - } - } - - /* - * Setup windows for PCI+PCIe IO+MEM space. - */ - setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE); - setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE, - TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE); - setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE, - TARGET_PCI, ATTR_PCI_MEM, -1); - - /* - * Setup MBUS dram target info. - */ - orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(DDR_BASE_CS(i)); - u32 size = readl(DDR_SIZE_CS(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &orion_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xff000000; - w->size = (size | 0x00ffffff) + 1; - } - } - orion_mbus_dram_info.num_cs = cs; -} - -void __init orion_setup_dev_boot_win(u32 base, u32 size) -{ - setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); -} - -void __init orion_setup_dev0_win(u32 base, u32 size) -{ - setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); -} - -void __init orion_setup_dev1_win(u32 base, u32 size) -{ - setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); -} - -void __init orion_setup_dev2_win(u32 base, u32 size) -{ - setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); -} - -void __init orion_setup_pcie_wa_win(u32 base, u32 size) -{ - setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); -} - -void __init orion_setup_eth_wins(void) -{ - int i; - - /* - * First, disable and clear windows - */ - for (i = 0; i < ETH_MAX_WIN; i++) { - orion_write(ETH_WIN_BASE(i), 0); - orion_write(ETH_WIN_SIZE(i), 0); - orion_setbits(ETH_WIN_EN, 1 << i); - orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); - if (i < ETH_MAX_REMAP_WIN) - orion_write(ETH_WIN_REMAP(i), 0); - } - - /* - * Setup windows for DDR banks. - */ - for (i = 0; i < DDR_MAX_CS; i++) { - u32 base, size; - size = orion_read(DDR_SIZE_CS(i)); - base = orion_read(DDR_BASE_CS(i)); - if (size & DDR_BANK_EN) { - base = DDR_REG_TO_BASE(base); - size = DDR_REG_TO_SIZE(size); - orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); - orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) | - (ATTR_DDR_CS(i) << 8) | - TARGET_DDR); - orion_clrbits(ETH_WIN_EN, 1 << i); - orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); - } - } -} diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c deleted file mode 100644 index 85c8f18268a..00000000000 --- a/arch/arm/mach-orion/common.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - * arch/arm/mach-orion/common.c - * - * Core functions for Marvell Orion System On Chip - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -/***************************************************************************** - * I/O Address Mapping - ****************************************************************************/ -static struct map_desc orion_io_desc[] __initdata = { - { - .virtual = ORION_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE), - .length = ORION_REGS_SIZE, - .type = MT_DEVICE - }, - { - .virtual = ORION_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE), - .length = ORION_PCIE_IO_SIZE, - .type = MT_DEVICE - }, - { - .virtual = ORION_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE), - .length = ORION_PCI_IO_SIZE, - .type = MT_DEVICE - }, - { - .virtual = ORION_PCIE_WA_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE), - .length = ORION_PCIE_WA_SIZE, - .type = MT_DEVICE - }, -}; - -void __init orion_map_io(void) -{ - iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc)); -} - -/***************************************************************************** - * UART - ****************************************************************************/ - -static struct resource orion_uart_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_ORION_UART0, - .end = IRQ_ORION_UART0, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_ORION_UART1, - .end = IRQ_ORION_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct plat_serial8250_port orion_uart_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_ORION_UART0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = ORION_TCLK, - }, - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_ORION_UART1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = ORION_TCLK, - }, - { }, -}; - -static struct platform_device orion_uart = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = orion_uart_data, - }, - .resource = orion_uart_resources, - .num_resources = ARRAY_SIZE(orion_uart_resources), -}; - -/******************************************************************************* - * USB Controller - 2 interfaces - ******************************************************************************/ - -static struct resource orion_ehci0_resources[] = { - { - .start = ORION_USB0_PHYS_BASE, - .end = ORION_USB0_PHYS_BASE + SZ_4K, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_ORION_USB0_CTRL, - .end = IRQ_ORION_USB0_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource orion_ehci1_resources[] = { - { - .start = ORION_USB1_PHYS_BASE, - .end = ORION_USB1_PHYS_BASE + SZ_4K, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_ORION_USB1_CTRL, - .end = IRQ_ORION_USB1_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct orion_ehci_data orion_ehci_data = { - .dram = &orion_mbus_dram_info, -}; - -static u64 ehci_dmamask = 0xffffffffUL; - -static struct platform_device orion_ehci0 = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &orion_ehci_data, - }, - .resource = orion_ehci0_resources, - .num_resources = ARRAY_SIZE(orion_ehci0_resources), -}; - -static struct platform_device orion_ehci1 = { - .name = "orion-ehci", - .id = 1, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &orion_ehci_data, - }, - .resource = orion_ehci1_resources, - .num_resources = ARRAY_SIZE(orion_ehci1_resources), -}; - -/***************************************************************************** - * Gigabit Ethernet port - * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) - ****************************************************************************/ - -static struct resource orion_eth_shared_resources[] = { - { - .start = ORION_ETH_PHYS_BASE + 0x2000, - .end = ORION_ETH_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device orion_eth_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .num_resources = 1, - .resource = orion_eth_shared_resources, -}; - -static struct resource orion_eth_resources[] = { - { - .name = "eth irq", - .start = IRQ_ORION_ETH_SUM, - .end = IRQ_ORION_ETH_SUM, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device orion_eth = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = orion_eth_resources, -}; - -void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) -{ - orion_eth.dev.platform_data = eth_data; - platform_device_register(&orion_eth_shared); - platform_device_register(&orion_eth); -} - -/***************************************************************************** - * I2C controller - * (The Orion and Discovery (MV643xx) families share the same I2C controller) - ****************************************************************************/ - -static struct mv64xxx_i2c_pdata orion_i2c_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource orion_i2c_resources[] = { - { - .name = "i2c base", - .start = I2C_PHYS_BASE, - .end = I2C_PHYS_BASE + 0x20 -1, - .flags = IORESOURCE_MEM, - }, - { - .name = "i2c irq", - .start = IRQ_ORION_I2C, - .end = IRQ_ORION_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion_i2c = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(orion_i2c_resources), - .resource = orion_i2c_resources, - .dev = { - .platform_data = &orion_i2c_pdata, - }, -}; - -/***************************************************************************** - * Sata port - ****************************************************************************/ -static struct resource orion_sata_resources[] = { - { - .name = "sata base", - .start = ORION_SATA_PHYS_BASE, - .end = ORION_SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "sata irq", - .start = IRQ_ORION_SATA, - .end = IRQ_ORION_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(orion_sata_resources), - .resource = orion_sata_resources, -}; - -void __init orion_sata_init(struct mv_sata_platform_data *sata_data) -{ - sata_data->dram = &orion_mbus_dram_info; - orion_sata.dev.platform_data = sata_data; - platform_device_register(&orion_sata); -} - -/***************************************************************************** - * Time handling - ****************************************************************************/ - -static void orion_timer_init(void) -{ - orion_time_init(IRQ_ORION_BRIDGE, ORION_TCLK); -} - -struct sys_timer orion_timer = { - .init = orion_timer_init, -}; - -/***************************************************************************** - * General - ****************************************************************************/ - -/* - * Identify device ID and rev from PCIE configuration header space '0'. - */ -static void __init orion_id(u32 *dev, u32 *rev, char **dev_name) -{ - orion_pcie_id(dev, rev); - - if (*dev == MV88F5281_DEV_ID) { - if (*rev == MV88F5281_REV_D2) { - *dev_name = "MV88F5281-D2"; - } else if (*rev == MV88F5281_REV_D1) { - *dev_name = "MV88F5281-D1"; - } else { - *dev_name = "MV88F5281-Rev-Unsupported"; - } - } else if (*dev == MV88F5182_DEV_ID) { - if (*rev == MV88F5182_REV_A2) { - *dev_name = "MV88F5182-A2"; - } else { - *dev_name = "MV88F5182-Rev-Unsupported"; - } - } else if (*dev == MV88F5181_DEV_ID) { - if (*rev == MV88F5181_REV_B1) { - *dev_name = "MV88F5181-Rev-B1"; - } else { - *dev_name = "MV88F5181-Rev-Unsupported"; - } - } else { - *dev_name = "Device-Unknown"; - } -} - -void __init orion_init(void) -{ - char *dev_name; - u32 dev, rev; - - orion_id(&dev, &rev, &dev_name); - printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK); - - /* - * Setup Orion address map - */ - orion_setup_cpu_mbus_bridge(); - orion_setup_eth_wins(); - - /* - * Register devices. - */ - platform_device_register(&orion_uart); - platform_device_register(&orion_ehci0); - if (dev == MV88F5182_DEV_ID) - platform_device_register(&orion_ehci1); - platform_device_register(&orion_i2c); -} - -/* - * Many orion-based systems have buggy bootloader implementations. - * This is a common fixup for bogus memory tags. - */ -void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t, - char **from, struct meminfo *meminfo) -{ - for (; t->hdr.size; t = tag_next(t)) - if (t->hdr.tag == ATAG_MEM && - (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || - t->u.mem.start & ~PAGE_MASK)) { - printk(KERN_WARNING - "Clearing invalid memory bank %dKB@0x%08x\n", - t->u.mem.size / 1024, t->u.mem.start); - t->hdr.tag = 0; - } -} diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h deleted file mode 100644 index bcc31adaca1..00000000000 --- a/arch/arm/mach-orion/common.h +++ /dev/null @@ -1,72 +0,0 @@ -#ifndef __ARCH_ORION_COMMON_H -#define __ARCH_ORION_COMMON_H - -/* - * Basic Orion init functions used early by machine-setup. - */ - -void orion_map_io(void); -void orion_init_irq(void); -void orion_init(void); -extern struct sys_timer orion_timer; - -/* - * Enumerations and functions for Orion windows mapping. Used by Orion core - * functions to map its interfaces and by the machine-setup to map its on- - * board devices. Details in /mach-orion/addr-map.c - */ -extern struct mbus_dram_target_info orion_mbus_dram_info; -void orion_setup_cpu_mbus_bridge(void); -void orion_setup_dev_boot_win(u32 base, u32 size); -void orion_setup_dev0_win(u32 base, u32 size); -void orion_setup_dev1_win(u32 base, u32 size); -void orion_setup_dev2_win(u32 base, u32 size); -void orion_setup_pcie_wa_win(u32 base, u32 size); -void orion_setup_eth_wins(void); - -/* - * Shared code used internally by other Orion core functions. - * (/mach-orion/pci.c) - */ - -struct pci_sys_data; -struct pci_bus; - -void orion_pcie_id(u32 *dev, u32 *rev); -int orion_pcie_local_bus_nr(void); -int orion_pci_local_bus_nr(void); -int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); -struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); - -/* - * Valid GPIO pins according to MPP setup, used by machine-setup. - * (/mach-orion/gpio.c). - */ - -void orion_gpio_set_valid_pins(u32 pins); -void gpio_display(void); /* debug */ - -/* - * Pull in Orion Ethernet platform_data, used by machine-setup - */ - -struct mv643xx_eth_platform_data; - -void orion_eth_init(struct mv643xx_eth_platform_data *eth_data); - -/* - * Orion Sata platform_data, used by machine-setup - */ - -struct mv_sata_platform_data; - -void orion_sata_init(struct mv_sata_platform_data *sata_data); - -struct machine_desc; -struct meminfo; -struct tag; -extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, - char **, struct meminfo *); - - -#endif diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c deleted file mode 100644 index a0a9e4851b5..00000000000 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * arch/arm/mach-orion/db88f5281-setup.c - * - * Marvell Orion-2 Development Board Setup - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -/***************************************************************************** - * DB-88F5281 on board devices - ****************************************************************************/ - -/* - * 512K NOR flash Device bus boot chip select - */ - -#define DB88F5281_NOR_BOOT_BASE 0xf4000000 -#define DB88F5281_NOR_BOOT_SIZE SZ_512K - -/* - * 7-Segment on Device bus chip select 0 - */ - -#define DB88F5281_7SEG_BASE 0xfa000000 -#define DB88F5281_7SEG_SIZE SZ_1K - -/* - * 32M NOR flash on Device bus chip select 1 - */ - -#define DB88F5281_NOR_BASE 0xfc000000 -#define DB88F5281_NOR_SIZE SZ_32M - -/* - * 32M NAND flash on Device bus chip select 2 - */ - -#define DB88F5281_NAND_BASE 0xfa800000 -#define DB88F5281_NAND_SIZE SZ_1K - -/* - * PCI - */ - -#define DB88F5281_PCI_SLOT0_OFFS 7 -#define DB88F5281_PCI_SLOT0_IRQ_PIN 12 -#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13 - -/***************************************************************************** - * 512M NOR Flash on Device bus Boot CS - ****************************************************************************/ - -static struct physmap_flash_data db88f5281_boot_flash_data = { - .width = 1, /* 8 bit bus width */ -}; - -static struct resource db88f5281_boot_flash_resource = { - .flags = IORESOURCE_MEM, - .start = DB88F5281_NOR_BOOT_BASE, - .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device db88f5281_boot_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &db88f5281_boot_flash_data, - }, - .num_resources = 1, - .resource = &db88f5281_boot_flash_resource, -}; - -/***************************************************************************** - * 32M NOR Flash on Device bus CS1 - ****************************************************************************/ - -static struct physmap_flash_data db88f5281_nor_flash_data = { - .width = 4, /* 32 bit bus width */ -}; - -static struct resource db88f5281_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = DB88F5281_NOR_BASE, - .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1, -}; - -static struct platform_device db88f5281_nor_flash = { - .name = "physmap-flash", - .id = 1, - .dev = { - .platform_data = &db88f5281_nor_flash_data, - }, - .num_resources = 1, - .resource = &db88f5281_nor_flash_resource, -}; - -/***************************************************************************** - * 32M NAND Flash on Device bus CS2 - ****************************************************************************/ - -static struct mtd_partition db88f5281_nand_parts[] = { - { - .name = "kernel", - .offset = 0, - .size = SZ_2M, - }, - { - .name = "root", - .offset = SZ_2M, - .size = (SZ_16M - SZ_2M), - }, - { - .name = "user", - .offset = SZ_16M, - .size = SZ_8M, - }, - { - .name = "recovery", - .offset = (SZ_16M + SZ_8M), - .size = SZ_8M, - }, -}; - -static struct resource db88f5281_nand_resource = { - .flags = IORESOURCE_MEM, - .start = DB88F5281_NAND_BASE, - .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1, -}; - -static struct orion_nand_data db88f5281_nand_data = { - .parts = db88f5281_nand_parts, - .nr_parts = ARRAY_SIZE(db88f5281_nand_parts), - .cle = 0, - .ale = 1, - .width = 8, -}; - -static struct platform_device db88f5281_nand_flash = { - .name = "orion_nand", - .id = -1, - .dev = { - .platform_data = &db88f5281_nand_data, - }, - .resource = &db88f5281_nand_resource, - .num_resources = 1, -}; - -/***************************************************************************** - * 7-Segment on Device bus CS0 - * Dummy counter every 2 sec - ****************************************************************************/ - -static void __iomem *db88f5281_7seg; -static struct timer_list db88f5281_timer; - -static void db88f5281_7seg_event(unsigned long data) -{ - static int count = 0; - writel(0, db88f5281_7seg + (count << 4)); - count = (count + 1) & 7; - mod_timer(&db88f5281_timer, jiffies + 2 * HZ); -} - -static int __init db88f5281_7seg_init(void) -{ - if (machine_is_db88f5281()) { - db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE, - DB88F5281_7SEG_SIZE); - if (!db88f5281_7seg) { - printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n"); - return -EIO; - } - setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0); - mod_timer(&db88f5281_timer, jiffies + 2 * HZ); - } - - return 0; -} - -__initcall(db88f5281_7seg_init); - -/***************************************************************************** - * PCI - ****************************************************************************/ - -void __init db88f5281_pci_preinit(void) -{ - int pin; - - /* - * Configure PCI GPIO IRQ pins - */ - pin = DB88F5281_PCI_SLOT0_IRQ_PIN; - if (gpio_request(pin, "PCI Int1") == 0) { - if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); - } else { - printk(KERN_ERR "db88f5281_pci_preinit faield to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); - } - - pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; - if (gpio_request(pin, "PCI Int2") == 0) { - if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); - } else { - printk(KERN_ERR "db88f5281_pci_preinit faield " - "to set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); - } -} - -static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - /* - * PCIE IRQ is connected internally (not GPIO) - */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; - - /* - * PCI IRQs are connected via GPIOs - */ - switch (slot - DB88F5281_PCI_SLOT0_OFFS) { - case 0: - return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN); - case 1: - case 2: - return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN); - default: - return -1; - } -} - -static struct hw_pci db88f5281_pci __initdata = { - .nr_controllers = 2, - .preinit = db88f5281_pci_preinit, - .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, - .map_irq = db88f5281_pci_map_irq, -}; - -static int __init db88f5281_pci_init(void) -{ - if (machine_is_db88f5281()) - pci_common_init(&db88f5281_pci); - - return 0; -} - -subsys_initcall(db88f5281_pci_init); - -/***************************************************************************** - * Ethernet - ****************************************************************************/ -static struct mv643xx_eth_platform_data db88f5281_eth_data = { - .phy_addr = 8, - .force_phy_addr = 1, -}; - -/***************************************************************************** - * RTC DS1339 on I2C bus - ****************************************************************************/ -static struct i2c_board_info __initdata db88f5281_i2c_rtc = { - .driver_name = "rtc-ds1307", - .type = "ds1339", - .addr = 0x68, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -static struct platform_device *db88f5281_devs[] __initdata = { - &db88f5281_boot_flash, - &db88f5281_nor_flash, - &db88f5281_nand_flash, -}; - -static void __init db88f5281_init(void) -{ - /* - * Basic Orion setup. Need to be called early. - */ - orion_init(); - - /* - * Setup the CPU address decode windows for our on-board devices - */ - orion_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE); - orion_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); - orion_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); - orion_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); - - /* - * Setup Multiplexing Pins: - * MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input) - * MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2] - * MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3] - * MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1) - * MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3) - * MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator) - * MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2) - * MPP14: NAND_REn[2] MPP15: NAND_WEn[2] - * MPP16: UART1_RX MPP17: UART1_TX - * MPP18: UART1_CTS MPP19: UART1_RTS - * MPP-DEV: DEV_D[16:31] - */ - orion_write(MPP_0_7_CTRL, 0x00222203); - orion_write(MPP_8_15_CTRL, 0x44000000); - orion_write(MPP_16_19_CTRL, 0); - orion_write(MPP_DEV_CTRL, 0); - - orion_gpio_set_valid_pins(0x00003fc3); - - platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); - i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); - orion_eth_init(&db88f5281_eth_data); -} - -MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") - /* Maintainer: Tzachi Perelstein */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = db88f5281_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, -MACHINE_END diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c deleted file mode 100644 index 88991f76479..00000000000 --- a/arch/arm/mach-orion/dns323-setup.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * arch/arm/mach-orion/dns323-setup.c - * - * Copyright (C) 2007 Herbert Valerio Riedel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -#define DNS323_GPIO_LED_RIGHT_AMBER 1 -#define DNS323_GPIO_LED_LEFT_AMBER 2 -#define DNS323_GPIO_LED_POWER 5 -#define DNS323_GPIO_OVERTEMP 6 -#define DNS323_GPIO_RTC 7 -#define DNS323_GPIO_POWER_OFF 8 -#define DNS323_GPIO_KEY_POWER 9 -#define DNS323_GPIO_KEY_RESET 10 - -/**************************************************************************** - * PCI setup - */ - -static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - /* PCI-E */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; - - pr_err("%s: requested mapping for unknown bus\n", __func__); - - return -1; -} - -static struct hw_pci dns323_pci __initdata = { - .nr_controllers = 1, - .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, - .map_irq = dns323_pci_map_irq, -}; - -static int __init dns323_pci_init(void) -{ - if (machine_is_dns323()) - pci_common_init(&dns323_pci); - - return 0; -} - -subsys_initcall(dns323_pci_init); - -/**************************************************************************** - * Ethernet - */ - -static struct mv643xx_eth_platform_data dns323_eth_data = { - .phy_addr = 8, - .force_phy_addr = 1, -}; - -/**************************************************************************** - * 8MiB NOR flash (Spansion S29GL064M90TFIR4) - * - * Layout as used by D-Link: - * 0x00000000-0x00010000 : "MTD1" - * 0x00010000-0x00020000 : "MTD2" - * 0x00020000-0x001a0000 : "Linux Kernel" - * 0x001a0000-0x007d0000 : "File System" - * 0x007d0000-0x00800000 : "u-boot" - */ - -#define DNS323_NOR_BOOT_BASE 0xf4000000 -#define DNS323_NOR_BOOT_SIZE SZ_8M - -static struct mtd_partition dns323_partitions[] = { - { - .name = "MTD1", - .size = 0x00010000, - .offset = 0, - }, { - .name = "MTD2", - .size = 0x00010000, - .offset = 0x00010000, - }, { - .name = "Linux Kernel", - .size = 0x00180000, - .offset = 0x00020000, - }, { - .name = "File System", - .size = 0x00630000, - .offset = 0x001A0000, - }, { - .name = "u-boot", - .size = 0x00030000, - .offset = 0x007d0000, - } -}; - -static struct physmap_flash_data dns323_nor_flash_data = { - .width = 1, - .parts = dns323_partitions, - .nr_parts = ARRAY_SIZE(dns323_partitions) -}; - -static struct resource dns323_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = DNS323_NOR_BOOT_BASE, - .end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device dns323_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { .platform_data = &dns323_nor_flash_data, }, - .resource = &dns323_nor_flash_resource, - .num_resources = 1, -}; - -/**************************************************************************** - * GPIO LEDs (simple - doesn't use hardware blinking support) - */ - -static struct gpio_led dns323_leds[] = { - { - .name = "power:blue", - .gpio = DNS323_GPIO_LED_POWER, - .active_low = 1, - }, { - .name = "right:amber", - .gpio = DNS323_GPIO_LED_RIGHT_AMBER, - .active_low = 1, - }, { - .name = "left:amber", - .gpio = DNS323_GPIO_LED_LEFT_AMBER, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data dns323_led_data = { - .num_leds = ARRAY_SIZE(dns323_leds), - .leds = dns323_leds, -}; - -static struct platform_device dns323_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { .platform_data = &dns323_led_data, }, -}; - -/**************************************************************************** - * GPIO Attached Keys - */ - -static struct gpio_keys_button dns323_buttons[] = { - { - .code = KEY_RESTART, - .gpio = DNS323_GPIO_KEY_RESET, - .desc = "Reset Button", - .active_low = 1, - }, - { - .code = KEY_POWER, - .gpio = DNS323_GPIO_KEY_POWER, - .desc = "Power Button", - .active_low = 1, - } -}; - -static struct gpio_keys_platform_data dns323_button_data = { - .buttons = dns323_buttons, - .nbuttons = ARRAY_SIZE(dns323_buttons), -}; - -static struct platform_device dns323_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { .platform_data = &dns323_button_data, }, -}; - -/**************************************************************************** - * General Setup - */ - -static struct platform_device *dns323_plat_devices[] __initdata = { - &dns323_nor_flash, - &dns323_gpio_leds, - &dns323_button_device, -}; - -/* - * On the DNS-323 the following devices are attached via I2C: - * - * i2c addr | chip | description - * 0x3e | GMT G760Af | fan speed PWM controller - * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) - * 0x68 | ST M41T80 | RTC w/ alarm - */ -static struct i2c_board_info __initdata dns323_i2c_devices[] = { - { - I2C_BOARD_INFO("g760a", 0x3e), - .type = "g760a", - }, -#if 0 - /* this entry requires the new-style driver model lm75 driver, - * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */ - { - I2C_BOARD_INFO("lm75", 0x48), - .type = "g751", - }, -#endif - { - I2C_BOARD_INFO("rtc-m41t80", 0x68), - .type = "m41t80", - } -}; - -/* DNS-323 specific power off method */ -static void dns323_power_off(void) -{ - pr_info("%s: triggering power-off...\n", __func__); - gpio_set_value(DNS323_GPIO_POWER_OFF, 1); -} - -static void __init dns323_init(void) -{ - /* Setup basic Orion functions. Need to be called early. */ - orion_init(); - - /* setup flash mapping - * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 - */ - orion_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); - - /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE - * - * Open a special address decode windows for the PCIE WA. - */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); - - /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ - orion_write(MPP_0_7_CTRL, 0); - orion_write(MPP_8_15_CTRL, 0); - orion_write(MPP_16_19_CTRL, 0); - orion_write(MPP_DEV_CTRL, 0); - - /* Define used GPIO pins - - GPIO Map: - - | 0 | | PEX_RST_OUT (not controlled by GPIO) - | 1 | Out | right amber LED (= sata ch0 LED) (low-active) - | 2 | Out | left amber LED (= sata ch1 LED) (low-active) - | 3 | Out | //unknown// - | 4 | Out | power button LED (low-active, together with pin #5) - | 5 | Out | power button LED (low-active, together with pin #4) - | 6 | In | GMT G751-2f overtemp. shutdown signal (low-active) - | 7 | In | M41T80 nIRQ/OUT/SQW signal - | 8 | Out | triggers power off (high-active) - | 9 | In | power button switch (low-active) - | 10 | In | reset button switch (low-active) - | 11 | Out | //unknown// - | 12 | Out | //unknown// - | 13 | Out | //unknown// - | 14 | Out | //unknown// - | 15 | Out | //unknown// - */ - orion_gpio_set_valid_pins(0x07f6); - - /* register dns323 specific power-off method */ - if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) - || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)) - pr_err("DNS323: failed to setup power-off GPIO\n"); - - pm_power_off = dns323_power_off; - - /* register flash and other platform devices */ - platform_add_devices(dns323_plat_devices, - ARRAY_SIZE(dns323_plat_devices)); - - i2c_register_board_info(0, dns323_i2c_devices, - ARRAY_SIZE(dns323_i2c_devices)); - - orion_eth_init(&dns323_eth_data); -} - -/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ -MACHINE_START(DNS323, "D-Link DNS-323") - /* Maintainer: Herbert Valerio Riedel */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, - .boot_params = 0x00000100, - .init_machine = dns323_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, - .fixup = tag_fixup_mem32, -MACHINE_END diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c deleted file mode 100644 index afc7be08b30..00000000000 --- a/arch/arm/mach-orion/gpio.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * arch/arm/mach-orion/gpio.c - * - * GPIO functions for Marvell Orion System On Chip - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -static DEFINE_SPINLOCK(gpio_lock); -static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; -static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ - -void __init orion_gpio_set_valid_pins(u32 pins) -{ - gpio_valid[0] = pins; -} - -/* - * GENERIC_GPIO primitives - */ -int gpio_direction_input(unsigned pin) -{ - unsigned long flags; - - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return -EINVAL; - } - - spin_lock_irqsave(&gpio_lock, flags); - - /* - * Some callers might have not used the gpio_request(), - * so flag this pin as requested now. - */ - if (!gpio_label[pin]) - gpio_label[pin] = "?"; - - orion_setbits(GPIO_IO_CONF, 1 << pin); - - spin_unlock_irqrestore(&gpio_lock, flags); - return 0; -} -EXPORT_SYMBOL(gpio_direction_input); - -int gpio_direction_output(unsigned pin, int value) -{ - unsigned long flags; - int mask; - - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return -EINVAL; - } - - spin_lock_irqsave(&gpio_lock, flags); - - /* - * Some callers might have not used the gpio_request(), - * so flag this pin as requested now. - */ - if (!gpio_label[pin]) - gpio_label[pin] = "?"; - - mask = 1 << pin; - orion_clrbits(GPIO_BLINK_EN, mask); - if (value) - orion_setbits(GPIO_OUT, mask); - else - orion_clrbits(GPIO_OUT, mask); - orion_clrbits(GPIO_IO_CONF, mask); - - spin_unlock_irqrestore(&gpio_lock, flags); - return 0; -} -EXPORT_SYMBOL(gpio_direction_output); - -int gpio_get_value(unsigned pin) -{ - int val, mask = 1 << pin; - - if (orion_read(GPIO_IO_CONF) & mask) - val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL); - else - val = orion_read(GPIO_OUT); - - return val & mask; -} -EXPORT_SYMBOL(gpio_get_value); - -void gpio_set_value(unsigned pin, int value) -{ - unsigned long flags; - int mask = 1 << pin; - - spin_lock_irqsave(&gpio_lock, flags); - - orion_clrbits(GPIO_BLINK_EN, mask); - if (value) - orion_setbits(GPIO_OUT, mask); - else - orion_clrbits(GPIO_OUT, mask); - - spin_unlock_irqrestore(&gpio_lock, flags); -} -EXPORT_SYMBOL(gpio_set_value); - -void orion_gpio_set_blink(unsigned pin, int blink) -{ - unsigned long flags; - int mask = 1 << pin; - - spin_lock_irqsave(&gpio_lock, flags); - - orion_clrbits(GPIO_OUT, mask); - if (blink) - orion_setbits(GPIO_BLINK_EN, mask); - else - orion_clrbits(GPIO_BLINK_EN, mask); - - spin_unlock_irqrestore(&gpio_lock, flags); -} -EXPORT_SYMBOL(orion_gpio_set_blink); - -int gpio_request(unsigned pin, const char *label) -{ - int ret = 0; - unsigned long flags; - - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return -EINVAL; - } - - spin_lock_irqsave(&gpio_lock, flags); - - if (gpio_label[pin]) { - pr_debug("%s: GPIO %d already used as %s\n", - __func__, pin, gpio_label[pin]); - ret = -EBUSY; - } else - gpio_label[pin] = label ? label : "?"; - - spin_unlock_irqrestore(&gpio_lock, flags); - return ret; -} -EXPORT_SYMBOL(gpio_request); - -void gpio_free(unsigned pin) -{ - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return; - } - - if (!gpio_label[pin]) - pr_warning("%s: GPIO %d already freed\n", __func__, pin); - else - gpio_label[pin] = NULL; -} -EXPORT_SYMBOL(gpio_free); - -/* Debug helper */ -void gpio_display(void) -{ - int i; - - for (i = 0; i < GPIO_MAX; i++) { - printk(KERN_DEBUG "Pin-%d: ", i); - - if (!test_bit(i, gpio_valid)) { - printk("non-GPIO\n"); - } else if (!gpio_label[i]) { - printk("GPIO, free\n"); - } else { - printk("GPIO, used by %s, ", gpio_label[i]); - if (orion_read(GPIO_IO_CONF) & (1 << i)) { - printk("input, active %s, level %s, edge %s\n", - ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", - ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", - ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); - } else { - printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1); - } - } - } - - printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", - MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL)); - printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", - MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL)); - printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", - MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL)); - printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", - MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL)); - printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", - GPIO_OUT, orion_read(GPIO_OUT)); - printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", - GPIO_IO_CONF, orion_read(GPIO_IO_CONF)); - printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", - GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN)); - printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", - GPIO_IN_POL, orion_read(GPIO_IN_POL)); - printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", - GPIO_DATA_IN, orion_read(GPIO_DATA_IN)); - printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", - GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK)); - printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", - GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE)); - printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", - GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK)); -} diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c deleted file mode 100644 index 7033cc1360e..00000000000 --- a/arch/arm/mach-orion/irq.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * arch/arm/mach-orion/irq.c - * - * Core IRQ functions for Marvell Orion System On Chip - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -/***************************************************************************** - * Orion GPIO IRQ - * - * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same - * value of the line or the opposite value. - * - * Level IRQ handlers: DATA_IN is used directly as cause register. - * Interrupt are masked by LEVEL_MASK registers. - * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. - * Interrupt are masked by EDGE_MASK registers. - * Both-edge handlers: Similar to regular Edge handlers, but also swaps - * the polarity to catch the next line transaction. - * This is a race condition that might not perfectly - * work on some use cases. - * - * Every eight GPIO lines are grouped (OR'ed) before going up to main - * cause register. - * - * EDGE cause mask - * data-in /--------| |-----| |----\ - * -----| |----- ---- to main cause reg - * X \----------------| |----/ - * polarity LEVEL mask - * - ****************************************************************************/ -static void orion_gpio_irq_ack(u32 irq) -{ - int pin = irq_to_gpio(irq); - if (irq_desc[irq].status & IRQ_LEVEL) - /* - * Mask bit for level interrupt - */ - orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); - else - /* - * Clear casue bit for egde interrupt - */ - orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin); -} - -static void orion_gpio_irq_mask(u32 irq) -{ - int pin = irq_to_gpio(irq); - if (irq_desc[irq].status & IRQ_LEVEL) - orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); - else - orion_clrbits(GPIO_EDGE_MASK, 1 << pin); -} - -static void orion_gpio_irq_unmask(u32 irq) -{ - int pin = irq_to_gpio(irq); - if (irq_desc[irq].status & IRQ_LEVEL) - orion_setbits(GPIO_LEVEL_MASK, 1 << pin); - else - orion_setbits(GPIO_EDGE_MASK, 1 << pin); -} - -static int orion_gpio_set_irq_type(u32 irq, u32 type) -{ - int pin = irq_to_gpio(irq); - struct irq_desc *desc; - - if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) { - printk(KERN_ERR "orion_gpio_set_irq_type failed " - "(irq %d, pin %d).\n", irq, pin); - return -EINVAL; - } - - desc = irq_desc + irq; - - switch (type) { - case IRQT_HIGH: - desc->handle_irq = handle_level_irq; - desc->status |= IRQ_LEVEL; - orion_clrbits(GPIO_IN_POL, (1 << pin)); - break; - case IRQT_LOW: - desc->handle_irq = handle_level_irq; - desc->status |= IRQ_LEVEL; - orion_setbits(GPIO_IN_POL, (1 << pin)); - break; - case IRQT_RISING: - desc->handle_irq = handle_edge_irq; - desc->status &= ~IRQ_LEVEL; - orion_clrbits(GPIO_IN_POL, (1 << pin)); - break; - case IRQT_FALLING: - desc->handle_irq = handle_edge_irq; - desc->status &= ~IRQ_LEVEL; - orion_setbits(GPIO_IN_POL, (1 << pin)); - break; - case IRQT_BOTHEDGE: - desc->handle_irq = handle_edge_irq; - desc->status &= ~IRQ_LEVEL; - /* - * set initial polarity based on current input level - */ - if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN)) - & (1 << pin)) - orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ - else - orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ - - break; - default: - printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); - return -EINVAL; - } - - desc->status &= ~IRQ_TYPE_SENSE_MASK; - desc->status |= type & IRQ_TYPE_SENSE_MASK; - - return 0; -} - -static struct irq_chip orion_gpio_irq_chip = { - .name = "Orion-IRQ-GPIO", - .ack = orion_gpio_irq_ack, - .mask = orion_gpio_irq_mask, - .unmask = orion_gpio_irq_unmask, - .set_type = orion_gpio_set_irq_type, -}; - -static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - u32 cause, offs, pin; - - BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31); - offs = (irq - IRQ_ORION_GPIO_0_7) * 8; - cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) | - (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK)); - - for (pin = offs; pin < offs + 8; pin++) { - if (cause & (1 << pin)) { - irq = gpio_to_irq(pin); - desc = irq_desc + irq; - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { - /* Swap polarity (race with GPIO line) */ - u32 polarity = orion_read(GPIO_IN_POL); - polarity ^= 1 << pin; - orion_write(GPIO_IN_POL, polarity); - } - desc_handle_irq(irq, desc); - } - } -} - -static void __init orion_init_gpio_irq(void) -{ - int i; - struct irq_desc *desc; - - /* - * Mask and clear GPIO IRQ interrupts - */ - orion_write(GPIO_LEVEL_MASK, 0x0); - orion_write(GPIO_EDGE_MASK, 0x0); - orion_write(GPIO_EDGE_CAUSE, 0x0); - - /* - * Register chained level handlers for GPIO IRQs by default. - * User can use set_type() if he wants to use edge types handlers. - */ - for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) { - set_irq_chip(i, &orion_gpio_irq_chip); - set_irq_handler(i, handle_level_irq); - desc = irq_desc + i; - desc->status |= IRQ_LEVEL; - set_irq_flags(i, IRQF_VALID); - } - set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler); -} - -/***************************************************************************** - * Orion Main IRQ - ****************************************************************************/ -static void __init orion_init_main_irq(void) -{ - orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); -} - -void __init orion_init_irq(void) -{ - orion_init_main_irq(); - orion_init_gpio_irq(); -} diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c deleted file mode 100644 index be417e7f423..00000000000 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * arch/arm/mach-orion/kurobox_pro-setup.c - * - * Maintainer: Ronen Shitrit - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -/***************************************************************************** - * KUROBOX-PRO Info - ****************************************************************************/ - -/* - * 256K NOR flash Device bus boot chip select - */ - -#define KUROBOX_PRO_NOR_BOOT_BASE 0xf4000000 -#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K - -/* - * 256M NAND flash on Device bus chip select 1 - */ - -#define KUROBOX_PRO_NAND_BASE 0xfc000000 -#define KUROBOX_PRO_NAND_SIZE SZ_2M - -/***************************************************************************** - * 256MB NAND Flash on Device bus CS0 - ****************************************************************************/ - -static struct mtd_partition kurobox_pro_nand_parts[] = { - { - .name = "uImage", - .offset = 0, - .size = SZ_4M, - }, - { - .name = "rootfs", - .offset = SZ_4M, - .size = SZ_64M, - }, - { - .name = "extra", - .offset = SZ_4M + SZ_64M, - .size = SZ_256M - (SZ_4M + SZ_64M), - }, -}; - -static struct resource kurobox_pro_nand_resource = { - .flags = IORESOURCE_MEM, - .start = KUROBOX_PRO_NAND_BASE, - .end = KUROBOX_PRO_NAND_BASE + KUROBOX_PRO_NAND_SIZE - 1, -}; - -static struct orion_nand_data kurobox_pro_nand_data = { - .parts = kurobox_pro_nand_parts, - .nr_parts = ARRAY_SIZE(kurobox_pro_nand_parts), - .cle = 0, - .ale = 1, - .width = 8, -}; - -static struct platform_device kurobox_pro_nand_flash = { - .name = "orion_nand", - .id = -1, - .dev = { - .platform_data = &kurobox_pro_nand_data, - }, - .resource = &kurobox_pro_nand_resource, - .num_resources = 1, -}; - -/***************************************************************************** - * 256KB NOR Flash on BOOT Device - ****************************************************************************/ - -static struct physmap_flash_data kurobox_pro_nor_flash_data = { - .width = 1, -}; - -static struct resource kurobox_pro_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = KUROBOX_PRO_NOR_BOOT_BASE, - .end = KUROBOX_PRO_NOR_BOOT_BASE + KUROBOX_PRO_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device kurobox_pro_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &kurobox_pro_nor_flash_data, - }, - .num_resources = 1, - .resource = &kurobox_pro_nor_flash_resource, -}; - -/***************************************************************************** - * PCI - ****************************************************************************/ - -static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - /* - * PCI isn't used on the Kuro - */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; - else - printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); - - return -1; -} - -static struct hw_pci kurobox_pro_pci __initdata = { - .nr_controllers = 1, - .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, - .map_irq = kurobox_pro_pci_map_irq, -}; - -static int __init kurobox_pro_pci_init(void) -{ - if (machine_is_kurobox_pro()) - pci_common_init(&kurobox_pro_pci); - - return 0; -} - -subsys_initcall(kurobox_pro_pci_init); - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data kurobox_pro_eth_data = { - .phy_addr = 8, - .force_phy_addr = 1, -}; - -/***************************************************************************** - * RTC 5C372a on I2C bus - ****************************************************************************/ -static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = { - .driver_name = "rtc-rs5c372", - .type = "rs5c372a", - .addr = 0x32, -}; - -/***************************************************************************** - * SATA - ****************************************************************************/ -static struct mv_sata_platform_data kurobox_pro_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -static struct platform_device *kurobox_pro_devices[] __initdata = { - &kurobox_pro_nor_flash, - &kurobox_pro_nand_flash, -}; - -static void __init kurobox_pro_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion_init(); - - /* - * Setup the CPU address decode windows for our devices - */ - orion_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, - KUROBOX_PRO_NOR_BOOT_SIZE); - orion_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); - - /* - * Open a special address decode windows for the PCIE WA. - */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); - - /* - * Setup Multiplexing Pins -- - * MPP[0-1] Not used - * MPP[2] GPIO Micon - * MPP[3] GPIO RTC - * MPP[4-5] Not used - * MPP[6] Nand Flash REn - * MPP[7] Nand Flash WEn - * MPP[8-11] Not used - * MPP[12] SATA 0 presence Indication - * MPP[13] SATA 1 presence Indication - * MPP[14] SATA 0 active Indication - * MPP[15] SATA 1 active indication - * MPP[16-19] Not used - */ - orion_write(MPP_0_7_CTRL, 0x44220003); - orion_write(MPP_8_15_CTRL, 0x55550000); - orion_write(MPP_16_19_CTRL, 0x0); - - orion_gpio_set_valid_pins(0x0000000c); - - platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); - i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); - orion_eth_init(&kurobox_pro_eth_data); - orion_sata_init(&kurobox_pro_sata_data); -} - -MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") - /* Maintainer: Ronen Shitrit */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, - .boot_params = 0x00000100, - .init_machine = kurobox_pro_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, - .fixup = tag_fixup_mem32, -MACHINE_END diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c deleted file mode 100644 index 59684cc329b..00000000000 --- a/arch/arm/mach-orion/pci.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * arch/arm/mach-orion/pci.c - * - * PCI and PCIe functions for Marvell Orion System On Chip - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "common.h" - -/***************************************************************************** - * Orion has one PCIe controller and one PCI controller. - * - * Note1: The local PCIe bus number is '0'. The local PCI bus number - * follows the scanned PCIe bridged busses, if any. - * - * Note2: It is possible for PCI/PCIe agents to access many subsystem's - * space, by configuring BARs and Address Decode Windows, e.g. flashes on - * device bus, Orion registers, etc. However this code only enable the - * access to DDR banks. - ****************************************************************************/ - - -/***************************************************************************** - * PCIe controller - ****************************************************************************/ -#define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) - -void __init orion_pcie_id(u32 *dev, u32 *rev) -{ - *dev = orion_pcie_dev_id(PCIE_BASE); - *rev = orion_pcie_rev(PCIE_BASE); -} - -int orion_pcie_local_bus_nr(void) -{ - return orion_pcie_get_local_bus_nr(PCIE_BASE); -} - -static int pcie_valid_config(int bus, int dev) -{ - /* - * Don't go out when trying to access -- - * 1. nonexisting device on local bus - * 2. where there's no device connected (no link) - */ - if (bus == 0 && dev == 0) - return 1; - - if (!orion_pcie_link_up(PCIE_BASE)) - return 0; - - if (bus == 0 && dev != 1) - return 0; - - return 1; -} - - -/* - * PCIe config cycles are done by programming the PCIE_CONF_ADDR register - * and then reading the PCIE_CONF_DATA register. Need to make sure these - * transactions are atomic. - */ -static DEFINE_SPINLOCK(orion_pcie_lock); - -static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) -{ - unsigned long flags; - int ret; - - if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - spin_lock_irqsave(&orion_pcie_lock, flags); - ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&orion_pcie_lock, flags); - - return ret; -} - -static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, - int where, int size, u32 *val) -{ - int ret; - - if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - /* - * We only support access to the non-extended configuration - * space when using the WA access method (or we would have to - * sacrifice 256M of CPU virtual address space.) - */ - if (where >= 0x100) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE, - bus, devfn, where, size, val); - - return ret; -} - -static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) -{ - unsigned long flags; - int ret; - - if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - spin_lock_irqsave(&orion_pcie_lock, flags); - ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&orion_pcie_lock, flags); - - return ret; -} - -static struct pci_ops pcie_ops = { - .read = pcie_rd_conf, - .write = pcie_wr_conf, -}; - - -static int __init pcie_setup(struct pci_sys_data *sys) -{ - struct resource *res; - int dev; - - /* - * Generic PCIe unit setup. - */ - orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info); - - /* - * Check whether to apply Orion-1/Orion-NAS PCIe config - * read transaction workaround. - */ - dev = orion_pcie_dev_id(PCIE_BASE); - if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { - printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " - "read transaction workaround\n"); - pcie_ops.read = pcie_rd_conf_wa; - } - - /* - * Request resources. - */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("pcie_setup unable to alloc resources"); - - /* - * IORESOURCE_IO - */ - res[0].name = "PCIe I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION_PCIE_IO_BUS_BASE; - res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCIe IO resource failed\n"); - sys->resource[0] = &res[0]; - - /* - * IORESOURCE_MEM - */ - res[1].name = "PCIe Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION_PCIE_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) - panic("Request PCIe Memory resource failed\n"); - sys->resource[1] = &res[1]; - - sys->resource[2] = NULL; - sys->io_offset = 0; - - return 1; -} - -/***************************************************************************** - * PCI controller - ****************************************************************************/ -#define PCI_MODE ORION_PCI_REG(0xd00) -#define PCI_CMD ORION_PCI_REG(0xc00) -#define PCI_P2P_CONF ORION_PCI_REG(0x1d14) -#define PCI_CONF_ADDR ORION_PCI_REG(0xc78) -#define PCI_CONF_DATA ORION_PCI_REG(0xc7c) - -/* - * PCI_MODE bits - */ -#define PCI_MODE_64BIT (1 << 2) -#define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) - -/* - * PCI_CMD bits - */ -#define PCI_CMD_HOST_REORDER (1 << 29) - -/* - * PCI_P2P_CONF bits - */ -#define PCI_P2P_BUS_OFFS 16 -#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) -#define PCI_P2P_DEV_OFFS 24 -#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) - -/* - * PCI_CONF_ADDR bits - */ -#define PCI_CONF_REG(reg) ((reg) & 0xfc) -#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) -#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) -#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) -#define PCI_CONF_ADDR_EN (1 << 31) - -/* - * Internal configuration space - */ -#define PCI_CONF_FUNC_STAT_CMD 0 -#define PCI_CONF_REG_STAT_CMD 4 -#define PCIX_STAT 0x64 -#define PCIX_STAT_BUS_OFFS 8 -#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) - -/* - * PCI Address Decode Windows registers - */ -#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ - ((n) == 1) ? ORION_PCI_REG(0xd08) : \ - ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) -#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ - ((n) == 1) ? ORION_PCI_REG(0xd48) : \ - ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) -#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) -#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) - -/* - * PCI configuration helpers for BAR settings - */ -#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) -#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) -#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) - -/* - * PCI config cycles are done by programming the PCI_CONF_ADDR register - * and then reading the PCI_CONF_DATA register. Need to make sure these - * transactions are atomic. - */ -static DEFINE_SPINLOCK(orion_pci_lock); - -int orion_pci_local_bus_nr(void) -{ - u32 conf = orion_read(PCI_P2P_CONF); - return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); -} - -static int orion_pci_hw_rd_conf(int bus, int dev, u32 func, - u32 where, u32 size, u32 *val) -{ - unsigned long flags; - spin_lock_irqsave(&orion_pci_lock, flags); - - orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); - - *val = orion_read(PCI_CONF_DATA); - - if (size == 1) - *val = (*val >> (8*(where & 0x3))) & 0xff; - else if (size == 2) - *val = (*val >> (8*(where & 0x3))) & 0xffff; - - spin_unlock_irqrestore(&orion_pci_lock, flags); - - return PCIBIOS_SUCCESSFUL; -} - -static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, - u32 where, u32 size, u32 val) -{ - unsigned long flags; - int ret = PCIBIOS_SUCCESSFUL; - - spin_lock_irqsave(&orion_pci_lock, flags); - - orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); - - if (size == 4) { - __raw_writel(val, PCI_CONF_DATA); - } else if (size == 2) { - __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); - } else if (size == 1) { - __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); - } else { - ret = PCIBIOS_BAD_REGISTER_NUMBER; - } - - spin_unlock_irqrestore(&orion_pci_lock, flags); - - return ret; -} - -static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 *val) -{ - /* - * Don't go out for local device - */ - if (bus->number == orion_pci_local_bus_nr() && - PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, val); -} - -static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) -{ - if (bus->number == orion_pci_local_bus_nr() && - PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, val); -} - -static struct pci_ops pci_ops = { - .read = orion_pci_rd_conf, - .write = orion_pci_wr_conf, -}; - -static void __init orion_pci_set_bus_nr(int nr) -{ - u32 p2p = orion_read(PCI_P2P_CONF); - - if (orion_read(PCI_MODE) & PCI_MODE_PCIX) { - /* - * PCI-X mode - */ - u32 pcix_status, bus, dev; - bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; - dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; - orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); - pcix_status &= ~PCIX_STAT_BUS_MASK; - pcix_status |= (nr << PCIX_STAT_BUS_OFFS); - orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); - } else { - /* - * PCI Conventional mode - */ - p2p &= ~PCI_P2P_BUS_MASK; - p2p |= (nr << PCI_P2P_BUS_OFFS); - orion_write(PCI_P2P_CONF, p2p); - } -} - -static void __init orion_pci_master_slave_enable(void) -{ - int bus_nr, func, reg; - u32 val; - - bus_nr = orion_pci_local_bus_nr(); - func = PCI_CONF_FUNC_STAT_CMD; - reg = PCI_CONF_REG_STAT_CMD; - orion_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); - val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - orion_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); -} - -static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) -{ - u32 win_enable; - int bus; - int i; - - /* - * First, disable windows. - */ - win_enable = 0xffffffff; - orion_write(PCI_BAR_ENABLE, win_enable); - - /* - * Setup windows for DDR banks. - */ - bus = orion_pci_local_bus_nr(); - - for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; - u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); - u32 reg; - u32 val; - - /* - * Write DRAM bank base address register. - */ - reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); - orion_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); - val = (cs->base & 0xfffff000) | (val & 0xfff); - orion_pci_hw_wr_conf(bus, 0, func, reg, 4, val); - - /* - * Write DRAM bank size register. - */ - reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); - orion_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); - orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), - (cs->size - 1) & 0xfffff000); - orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), - cs->base & 0xfffff000); - - /* - * Enable decode window for this chip select. - */ - win_enable &= ~(1 << cs->cs_index); - } - - /* - * Re-enable decode windows. - */ - orion_write(PCI_BAR_ENABLE, win_enable); - - /* - * Disable automatic update of address remaping when writing to BARs. - */ - orion_setbits(PCI_ADDR_DECODE_CTRL, 1); -} - -static int __init pci_setup(struct pci_sys_data *sys) -{ - struct resource *res; - - /* - * Point PCI unit MBUS decode windows to DRAM space. - */ - orion_setup_pci_wins(&orion_mbus_dram_info); - - /* - * Master + Slave enable - */ - orion_pci_master_slave_enable(); - - /* - * Force ordering - */ - orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); - - /* - * Request resources - */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("pci_setup unable to alloc resources"); - - /* - * IORESOURCE_IO - */ - res[0].name = "PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION_PCI_IO_BUS_BASE; - res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCI IO resource failed\n"); - sys->resource[0] = &res[0]; - - /* - * IORESOURCE_MEM - */ - res[1].name = "PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION_PCI_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) - panic("Request PCI Memory resource failed\n"); - sys->resource[1] = &res[1]; - - sys->resource[2] = NULL; - sys->io_offset = 0; - - return 1; -} - - -/***************************************************************************** - * General PCIe + PCI - ****************************************************************************/ -static void __devinit rc_pci_fixup(struct pci_dev *dev) -{ - /* - * Prevent enumeration of root complex. - */ - if (dev->bus->parent == NULL && dev->devfn == 0) { - int i; - - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); - -int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) -{ - int ret = 0; - - if (nr == 0) { - orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); - ret = pcie_setup(sys); - } else if (nr == 1) { - orion_pci_set_bus_nr(sys->busnr); - ret = pci_setup(sys); - } - - return ret; -} - -struct pci_bus __init *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) -{ - struct pci_bus *bus; - - if (nr == 0) { - bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); - } else if (nr == 1) { - bus = pci_scan_bus(sys->busnr, &pci_ops, sys); - } else { - bus = NULL; - BUG(); - } - - return bus; -} diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c deleted file mode 100644 index f3e38ecda1c..00000000000 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * arch/arm/mach-orion/rd88f5182-setup.c - * - * Marvell Orion-NAS Reference Design Setup - * - * Maintainer: Ronen Shitrit - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -/***************************************************************************** - * RD-88F5182 Info - ****************************************************************************/ - -/* - * 512K NOR flash Device bus boot chip select - */ - -#define RD88F5182_NOR_BOOT_BASE 0xf4000000 -#define RD88F5182_NOR_BOOT_SIZE SZ_512K - -/* - * 16M NOR flash on Device bus chip select 1 - */ - -#define RD88F5182_NOR_BASE 0xfc000000 -#define RD88F5182_NOR_SIZE SZ_16M - -/* - * PCI - */ - -#define RD88F5182_PCI_SLOT0_OFFS 7 -#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7 -#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6 - -/* - * GPIO Debug LED - */ - -#define RD88F5182_GPIO_DBG_LED 0 - -/***************************************************************************** - * 16M NOR Flash on Device bus CS1 - ****************************************************************************/ - -static struct physmap_flash_data rd88f5182_nor_flash_data = { - .width = 1, -}; - -static struct resource rd88f5182_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = RD88F5182_NOR_BASE, - .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1, -}; - -static struct platform_device rd88f5182_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &rd88f5182_nor_flash_data, - }, - .num_resources = 1, - .resource = &rd88f5182_nor_flash_resource, -}; - -#ifdef CONFIG_LEDS - -/***************************************************************************** - * Use GPIO debug led as CPU active indication - ****************************************************************************/ - -static void rd88f5182_dbgled_event(led_event_t evt) -{ - int val; - - if (evt == led_idle_end) - val = 1; - else if (evt == led_idle_start) - val = 0; - else - return; - - gpio_set_value(RD88F5182_GPIO_DBG_LED, val); -} - -static int __init rd88f5182_dbgled_init(void) -{ - int pin; - - if (machine_is_rd88f5182()) { - pin = RD88F5182_GPIO_DBG_LED; - - if (gpio_request(pin, "DBGLED") == 0) { - if (gpio_direction_output(pin, 0) != 0) { - printk(KERN_ERR "rd88f5182_dbgled_init failed " - "to set output pin %d\n", pin); - gpio_free(pin); - return 0; - } - } else { - printk(KERN_ERR "rd88f5182_dbgled_init failed " - "to request gpio %d\n", pin); - return 0; - } - - leds_event = rd88f5182_dbgled_event; - } - return 0; -} - -__initcall(rd88f5182_dbgled_init); - -#endif - -/***************************************************************************** - * PCI - ****************************************************************************/ - -void __init rd88f5182_pci_preinit(void) -{ - int pin; - - /* - * Configure PCI GPIO IRQ pins - */ - pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; - if (gpio_request(pin, "PCI IntA") == 0) { - if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); - } else { - printk(KERN_ERR "rd88f5182_pci_preinit faield to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); - } - - pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; - if (gpio_request(pin, "PCI IntB") == 0) { - if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); - } else { - printk(KERN_ERR "rd88f5182_pci_preinit faield to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); - } -} - -static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - /* - * PCI-E isn't used on the RD2 - */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; - - /* - * PCI IRQs are connected via GPIOs - */ - switch (slot - RD88F5182_PCI_SLOT0_OFFS) { - case 0: - if (pin == 1) - return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN); - else - return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN); - default: - return -1; - } -} - -static struct hw_pci rd88f5182_pci __initdata = { - .nr_controllers = 2, - .preinit = rd88f5182_pci_preinit, - .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, - .map_irq = rd88f5182_pci_map_irq, -}; - -static int __init rd88f5182_pci_init(void) -{ - if (machine_is_rd88f5182()) - pci_common_init(&rd88f5182_pci); - - return 0; -} - -subsys_initcall(rd88f5182_pci_init); - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data rd88f5182_eth_data = { - .phy_addr = 8, - .force_phy_addr = 1, -}; - -/***************************************************************************** - * RTC DS1338 on I2C bus - ****************************************************************************/ -static struct i2c_board_info __initdata rd88f5182_i2c_rtc = { - .driver_name = "rtc-ds1307", - .type = "ds1338", - .addr = 0x68, -}; - -/***************************************************************************** - * Sata - ****************************************************************************/ -static struct mv_sata_platform_data rd88f5182_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -static struct platform_device *rd88f5182_devices[] __initdata = { - &rd88f5182_nor_flash, -}; - -static void __init rd88f5182_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion_init(); - - /* - * Setup the CPU address decode windows for our devices - */ - orion_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE); - orion_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); - - /* - * Open a special address decode windows for the PCIE WA. - */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); - - /* - * Setup Multiplexing Pins -- - * MPP[0] Debug Led (GPIO - Out) - * MPP[1] Debug Led (GPIO - Out) - * MPP[2] N/A - * MPP[3] RTC_Int (GPIO - In) - * MPP[4] GPIO - * MPP[5] GPIO - * MPP[6] PCI_intA (GPIO - In) - * MPP[7] PCI_intB (GPIO - In) - * MPP[8-11] N/A - * MPP[12] SATA 0 presence Indication - * MPP[13] SATA 1 presence Indication - * MPP[14] SATA 0 active Indication - * MPP[15] SATA 1 active indication - * MPP[16-19] Not used - * MPP[20] PCI Clock to MV88F5182 - * MPP[21] PCI Clock to mini PCI CON11 - * MPP[22] USB 0 over current indication - * MPP[23] USB 1 over current indication - * MPP[24] USB 1 over current enable - * MPP[25] USB 0 over current enable - */ - - orion_write(MPP_0_7_CTRL, 0x00000003); - orion_write(MPP_8_15_CTRL, 0x55550000); - orion_write(MPP_16_19_CTRL, 0x5555); - - orion_gpio_set_valid_pins(0x000000fb); - - platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); - i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); - orion_eth_init(&rd88f5182_eth_data); - orion_sata_init(&rd88f5182_sata_data); -} - -MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") - /* Maintainer: Ronen Shitrit */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, - .boot_params = 0x00000100, - .init_machine = rd88f5182_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, -MACHINE_END diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c deleted file mode 100644 index 8eca070006f..00000000000 --- a/arch/arm/mach-orion/ts209-setup.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * QNAP TS-109/TS-209 Board Setup - * - * Maintainer: Byron Bradley - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 -#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M - -/**************************************************************************** - * 8MiB NOR flash. The struct mtd_partition is not in the same order as the - * partitions on the device because we want to keep compatability with - * existing QNAP firmware. - * - * Layout as used by QNAP: - * [2] 0x00000000-0x00200000 : "Kernel" - * [3] 0x00200000-0x00600000 : "RootFS1" - * [4] 0x00600000-0x00700000 : "RootFS2" - * [6] 0x00700000-0x00760000 : "NAS Config" (read-only) - * [5] 0x00760000-0x00780000 : "U-Boot Config" - * [1] 0x00780000-0x00800000 : "U-Boot" (read-only) - ***************************************************************************/ -static struct mtd_partition qnap_ts209_partitions[] = { - { - .name = "U-Boot", - .size = 0x00080000, - .offset = 0x00780000, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "Kernel", - .size = 0x00200000, - .offset = 0, - }, { - .name = "RootFS1", - .size = 0x00400000, - .offset = 0x00200000, - }, { - .name = "RootFS2", - .size = 0x00100000, - .offset = 0x00600000, - }, { - .name = "U-Boot Config", - .size = 0x00020000, - .offset = 0x00760000, - }, { - .name = "NAS Config", - .size = 0x00060000, - .offset = 0x00700000, - .mask_flags = MTD_WRITEABLE, - } -}; - -static struct physmap_flash_data qnap_ts209_nor_flash_data = { - .width = 1, - .parts = qnap_ts209_partitions, - .nr_parts = ARRAY_SIZE(qnap_ts209_partitions) -}; - -static struct resource qnap_ts209_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = QNAP_TS209_NOR_BOOT_BASE, - .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device qnap_ts209_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { .platform_data = &qnap_ts209_nor_flash_data, }, - .resource = &qnap_ts209_nor_flash_resource, - .num_resources = 1, -}; - -/***************************************************************************** - * PCI - ****************************************************************************/ - -#define QNAP_TS209_PCI_SLOT0_OFFS 7 -#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6 -#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7 - -void __init qnap_ts209_pci_preinit(void) -{ - int pin; - - /* - * Configure PCI GPIO IRQ pins - */ - pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; - if (gpio_request(pin, "PCI Int1") == 0) { - if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); - } else { - printk(KERN_ERR "qnap_ts209_pci_preinit failed to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request " - "%d\n", pin); - } - - pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; - if (gpio_request(pin, "PCI Int2") == 0) { - if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQT_LOW); - } else { - printk(KERN_ERR "qnap_ts209_pci_preinit failed " - "to set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request " - "%d\n", pin); - } -} - -static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - /* - * PCIE IRQ is connected internally (not GPIO) - */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; - - /* - * PCI IRQs are connected via GPIOs - */ - switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) { - case 0: - return gpio_to_irq(QNAP_TS209_PCI_SLOT0_IRQ_PIN); - case 1: - return gpio_to_irq(QNAP_TS209_PCI_SLOT1_IRQ_PIN); - default: - return -1; - } -} - -static struct hw_pci qnap_ts209_pci __initdata = { - .nr_controllers = 2, - .preinit = qnap_ts209_pci_preinit, - .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, - .map_irq = qnap_ts209_pci_map_irq, -}; - -static int __init qnap_ts209_pci_init(void) -{ - if (machine_is_ts_x09()) - pci_common_init(&qnap_ts209_pci); - - return 0; -} - -subsys_initcall(qnap_ts209_pci_init); - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data qnap_ts209_eth_data = { - .phy_addr = 8, - .force_phy_addr = 1, -}; - -/***************************************************************************** - * RTC S35390A on I2C bus - ****************************************************************************/ - -#define TS209_RTC_GPIO 3 - -static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = { - .driver_name = "rtc-s35390a", - .addr = 0x30, - .irq = 0, -}; - -/**************************************************************************** - * GPIO Attached Keys - * Power button is attached to the PIC microcontroller - ****************************************************************************/ - -#define QNAP_TS209_GPIO_KEY_MEDIA 1 -#define QNAP_TS209_GPIO_KEY_RESET 2 - -static struct gpio_keys_button qnap_ts209_buttons[] = { - { - .code = KEY_RESTART, - .gpio = QNAP_TS209_GPIO_KEY_MEDIA, - .desc = "USB Copy Button", - .active_low = 1, - }, - { - .code = KEY_POWER, - .gpio = QNAP_TS209_GPIO_KEY_RESET, - .desc = "Reset Button", - .active_low = 1, - } -}; - -static struct gpio_keys_platform_data qnap_ts209_button_data = { - .buttons = qnap_ts209_buttons, - .nbuttons = ARRAY_SIZE(qnap_ts209_buttons), -}; - -static struct platform_device qnap_ts209_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { .platform_data = &qnap_ts209_button_data, }, -}; - -/***************************************************************************** - * SATA - ****************************************************************************/ -static struct mv_sata_platform_data qnap_ts209_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - - * General Setup - ****************************************************************************/ - -static struct platform_device *qnap_ts209_devices[] __initdata = { - &qnap_ts209_nor_flash, - &qnap_ts209_button_device, -}; - -/* - * QNAP TS-[12]09 specific power off method via UART1-attached PIC - */ - -#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) - -static void qnap_ts209_power_off(void) -{ - /* 19200 baud divisor */ - const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200)); - - pr_info("%s: triggering power-off...\n", __func__); - - /* hijack uart1 and reset into sane state (19200,8n1) */ - orion_write(UART1_REG(LCR), 0x83); - orion_write(UART1_REG(DLL), divisor & 0xff); - orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff); - orion_write(UART1_REG(LCR), 0x03); - orion_write(UART1_REG(IER), 0x00); - orion_write(UART1_REG(FCR), 0x00); - orion_write(UART1_REG(MCR), 0x00); - - /* send the power-off command 'A' to PIC */ - orion_write(UART1_REG(TX), 'A'); -} - -static void __init qnap_ts209_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion_init(); - - /* - * Setup flash mapping - */ - orion_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, - QNAP_TS209_NOR_BOOT_SIZE); - - /* - * Open a special address decode windows for the PCIE WA. - */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); - - /* - * Setup Multiplexing Pins -- - * MPP[0] Reserved - * MPP[1] USB copy button (0 active) - * MPP[2] Load defaults button (0 active) - * MPP[3] GPIO RTC - * MPP[4-5] Reserved - * MPP[6] PCI Int A - * MPP[7] PCI Int B - * MPP[8-11] Reserved - * MPP[12] SATA 0 presence - * MPP[13] SATA 1 presence - * MPP[14] SATA 0 active - * MPP[15] SATA 1 active - * MPP[16] UART1 RXD - * MPP[17] UART1 TXD - * MPP[18] SW_RST (0 active) - * MPP[19] Reserved - * MPP[20] PCI clock 0 - * MPP[21] PCI clock 1 - * MPP[22] USB 0 over current - * MPP[23-25] Reserved - */ - orion_write(MPP_0_7_CTRL, 0x3); - orion_write(MPP_8_15_CTRL, 0x55550000); - orion_write(MPP_16_19_CTRL, 0x5500); - orion_gpio_set_valid_pins(0x3cc0fff); - - /* register ts209 specific power-off method */ - pm_power_off = qnap_ts209_power_off; - - platform_add_devices(qnap_ts209_devices, - ARRAY_SIZE(qnap_ts209_devices)); - - /* Get RTC IRQ and register the chip */ - if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) { - if (gpio_direction_input(TS209_RTC_GPIO) == 0) - qnap_ts209_i2c_rtc.irq = gpio_to_irq(TS209_RTC_GPIO); - else - gpio_free(TS209_RTC_GPIO); - } - if (qnap_ts209_i2c_rtc.irq == 0) - pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); - i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); - - orion_eth_init(&qnap_ts209_eth_data); - orion_sata_init(&qnap_ts209_sata_data); -} - -MACHINE_START(TS209, "QNAP TS-109/TS-209") - /* Maintainer: Byron Bradley */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, - .boot_params = 0x00000100, - .init_machine = qnap_ts209_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, - .fixup = tag_fixup_mem32, -MACHINE_END diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig new file mode 100644 index 00000000000..01c66957d8f --- /dev/null +++ b/arch/arm/mach-orion5x/Kconfig @@ -0,0 +1,41 @@ +if ARCH_ORION5X + +menu "Orion Implementations" + +config MACH_DB88F5281 + bool "Marvell Orion-2 Development Board" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Marvell Orion-2 (88F5281) Development Board + +config MACH_RD88F5182 + bool "Marvell Orion-NAS Reference Design" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Marvell Orion-NAS (88F5182) RD2 + +config MACH_KUROBOX_PRO + bool "KuroBox Pro" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + KuroBox Pro platform. + +config MACH_DNS323 + bool "D-Link DNS-323" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + D-Link DNS-323 platform. + +config MACH_TS209 + bool "QNAP TS-109/TS-209" + help + Say 'Y' here if you want your kernel to support the + QNAP TS-109/TS-209 platform. + +endmenu + +endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile new file mode 100644 index 00000000000..d894caa5060 --- /dev/null +++ b/arch/arm/mach-orion5x/Makefile @@ -0,0 +1,6 @@ +obj-y += common.o addr-map.o pci.o gpio.o irq.o +obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o +obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o +obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o +obj-$(CONFIG_MACH_DNS323) += dns323-setup.o +obj-$(CONFIG_MACH_TS209) += ts209-setup.o diff --git a/arch/arm/mach-orion5x/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot new file mode 100644 index 00000000000..67039c3e0c4 --- /dev/null +++ b/arch/arm/mach-orion5x/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c new file mode 100644 index 00000000000..6b179371e0a --- /dev/null +++ b/arch/arm/mach-orion5x/addr-map.c @@ -0,0 +1,240 @@ +/* + * arch/arm/mach-orion5x/addr-map.c + * + * Address map functions for Marvell Orion 5x SoCs + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include "common.h" + +/* + * The Orion has fully programable address map. There's a separate address + * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, + * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own + * address decode windows that allow it to access any of the Orion resources. + * + * CPU address decoding -- + * Linux assumes that it is the boot loader that already setup the access to + * DDR and internal registers. + * Setup access to PCI and PCI-E IO/MEM space is issued by this file. + * Setup access to various devices located on the device bus interface (e.g. + * flashes, RTC, etc) should be issued by machine-setup.c according to + * specific board population (by using orion5x_setup_*_win()). + * + * Non-CPU Masters address decoding -- + * Unlike the CPU, we setup the access from Orion's master interfaces to DDR + * banks only (the typical use case). + * Setup access for each master to DDR is issued by common.c. + * + * Note: although orion_setbits() and orion_clrbits() are not atomic + * no locking is necessary here since code in this file is only called + * at boot time when there is no concurrency issues. + */ + +/* + * Generic Address Decode Windows bit settings + */ +#define TARGET_DDR 0 +#define TARGET_DEV_BUS 1 +#define TARGET_PCI 3 +#define TARGET_PCIE 4 +#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ + ((n) == 1) ? 0xd : \ + ((n) == 2) ? 0xb : \ + ((n) == 3) ? 0x7 : 0xf) +#define ATTR_PCIE_MEM 0x59 +#define ATTR_PCIE_IO 0x51 +#define ATTR_PCIE_WA 0x79 +#define ATTR_PCI_MEM 0x59 +#define ATTR_PCI_IO 0x51 +#define ATTR_DEV_CS0 0x1e +#define ATTR_DEV_CS1 0x1d +#define ATTR_DEV_CS2 0x1b +#define ATTR_DEV_BOOT 0xf +#define WIN_EN 1 + +/* + * Helpers to get DDR bank info + */ +#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) +#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) +#define DDR_MAX_CS 4 +#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) +#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) +#define DDR_BANK_EN 1 + +/* + * CPU Address Decode Windows registers + */ +#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) +#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) +#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) +#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) + +/* + * Gigabit Ethernet Address Decode Windows registers + */ +#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8)) +#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8)) +#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4)) +#define ETH_WIN_EN ORION5X_ETH_REG(0x290) +#define ETH_WIN_PROT ORION5X_ETH_REG(0x294) +#define ETH_MAX_WIN 6 +#define ETH_MAX_REMAP_WIN 4 + + +struct mbus_dram_target_info orion5x_mbus_dram_info; + +static int __init orion5x_cpu_win_can_remap(int win) +{ + u32 dev, rev; + + orion5x_pcie_id(&dev, &rev); + if ((dev == MV88F5281_DEV_ID && win < 4) + || (dev == MV88F5182_DEV_ID && win < 2) + || (dev == MV88F5181_DEV_ID && win < 2)) + return 1; + + return 0; +} + +static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) +{ + orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); + orion5x_write(CPU_WIN_CTRL(win), + ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); + + if (orion5x_cpu_win_can_remap(win)) { + if (remap < 0) + remap = base; + + orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); + orion5x_write(CPU_WIN_REMAP_HI(win), 0); + } +} + +void __init orion5x_setup_cpu_mbus_bridge(void) +{ + int i; + int cs; + + /* + * First, disable and clear windows. + */ + for (i = 0; i < 8; i++) { + orion5x_write(CPU_WIN_BASE(i), 0); + orion5x_write(CPU_WIN_CTRL(i), 0); + if (orion5x_cpu_win_can_remap(i)) { + orion5x_write(CPU_WIN_REMAP_LO(i), 0); + orion5x_write(CPU_WIN_REMAP_HI(i), 0); + } + } + + /* + * Setup windows for PCI+PCIe IO+MEM space. + */ + setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); + setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, + TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); + setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, -1); + setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, + TARGET_PCI, ATTR_PCI_MEM, -1); + + /* + * Setup MBUS dram target info. + */ + orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(DDR_BASE_CS(i)); + u32 size = readl(DDR_SIZE_CS(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &orion5x_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xff000000; + w->size = (size | 0x00ffffff) + 1; + } + } + orion5x_mbus_dram_info.num_cs = cs; +} + +void __init orion5x_setup_dev_boot_win(u32 base, u32 size) +{ + setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); +} + +void __init orion5x_setup_dev0_win(u32 base, u32 size) +{ + setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); +} + +void __init orion5x_setup_dev1_win(u32 base, u32 size) +{ + setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); +} + +void __init orion5x_setup_dev2_win(u32 base, u32 size) +{ + setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); +} + +void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) +{ + setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); +} + +void __init orion5x_setup_eth_wins(void) +{ + int i; + + /* + * First, disable and clear windows + */ + for (i = 0; i < ETH_MAX_WIN; i++) { + orion5x_write(ETH_WIN_BASE(i), 0); + orion5x_write(ETH_WIN_SIZE(i), 0); + orion5x_setbits(ETH_WIN_EN, 1 << i); + orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); + if (i < ETH_MAX_REMAP_WIN) + orion5x_write(ETH_WIN_REMAP(i), 0); + } + + /* + * Setup windows for DDR banks. + */ + for (i = 0; i < DDR_MAX_CS; i++) { + u32 base, size; + size = orion5x_read(DDR_SIZE_CS(i)); + base = orion5x_read(DDR_BASE_CS(i)); + if (size & DDR_BANK_EN) { + base = DDR_REG_TO_BASE(base); + size = DDR_REG_TO_SIZE(size); + orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); + orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) | + (ATTR_DDR_CS(i) << 8) | + TARGET_DDR); + orion5x_clrbits(ETH_WIN_EN, 1 << i); + orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); + } + } +} diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c new file mode 100644 index 00000000000..439c7784af0 --- /dev/null +++ b/arch/arm/mach-orion5x/common.c @@ -0,0 +1,391 @@ +/* + * arch/arm/mach-orion5x/common.c + * + * Core functions for Marvell Orion 5x SoCs + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc orion5x_io_desc[] __initdata = { + { + .virtual = ORION5X_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), + .length = ORION5X_REGS_SIZE, + .type = MT_DEVICE + }, + { + .virtual = ORION5X_PCIE_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), + .length = ORION5X_PCIE_IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = ORION5X_PCI_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), + .length = ORION5X_PCI_IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = ORION5X_PCIE_WA_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), + .length = ORION5X_PCIE_WA_SIZE, + .type = MT_DEVICE + }, +}; + +void __init orion5x_map_io(void) +{ + iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); +} + +/***************************************************************************** + * UART + ****************************************************************************/ + +static struct resource orion5x_uart_resources[] = { + { + .start = UART0_PHYS_BASE, + .end = UART0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_ORION5X_UART0, + .end = IRQ_ORION5X_UART0, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART1_PHYS_BASE, + .end = UART1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_ORION5X_UART1, + .end = IRQ_ORION5X_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct plat_serial8250_port orion5x_uart_data[] = { + { + .mapbase = UART0_PHYS_BASE, + .membase = (char *)UART0_VIRT_BASE, + .irq = IRQ_ORION5X_UART0, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = ORION5X_TCLK, + }, + { + .mapbase = UART1_PHYS_BASE, + .membase = (char *)UART1_VIRT_BASE, + .irq = IRQ_ORION5X_UART1, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = ORION5X_TCLK, + }, + { }, +}; + +static struct platform_device orion5x_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = orion5x_uart_data, + }, + .resource = orion5x_uart_resources, + .num_resources = ARRAY_SIZE(orion5x_uart_resources), +}; + +/******************************************************************************* + * USB Controller - 2 interfaces + ******************************************************************************/ + +static struct resource orion5x_ehci0_resources[] = { + { + .start = ORION5X_USB0_PHYS_BASE, + .end = ORION5X_USB0_PHYS_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_ORION5X_USB0_CTRL, + .end = IRQ_ORION5X_USB0_CTRL, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource orion5x_ehci1_resources[] = { + { + .start = ORION5X_USB1_PHYS_BASE, + .end = ORION5X_USB1_PHYS_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_ORION5X_USB1_CTRL, + .end = IRQ_ORION5X_USB1_CTRL, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct orion_ehci_data orion5x_ehci_data = { + .dram = &orion5x_mbus_dram_info, +}; + +static u64 ehci_dmamask = 0xffffffffUL; + +static struct platform_device orion5x_ehci0 = { + .name = "orion-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &orion5x_ehci_data, + }, + .resource = orion5x_ehci0_resources, + .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), +}; + +static struct platform_device orion5x_ehci1 = { + .name = "orion-ehci", + .id = 1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &orion5x_ehci_data, + }, + .resource = orion5x_ehci1_resources, + .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), +}; + +/***************************************************************************** + * Gigabit Ethernet port + * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) + ****************************************************************************/ + +static struct resource orion5x_eth_shared_resources[] = { + { + .start = ORION5X_ETH_PHYS_BASE + 0x2000, + .end = ORION5X_ETH_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device orion5x_eth_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .num_resources = 1, + .resource = orion5x_eth_shared_resources, +}; + +static struct resource orion5x_eth_resources[] = { + { + .name = "eth irq", + .start = IRQ_ORION5X_ETH_SUM, + .end = IRQ_ORION5X_ETH_SUM, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device orion5x_eth = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = orion5x_eth_resources, +}; + +void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) +{ + orion5x_eth.dev.platform_data = eth_data; + platform_device_register(&orion5x_eth_shared); + platform_device_register(&orion5x_eth); +} + +/***************************************************************************** + * I2C controller + * (The Orion and Discovery (MV643xx) families share the same I2C controller) + ****************************************************************************/ + +static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { + .freq_m = 8, /* assumes 166 MHz TCLK */ + .freq_n = 3, + .timeout = 1000, /* Default timeout of 1 second */ +}; + +static struct resource orion5x_i2c_resources[] = { + { + .name = "i2c base", + .start = I2C_PHYS_BASE, + .end = I2C_PHYS_BASE + 0x20 -1, + .flags = IORESOURCE_MEM, + }, + { + .name = "i2c irq", + .start = IRQ_ORION5X_I2C, + .end = IRQ_ORION5X_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion5x_i2c = { + .name = MV64XXX_I2C_CTLR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(orion5x_i2c_resources), + .resource = orion5x_i2c_resources, + .dev = { + .platform_data = &orion5x_i2c_pdata, + }, +}; + +/***************************************************************************** + * Sata port + ****************************************************************************/ +static struct resource orion5x_sata_resources[] = { + { + .name = "sata base", + .start = ORION5X_SATA_PHYS_BASE, + .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "sata irq", + .start = IRQ_ORION5X_SATA, + .end = IRQ_ORION5X_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion5x_sata = { + .name = "sata_mv", + .id = 0, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(orion5x_sata_resources), + .resource = orion5x_sata_resources, +}; + +void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) +{ + sata_data->dram = &orion5x_mbus_dram_info; + orion5x_sata.dev.platform_data = sata_data; + platform_device_register(&orion5x_sata); +} + +/***************************************************************************** + * Time handling + ****************************************************************************/ + +static void orion5x_timer_init(void) +{ + orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); +} + +struct sys_timer orion5x_timer = { + .init = orion5x_timer_init, +}; + +/***************************************************************************** + * General + ****************************************************************************/ + +/* + * Identify device ID and rev from PCIE configuration header space '0'. + */ +static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) +{ + orion5x_pcie_id(dev, rev); + + if (*dev == MV88F5281_DEV_ID) { + if (*rev == MV88F5281_REV_D2) { + *dev_name = "MV88F5281-D2"; + } else if (*rev == MV88F5281_REV_D1) { + *dev_name = "MV88F5281-D1"; + } else { + *dev_name = "MV88F5281-Rev-Unsupported"; + } + } else if (*dev == MV88F5182_DEV_ID) { + if (*rev == MV88F5182_REV_A2) { + *dev_name = "MV88F5182-A2"; + } else { + *dev_name = "MV88F5182-Rev-Unsupported"; + } + } else if (*dev == MV88F5181_DEV_ID) { + if (*rev == MV88F5181_REV_B1) { + *dev_name = "MV88F5181-Rev-B1"; + } else { + *dev_name = "MV88F5181-Rev-Unsupported"; + } + } else { + *dev_name = "Device-Unknown"; + } +} + +void __init orion5x_init(void) +{ + char *dev_name; + u32 dev, rev; + + orion5x_id(&dev, &rev, &dev_name); + printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK); + + /* + * Setup Orion address map + */ + orion5x_setup_cpu_mbus_bridge(); + orion5x_setup_eth_wins(); + + /* + * Register devices. + */ + platform_device_register(&orion5x_uart); + platform_device_register(&orion5x_ehci0); + if (dev == MV88F5182_DEV_ID) + platform_device_register(&orion5x_ehci1); + platform_device_register(&orion5x_i2c); +} + +/* + * Many orion-based systems have buggy bootloader implementations. + * This is a common fixup for bogus memory tags. + */ +void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t, + char **from, struct meminfo *meminfo) +{ + for (; t->hdr.size; t = tag_next(t)) + if (t->hdr.tag == ATAG_MEM && + (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || + t->u.mem.start & ~PAGE_MASK)) { + printk(KERN_WARNING + "Clearing invalid memory bank %dKB@0x%08x\n", + t->u.mem.size / 1024, t->u.mem.start); + t->hdr.tag = 0; + } +} diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h new file mode 100644 index 00000000000..f4c4c9a72a7 --- /dev/null +++ b/arch/arm/mach-orion5x/common.h @@ -0,0 +1,72 @@ +#ifndef __ARCH_ORION5X_COMMON_H +#define __ARCH_ORION5X_COMMON_H + +/* + * Basic Orion init functions used early by machine-setup. + */ + +void orion5x_map_io(void); +void orion5x_init_irq(void); +void orion5x_init(void); +extern struct sys_timer orion5x_timer; + +/* + * Enumerations and functions for Orion windows mapping. Used by Orion core + * functions to map its interfaces and by the machine-setup to map its on- + * board devices. Details in /mach-orion/addr-map.c + */ +extern struct mbus_dram_target_info orion5x_mbus_dram_info; +void orion5x_setup_cpu_mbus_bridge(void); +void orion5x_setup_dev_boot_win(u32 base, u32 size); +void orion5x_setup_dev0_win(u32 base, u32 size); +void orion5x_setup_dev1_win(u32 base, u32 size); +void orion5x_setup_dev2_win(u32 base, u32 size); +void orion5x_setup_pcie_wa_win(u32 base, u32 size); +void orion5x_setup_eth_wins(void); + +/* + * Shared code used internally by other Orion core functions. + * (/mach-orion/pci.c) + */ + +struct pci_sys_data; +struct pci_bus; + +void orion5x_pcie_id(u32 *dev, u32 *rev); +int orion5x_pcie_local_bus_nr(void); +int orion5x_pci_local_bus_nr(void); +int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); + +/* + * Valid GPIO pins according to MPP setup, used by machine-setup. + * (/mach-orion/gpio.c). + */ + +void orion5x_gpio_set_valid_pins(u32 pins); +void gpio_display(void); /* debug */ + +/* + * Pull in Orion Ethernet platform_data, used by machine-setup + */ + +struct mv643xx_eth_platform_data; + +void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); + +/* + * Orion Sata platform_data, used by machine-setup + */ + +struct mv_sata_platform_data; + +void orion5x_sata_init(struct mv_sata_platform_data *sata_data); + +struct machine_desc; +struct meminfo; +struct tag; +extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, + char **, struct meminfo *); + + +#endif diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c new file mode 100644 index 00000000000..872aed37232 --- /dev/null +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -0,0 +1,361 @@ +/* + * arch/arm/mach-orion5x/db88f5281-setup.c + * + * Marvell Orion-2 Development Board Setup + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * DB-88F5281 on board devices + ****************************************************************************/ + +/* + * 512K NOR flash Device bus boot chip select + */ + +#define DB88F5281_NOR_BOOT_BASE 0xf4000000 +#define DB88F5281_NOR_BOOT_SIZE SZ_512K + +/* + * 7-Segment on Device bus chip select 0 + */ + +#define DB88F5281_7SEG_BASE 0xfa000000 +#define DB88F5281_7SEG_SIZE SZ_1K + +/* + * 32M NOR flash on Device bus chip select 1 + */ + +#define DB88F5281_NOR_BASE 0xfc000000 +#define DB88F5281_NOR_SIZE SZ_32M + +/* + * 32M NAND flash on Device bus chip select 2 + */ + +#define DB88F5281_NAND_BASE 0xfa800000 +#define DB88F5281_NAND_SIZE SZ_1K + +/* + * PCI + */ + +#define DB88F5281_PCI_SLOT0_OFFS 7 +#define DB88F5281_PCI_SLOT0_IRQ_PIN 12 +#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13 + +/***************************************************************************** + * 512M NOR Flash on Device bus Boot CS + ****************************************************************************/ + +static struct physmap_flash_data db88f5281_boot_flash_data = { + .width = 1, /* 8 bit bus width */ +}; + +static struct resource db88f5281_boot_flash_resource = { + .flags = IORESOURCE_MEM, + .start = DB88F5281_NOR_BOOT_BASE, + .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device db88f5281_boot_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &db88f5281_boot_flash_data, + }, + .num_resources = 1, + .resource = &db88f5281_boot_flash_resource, +}; + +/***************************************************************************** + * 32M NOR Flash on Device bus CS1 + ****************************************************************************/ + +static struct physmap_flash_data db88f5281_nor_flash_data = { + .width = 4, /* 32 bit bus width */ +}; + +static struct resource db88f5281_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = DB88F5281_NOR_BASE, + .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1, +}; + +static struct platform_device db88f5281_nor_flash = { + .name = "physmap-flash", + .id = 1, + .dev = { + .platform_data = &db88f5281_nor_flash_data, + }, + .num_resources = 1, + .resource = &db88f5281_nor_flash_resource, +}; + +/***************************************************************************** + * 32M NAND Flash on Device bus CS2 + ****************************************************************************/ + +static struct mtd_partition db88f5281_nand_parts[] = { + { + .name = "kernel", + .offset = 0, + .size = SZ_2M, + }, + { + .name = "root", + .offset = SZ_2M, + .size = (SZ_16M - SZ_2M), + }, + { + .name = "user", + .offset = SZ_16M, + .size = SZ_8M, + }, + { + .name = "recovery", + .offset = (SZ_16M + SZ_8M), + .size = SZ_8M, + }, +}; + +static struct resource db88f5281_nand_resource = { + .flags = IORESOURCE_MEM, + .start = DB88F5281_NAND_BASE, + .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1, +}; + +static struct orion_nand_data db88f5281_nand_data = { + .parts = db88f5281_nand_parts, + .nr_parts = ARRAY_SIZE(db88f5281_nand_parts), + .cle = 0, + .ale = 1, + .width = 8, +}; + +static struct platform_device db88f5281_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &db88f5281_nand_data, + }, + .resource = &db88f5281_nand_resource, + .num_resources = 1, +}; + +/***************************************************************************** + * 7-Segment on Device bus CS0 + * Dummy counter every 2 sec + ****************************************************************************/ + +static void __iomem *db88f5281_7seg; +static struct timer_list db88f5281_timer; + +static void db88f5281_7seg_event(unsigned long data) +{ + static int count = 0; + writel(0, db88f5281_7seg + (count << 4)); + count = (count + 1) & 7; + mod_timer(&db88f5281_timer, jiffies + 2 * HZ); +} + +static int __init db88f5281_7seg_init(void) +{ + if (machine_is_db88f5281()) { + db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE, + DB88F5281_7SEG_SIZE); + if (!db88f5281_7seg) { + printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n"); + return -EIO; + } + setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0); + mod_timer(&db88f5281_timer, jiffies + 2 * HZ); + } + + return 0; +} + +__initcall(db88f5281_7seg_init); + +/***************************************************************************** + * PCI + ****************************************************************************/ + +void __init db88f5281_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = DB88F5281_PCI_SLOT0_IRQ_PIN; + if (gpio_request(pin, "PCI Int1") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "db88f5281_pci_preinit faield to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); + } + + pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; + if (gpio_request(pin, "PCI Int2") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "db88f5281_pci_preinit faield " + "to set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); + } +} + +static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* + * PCIE IRQ is connected internally (not GPIO) + */ + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; + + /* + * PCI IRQs are connected via GPIOs + */ + switch (slot - DB88F5281_PCI_SLOT0_OFFS) { + case 0: + return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN); + case 1: + case 2: + return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN); + default: + return -1; + } +} + +static struct hw_pci db88f5281_pci __initdata = { + .nr_controllers = 2, + .preinit = db88f5281_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = db88f5281_pci_map_irq, +}; + +static int __init db88f5281_pci_init(void) +{ + if (machine_is_db88f5281()) + pci_common_init(&db88f5281_pci); + + return 0; +} + +subsys_initcall(db88f5281_pci_init); + +/***************************************************************************** + * Ethernet + ****************************************************************************/ +static struct mv643xx_eth_platform_data db88f5281_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/***************************************************************************** + * RTC DS1339 on I2C bus + ****************************************************************************/ +static struct i2c_board_info __initdata db88f5281_i2c_rtc = { + .driver_name = "rtc-ds1307", + .type = "ds1339", + .addr = 0x68, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +static struct platform_device *db88f5281_devs[] __initdata = { + &db88f5281_boot_flash, + &db88f5281_nor_flash, + &db88f5281_nand_flash, +}; + +static void __init db88f5281_init(void) +{ + /* + * Basic Orion setup. Need to be called early. + */ + orion5x_init(); + + /* + * Setup the CPU address decode windows for our on-board devices + */ + orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, + DB88F5281_NOR_BOOT_SIZE); + orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); + orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); + orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); + + /* + * Setup Multiplexing Pins: + * MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input) + * MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2] + * MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3] + * MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1) + * MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3) + * MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator) + * MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2) + * MPP14: NAND_REn[2] MPP15: NAND_WEn[2] + * MPP16: UART1_RX MPP17: UART1_TX + * MPP18: UART1_CTS MPP19: UART1_RTS + * MPP-DEV: DEV_D[16:31] + */ + orion5x_write(MPP_0_7_CTRL, 0x00222203); + orion5x_write(MPP_8_15_CTRL, 0x44000000); + orion5x_write(MPP_16_19_CTRL, 0); + orion5x_write(MPP_DEV_CTRL, 0); + + orion5x_gpio_set_valid_pins(0x00003fc3); + + platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); + i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); + orion5x_eth_init(&db88f5281_eth_data); +} + +MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") + /* Maintainer: Tzachi Perelstein */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = db88f5281_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, +MACHINE_END diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c new file mode 100644 index 00000000000..d67790ef236 --- /dev/null +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -0,0 +1,320 @@ +/* + * arch/arm/mach-orion5x/dns323-setup.c + * + * Copyright (C) 2007 Herbert Valerio Riedel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +#define DNS323_GPIO_LED_RIGHT_AMBER 1 +#define DNS323_GPIO_LED_LEFT_AMBER 2 +#define DNS323_GPIO_LED_POWER 5 +#define DNS323_GPIO_OVERTEMP 6 +#define DNS323_GPIO_RTC 7 +#define DNS323_GPIO_POWER_OFF 8 +#define DNS323_GPIO_KEY_POWER 9 +#define DNS323_GPIO_KEY_RESET 10 + +/**************************************************************************** + * PCI setup + */ + +static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* PCI-E */ + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; + + pr_err("%s: requested mapping for unknown bus\n", __func__); + + return -1; +} + +static struct hw_pci dns323_pci __initdata = { + .nr_controllers = 1, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = dns323_pci_map_irq, +}; + +static int __init dns323_pci_init(void) +{ + if (machine_is_dns323()) + pci_common_init(&dns323_pci); + + return 0; +} + +subsys_initcall(dns323_pci_init); + +/**************************************************************************** + * Ethernet + */ + +static struct mv643xx_eth_platform_data dns323_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/**************************************************************************** + * 8MiB NOR flash (Spansion S29GL064M90TFIR4) + * + * Layout as used by D-Link: + * 0x00000000-0x00010000 : "MTD1" + * 0x00010000-0x00020000 : "MTD2" + * 0x00020000-0x001a0000 : "Linux Kernel" + * 0x001a0000-0x007d0000 : "File System" + * 0x007d0000-0x00800000 : "u-boot" + */ + +#define DNS323_NOR_BOOT_BASE 0xf4000000 +#define DNS323_NOR_BOOT_SIZE SZ_8M + +static struct mtd_partition dns323_partitions[] = { + { + .name = "MTD1", + .size = 0x00010000, + .offset = 0, + }, { + .name = "MTD2", + .size = 0x00010000, + .offset = 0x00010000, + }, { + .name = "Linux Kernel", + .size = 0x00180000, + .offset = 0x00020000, + }, { + .name = "File System", + .size = 0x00630000, + .offset = 0x001A0000, + }, { + .name = "u-boot", + .size = 0x00030000, + .offset = 0x007d0000, + } +}; + +static struct physmap_flash_data dns323_nor_flash_data = { + .width = 1, + .parts = dns323_partitions, + .nr_parts = ARRAY_SIZE(dns323_partitions) +}; + +static struct resource dns323_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = DNS323_NOR_BOOT_BASE, + .end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device dns323_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { .platform_data = &dns323_nor_flash_data, }, + .resource = &dns323_nor_flash_resource, + .num_resources = 1, +}; + +/**************************************************************************** + * GPIO LEDs (simple - doesn't use hardware blinking support) + */ + +static struct gpio_led dns323_leds[] = { + { + .name = "power:blue", + .gpio = DNS323_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "right:amber", + .gpio = DNS323_GPIO_LED_RIGHT_AMBER, + .active_low = 1, + }, { + .name = "left:amber", + .gpio = DNS323_GPIO_LED_LEFT_AMBER, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data dns323_led_data = { + .num_leds = ARRAY_SIZE(dns323_leds), + .leds = dns323_leds, +}; + +static struct platform_device dns323_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { .platform_data = &dns323_led_data, }, +}; + +/**************************************************************************** + * GPIO Attached Keys + */ + +static struct gpio_keys_button dns323_buttons[] = { + { + .code = KEY_RESTART, + .gpio = DNS323_GPIO_KEY_RESET, + .desc = "Reset Button", + .active_low = 1, + }, + { + .code = KEY_POWER, + .gpio = DNS323_GPIO_KEY_POWER, + .desc = "Power Button", + .active_low = 1, + } +}; + +static struct gpio_keys_platform_data dns323_button_data = { + .buttons = dns323_buttons, + .nbuttons = ARRAY_SIZE(dns323_buttons), +}; + +static struct platform_device dns323_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { .platform_data = &dns323_button_data, }, +}; + +/**************************************************************************** + * General Setup + */ + +static struct platform_device *dns323_plat_devices[] __initdata = { + &dns323_nor_flash, + &dns323_gpio_leds, + &dns323_button_device, +}; + +/* + * On the DNS-323 the following devices are attached via I2C: + * + * i2c addr | chip | description + * 0x3e | GMT G760Af | fan speed PWM controller + * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) + * 0x68 | ST M41T80 | RTC w/ alarm + */ +static struct i2c_board_info __initdata dns323_i2c_devices[] = { + { + I2C_BOARD_INFO("g760a", 0x3e), + .type = "g760a", + }, +#if 0 + /* this entry requires the new-style driver model lm75 driver, + * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */ + { + I2C_BOARD_INFO("lm75", 0x48), + .type = "g751", + }, +#endif + { + I2C_BOARD_INFO("rtc-m41t80", 0x68), + .type = "m41t80", + } +}; + +/* DNS-323 specific power off method */ +static void dns323_power_off(void) +{ + pr_info("%s: triggering power-off...\n", __func__); + gpio_set_value(DNS323_GPIO_POWER_OFF, 1); +} + +static void __init dns323_init(void) +{ + /* Setup basic Orion functions. Need to be called early. */ + orion5x_init(); + + /* setup flash mapping + * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 + */ + orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); + + /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE + * + * Open a special address decode windows for the PCIE WA. + */ + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); + + /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ + orion5x_write(MPP_0_7_CTRL, 0); + orion5x_write(MPP_8_15_CTRL, 0); + orion5x_write(MPP_16_19_CTRL, 0); + orion5x_write(MPP_DEV_CTRL, 0); + + /* Define used GPIO pins + + GPIO Map: + + | 0 | | PEX_RST_OUT (not controlled by GPIO) + | 1 | Out | right amber LED (= sata ch0 LED) (low-active) + | 2 | Out | left amber LED (= sata ch1 LED) (low-active) + | 3 | Out | //unknown// + | 4 | Out | power button LED (low-active, together with pin #5) + | 5 | Out | power button LED (low-active, together with pin #4) + | 6 | In | GMT G751-2f overtemp. shutdown signal (low-active) + | 7 | In | M41T80 nIRQ/OUT/SQW signal + | 8 | Out | triggers power off (high-active) + | 9 | In | power button switch (low-active) + | 10 | In | reset button switch (low-active) + | 11 | Out | //unknown// + | 12 | Out | //unknown// + | 13 | Out | //unknown// + | 14 | Out | //unknown// + | 15 | Out | //unknown// + */ + orion5x_gpio_set_valid_pins(0x07f6); + + /* register dns323 specific power-off method */ + if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) + || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)) + pr_err("DNS323: failed to setup power-off GPIO\n"); + + pm_power_off = dns323_power_off; + + /* register flash and other platform devices */ + platform_add_devices(dns323_plat_devices, + ARRAY_SIZE(dns323_plat_devices)); + + i2c_register_board_info(0, dns323_i2c_devices, + ARRAY_SIZE(dns323_i2c_devices)); + + orion5x_eth_init(&dns323_eth_data); +} + +/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ +MACHINE_START(DNS323, "D-Link DNS-323") + /* Maintainer: Herbert Valerio Riedel */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = dns323_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c new file mode 100644 index 00000000000..8108c316c42 --- /dev/null +++ b/arch/arm/mach-orion5x/gpio.c @@ -0,0 +1,226 @@ +/* + * arch/arm/mach-orion5x/gpio.c + * + * GPIO functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +static DEFINE_SPINLOCK(gpio_lock); +static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; +static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ + +void __init orion5x_gpio_set_valid_pins(u32 pins) +{ + gpio_valid[0] = pins; +} + +/* + * GENERIC_GPIO primitives + */ +int gpio_direction_input(unsigned pin) +{ + unsigned long flags; + + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __func__, pin); + return -EINVAL; + } + + spin_lock_irqsave(&gpio_lock, flags); + + /* + * Some callers might have not used the gpio_request(), + * so flag this pin as requested now. + */ + if (!gpio_label[pin]) + gpio_label[pin] = "?"; + + orion5x_setbits(GPIO_IO_CONF, 1 << pin); + + spin_unlock_irqrestore(&gpio_lock, flags); + return 0; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned pin, int value) +{ + unsigned long flags; + int mask; + + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __func__, pin); + return -EINVAL; + } + + spin_lock_irqsave(&gpio_lock, flags); + + /* + * Some callers might have not used the gpio_request(), + * so flag this pin as requested now. + */ + if (!gpio_label[pin]) + gpio_label[pin] = "?"; + + mask = 1 << pin; + orion5x_clrbits(GPIO_BLINK_EN, mask); + if (value) + orion5x_setbits(GPIO_OUT, mask); + else + orion5x_clrbits(GPIO_OUT, mask); + orion5x_clrbits(GPIO_IO_CONF, mask); + + spin_unlock_irqrestore(&gpio_lock, flags); + return 0; +} +EXPORT_SYMBOL(gpio_direction_output); + +int gpio_get_value(unsigned pin) +{ + int val, mask = 1 << pin; + + if (orion5x_read(GPIO_IO_CONF) & mask) + val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); + else + val = orion5x_read(GPIO_OUT); + + return val & mask; +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned pin, int value) +{ + unsigned long flags; + int mask = 1 << pin; + + spin_lock_irqsave(&gpio_lock, flags); + + orion5x_clrbits(GPIO_BLINK_EN, mask); + if (value) + orion5x_setbits(GPIO_OUT, mask); + else + orion5x_clrbits(GPIO_OUT, mask); + + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(gpio_set_value); + +void orion5x_gpio_set_blink(unsigned pin, int blink) +{ + unsigned long flags; + int mask = 1 << pin; + + spin_lock_irqsave(&gpio_lock, flags); + + orion5x_clrbits(GPIO_OUT, mask); + if (blink) + orion5x_setbits(GPIO_BLINK_EN, mask); + else + orion5x_clrbits(GPIO_BLINK_EN, mask); + + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(orion5x_gpio_set_blink); + +int gpio_request(unsigned pin, const char *label) +{ + int ret = 0; + unsigned long flags; + + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __func__, pin); + return -EINVAL; + } + + spin_lock_irqsave(&gpio_lock, flags); + + if (gpio_label[pin]) { + pr_debug("%s: GPIO %d already used as %s\n", + __func__, pin, gpio_label[pin]); + ret = -EBUSY; + } else + gpio_label[pin] = label ? label : "?"; + + spin_unlock_irqrestore(&gpio_lock, flags); + return ret; +} +EXPORT_SYMBOL(gpio_request); + +void gpio_free(unsigned pin) +{ + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __func__, pin); + return; + } + + if (!gpio_label[pin]) + pr_warning("%s: GPIO %d already freed\n", __func__, pin); + else + gpio_label[pin] = NULL; +} +EXPORT_SYMBOL(gpio_free); + +/* Debug helper */ +void gpio_display(void) +{ + int i; + + for (i = 0; i < GPIO_MAX; i++) { + printk(KERN_DEBUG "Pin-%d: ", i); + + if (!test_bit(i, gpio_valid)) { + printk("non-GPIO\n"); + } else if (!gpio_label[i]) { + printk("GPIO, free\n"); + } else { + printk("GPIO, used by %s, ", gpio_label[i]); + if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { + printk("input, active %s, level %s, edge %s\n", + ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", + ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", + ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); + } else { + printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); + } + } + } + + printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", + MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); + printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", + MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); + printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", + MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); + printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", + MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); + printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", + GPIO_OUT, orion5x_read(GPIO_OUT)); + printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", + GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); + printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", + GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); + printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", + GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); + printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", + GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); + printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", + GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); + printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", + GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); + printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", + GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); +} diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c new file mode 100644 index 00000000000..dd21f38c5d3 --- /dev/null +++ b/arch/arm/mach-orion5x/irq.c @@ -0,0 +1,211 @@ +/* + * arch/arm/mach-orion5x/irq.c + * + * Core IRQ functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * Orion GPIO IRQ + * + * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same + * value of the line or the opposite value. + * + * Level IRQ handlers: DATA_IN is used directly as cause register. + * Interrupt are masked by LEVEL_MASK registers. + * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. + * Interrupt are masked by EDGE_MASK registers. + * Both-edge handlers: Similar to regular Edge handlers, but also swaps + * the polarity to catch the next line transaction. + * This is a race condition that might not perfectly + * work on some use cases. + * + * Every eight GPIO lines are grouped (OR'ed) before going up to main + * cause register. + * + * EDGE cause mask + * data-in /--------| |-----| |----\ + * -----| |----- ---- to main cause reg + * X \----------------| |----/ + * polarity LEVEL mask + * + ****************************************************************************/ +static void orion5x_gpio_irq_ack(u32 irq) +{ + int pin = irq_to_gpio(irq); + if (irq_desc[irq].status & IRQ_LEVEL) + /* + * Mask bit for level interrupt + */ + orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); + else + /* + * Clear casue bit for egde interrupt + */ + orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin); +} + +static void orion5x_gpio_irq_mask(u32 irq) +{ + int pin = irq_to_gpio(irq); + if (irq_desc[irq].status & IRQ_LEVEL) + orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); + else + orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin); +} + +static void orion5x_gpio_irq_unmask(u32 irq) +{ + int pin = irq_to_gpio(irq); + if (irq_desc[irq].status & IRQ_LEVEL) + orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin); + else + orion5x_setbits(GPIO_EDGE_MASK, 1 << pin); +} + +static int orion5x_gpio_set_irq_type(u32 irq, u32 type) +{ + int pin = irq_to_gpio(irq); + struct irq_desc *desc; + + if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { + printk(KERN_ERR "orion5x_gpio_set_irq_type failed " + "(irq %d, pin %d).\n", irq, pin); + return -EINVAL; + } + + desc = irq_desc + irq; + + switch (type) { + case IRQT_HIGH: + desc->handle_irq = handle_level_irq; + desc->status |= IRQ_LEVEL; + orion5x_clrbits(GPIO_IN_POL, (1 << pin)); + break; + case IRQT_LOW: + desc->handle_irq = handle_level_irq; + desc->status |= IRQ_LEVEL; + orion5x_setbits(GPIO_IN_POL, (1 << pin)); + break; + case IRQT_RISING: + desc->handle_irq = handle_edge_irq; + desc->status &= ~IRQ_LEVEL; + orion5x_clrbits(GPIO_IN_POL, (1 << pin)); + break; + case IRQT_FALLING: + desc->handle_irq = handle_edge_irq; + desc->status &= ~IRQ_LEVEL; + orion5x_setbits(GPIO_IN_POL, (1 << pin)); + break; + case IRQT_BOTHEDGE: + desc->handle_irq = handle_edge_irq; + desc->status &= ~IRQ_LEVEL; + /* + * set initial polarity based on current input level + */ + if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) + & (1 << pin)) + orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ + else + orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ + + break; + default: + printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); + return -EINVAL; + } + + desc->status &= ~IRQ_TYPE_SENSE_MASK; + desc->status |= type & IRQ_TYPE_SENSE_MASK; + + return 0; +} + +static struct irq_chip orion5x_gpio_irq_chip = { + .name = "Orion-IRQ-GPIO", + .ack = orion5x_gpio_irq_ack, + .mask = orion5x_gpio_irq_mask, + .unmask = orion5x_gpio_irq_unmask, + .set_type = orion5x_gpio_set_irq_type, +}; + +static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 cause, offs, pin; + + BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); + offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; + cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | + (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); + + for (pin = offs; pin < offs + 8; pin++) { + if (cause & (1 << pin)) { + irq = gpio_to_irq(pin); + desc = irq_desc + irq; + if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { + /* Swap polarity (race with GPIO line) */ + u32 polarity = orion5x_read(GPIO_IN_POL); + polarity ^= 1 << pin; + orion5x_write(GPIO_IN_POL, polarity); + } + desc_handle_irq(irq, desc); + } + } +} + +static void __init orion5x_init_gpio_irq(void) +{ + int i; + struct irq_desc *desc; + + /* + * Mask and clear GPIO IRQ interrupts + */ + orion5x_write(GPIO_LEVEL_MASK, 0x0); + orion5x_write(GPIO_EDGE_MASK, 0x0); + orion5x_write(GPIO_EDGE_CAUSE, 0x0); + + /* + * Register chained level handlers for GPIO IRQs by default. + * User can use set_type() if he wants to use edge types handlers. + */ + for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { + set_irq_chip(i, &orion5x_gpio_irq_chip); + set_irq_handler(i, handle_level_irq); + desc = irq_desc + i; + desc->status |= IRQ_LEVEL; + set_irq_flags(i, IRQF_VALID); + } + set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); +} + +/***************************************************************************** + * Orion Main IRQ + ****************************************************************************/ +static void __init orion5x_init_main_irq(void) +{ + orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); +} + +void __init orion5x_init_irq(void) +{ + orion5x_init_main_irq(); + orion5x_init_gpio_irq(); +} diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c new file mode 100644 index 00000000000..8ad4390b4b7 --- /dev/null +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -0,0 +1,243 @@ +/* + * arch/arm/mach-orion5x/kurobox_pro-setup.c + * + * Maintainer: Ronen Shitrit + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * KUROBOX-PRO Info + ****************************************************************************/ + +/* + * 256K NOR flash Device bus boot chip select + */ + +#define KUROBOX_PRO_NOR_BOOT_BASE 0xf4000000 +#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K + +/* + * 256M NAND flash on Device bus chip select 1 + */ + +#define KUROBOX_PRO_NAND_BASE 0xfc000000 +#define KUROBOX_PRO_NAND_SIZE SZ_2M + +/***************************************************************************** + * 256MB NAND Flash on Device bus CS0 + ****************************************************************************/ + +static struct mtd_partition kurobox_pro_nand_parts[] = { + { + .name = "uImage", + .offset = 0, + .size = SZ_4M, + }, + { + .name = "rootfs", + .offset = SZ_4M, + .size = SZ_64M, + }, + { + .name = "extra", + .offset = SZ_4M + SZ_64M, + .size = SZ_256M - (SZ_4M + SZ_64M), + }, +}; + +static struct resource kurobox_pro_nand_resource = { + .flags = IORESOURCE_MEM, + .start = KUROBOX_PRO_NAND_BASE, + .end = KUROBOX_PRO_NAND_BASE + KUROBOX_PRO_NAND_SIZE - 1, +}; + +static struct orion_nand_data kurobox_pro_nand_data = { + .parts = kurobox_pro_nand_parts, + .nr_parts = ARRAY_SIZE(kurobox_pro_nand_parts), + .cle = 0, + .ale = 1, + .width = 8, +}; + +static struct platform_device kurobox_pro_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &kurobox_pro_nand_data, + }, + .resource = &kurobox_pro_nand_resource, + .num_resources = 1, +}; + +/***************************************************************************** + * 256KB NOR Flash on BOOT Device + ****************************************************************************/ + +static struct physmap_flash_data kurobox_pro_nor_flash_data = { + .width = 1, +}; + +static struct resource kurobox_pro_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = KUROBOX_PRO_NOR_BOOT_BASE, + .end = KUROBOX_PRO_NOR_BOOT_BASE + KUROBOX_PRO_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device kurobox_pro_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &kurobox_pro_nor_flash_data, + }, + .num_resources = 1, + .resource = &kurobox_pro_nor_flash_resource, +}; + +/***************************************************************************** + * PCI + ****************************************************************************/ + +static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* + * PCI isn't used on the Kuro + */ + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; + else + printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); + + return -1; +} + +static struct hw_pci kurobox_pro_pci __initdata = { + .nr_controllers = 1, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = kurobox_pro_pci_map_irq, +}; + +static int __init kurobox_pro_pci_init(void) +{ + if (machine_is_kurobox_pro()) + pci_common_init(&kurobox_pro_pci); + + return 0; +} + +subsys_initcall(kurobox_pro_pci_init); + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data kurobox_pro_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/***************************************************************************** + * RTC 5C372a on I2C bus + ****************************************************************************/ +static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = { + .driver_name = "rtc-rs5c372", + .type = "rs5c372a", + .addr = 0x32, +}; + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct mv_sata_platform_data kurobox_pro_sata_data = { + .n_ports = 2, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +static struct platform_device *kurobox_pro_devices[] __initdata = { + &kurobox_pro_nor_flash, + &kurobox_pro_nand_flash, +}; + +static void __init kurobox_pro_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + /* + * Setup the CPU address decode windows for our devices + */ + orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, + KUROBOX_PRO_NOR_BOOT_SIZE); + orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); + + /* + * Open a special address decode windows for the PCIE WA. + */ + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); + + /* + * Setup Multiplexing Pins -- + * MPP[0-1] Not used + * MPP[2] GPIO Micon + * MPP[3] GPIO RTC + * MPP[4-5] Not used + * MPP[6] Nand Flash REn + * MPP[7] Nand Flash WEn + * MPP[8-11] Not used + * MPP[12] SATA 0 presence Indication + * MPP[13] SATA 1 presence Indication + * MPP[14] SATA 0 active Indication + * MPP[15] SATA 1 active indication + * MPP[16-19] Not used + */ + orion5x_write(MPP_0_7_CTRL, 0x44220003); + orion5x_write(MPP_8_15_CTRL, 0x55550000); + orion5x_write(MPP_16_19_CTRL, 0x0); + + orion5x_gpio_set_valid_pins(0x0000000c); + + platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); + i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); + orion5x_eth_init(&kurobox_pro_eth_data); + orion5x_sata_init(&kurobox_pro_sata_data); +} + +MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") + /* Maintainer: Ronen Shitrit */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = kurobox_pro_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c new file mode 100644 index 00000000000..27b4afc8f48 --- /dev/null +++ b/arch/arm/mach-orion5x/pci.c @@ -0,0 +1,559 @@ +/* + * arch/arm/mach-orion5x/pci.c + * + * PCI and PCIe functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * Orion has one PCIe controller and one PCI controller. + * + * Note1: The local PCIe bus number is '0'. The local PCI bus number + * follows the scanned PCIe bridged busses, if any. + * + * Note2: It is possible for PCI/PCIe agents to access many subsystem's + * space, by configuring BARs and Address Decode Windows, e.g. flashes on + * device bus, Orion registers, etc. However this code only enable the + * access to DDR banks. + ****************************************************************************/ + + +/***************************************************************************** + * PCIe controller + ****************************************************************************/ +#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) + +void __init orion5x_pcie_id(u32 *dev, u32 *rev) +{ + *dev = orion_pcie_dev_id(PCIE_BASE); + *rev = orion_pcie_rev(PCIE_BASE); +} + +int orion5x_pcie_local_bus_nr(void) +{ + return orion_pcie_get_local_bus_nr(PCIE_BASE); +} + +static int pcie_valid_config(int bus, int dev) +{ + /* + * Don't go out when trying to access -- + * 1. nonexisting device on local bus + * 2. where there's no device connected (no link) + */ + if (bus == 0 && dev == 0) + return 1; + + if (!orion_pcie_link_up(PCIE_BASE)) + return 0; + + if (bus == 0 && dev != 1) + return 0; + + return 1; +} + + +/* + * PCIe config cycles are done by programming the PCIE_CONF_ADDR register + * and then reading the PCIE_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(orion5x_pcie_lock); + +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + unsigned long flags; + int ret; + + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + spin_lock_irqsave(&orion5x_pcie_lock, flags); + ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&orion5x_pcie_lock, flags); + + return ret; +} + +static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, + int where, int size, u32 *val) +{ + int ret; + + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + /* + * We only support access to the non-extended configuration + * space when using the WA access method (or we would have to + * sacrifice 256M of CPU virtual address space.) + */ + if (where >= 0x100) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, + bus, devfn, where, size, val); + + return ret; +} + +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + unsigned long flags; + int ret; + + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + spin_lock_irqsave(&orion5x_pcie_lock, flags); + ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&orion5x_pcie_lock, flags); + + return ret; +} + +static struct pci_ops pcie_ops = { + .read = pcie_rd_conf, + .write = pcie_wr_conf, +}; + + +static int __init pcie_setup(struct pci_sys_data *sys) +{ + struct resource *res; + int dev; + + /* + * Generic PCIe unit setup. + */ + orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); + + /* + * Check whether to apply Orion-1/Orion-NAS PCIe config + * read transaction workaround. + */ + dev = orion_pcie_dev_id(PCIE_BASE); + if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { + printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " + "read transaction workaround\n"); + pcie_ops.read = pcie_rd_conf_wa; + } + + /* + * Request resources. + */ + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("pcie_setup unable to alloc resources"); + + /* + * IORESOURCE_IO + */ + res[0].name = "PCIe I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = ORION5X_PCIE_IO_BUS_BASE; + res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCIe IO resource failed\n"); + sys->resource[0] = &res[0]; + + /* + * IORESOURCE_MEM + */ + res[1].name = "PCIe Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCIe Memory resource failed\n"); + sys->resource[1] = &res[1]; + + sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +} + +/***************************************************************************** + * PCI controller + ****************************************************************************/ +#define PCI_MODE ORION5X_PCI_REG(0xd00) +#define PCI_CMD ORION5X_PCI_REG(0xc00) +#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) +#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) +#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) + +/* + * PCI_MODE bits + */ +#define PCI_MODE_64BIT (1 << 2) +#define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) + +/* + * PCI_CMD bits + */ +#define PCI_CMD_HOST_REORDER (1 << 29) + +/* + * PCI_P2P_CONF bits + */ +#define PCI_P2P_BUS_OFFS 16 +#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) +#define PCI_P2P_DEV_OFFS 24 +#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) + +/* + * PCI_CONF_ADDR bits + */ +#define PCI_CONF_REG(reg) ((reg) & 0xfc) +#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) +#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) +#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) +#define PCI_CONF_ADDR_EN (1 << 31) + +/* + * Internal configuration space + */ +#define PCI_CONF_FUNC_STAT_CMD 0 +#define PCI_CONF_REG_STAT_CMD 4 +#define PCIX_STAT 0x64 +#define PCIX_STAT_BUS_OFFS 8 +#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) + +/* + * PCI Address Decode Windows registers + */ +#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ + ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ + ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ + ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) +#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ + ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ + ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ + ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) +#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) +#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) + +/* + * PCI configuration helpers for BAR settings + */ +#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) +#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) +#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) + +/* + * PCI config cycles are done by programming the PCI_CONF_ADDR register + * and then reading the PCI_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(orion5x_pci_lock); + +int orion5x_pci_local_bus_nr(void) +{ + u32 conf = orion5x_read(PCI_P2P_CONF); + return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); +} + +static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, + u32 where, u32 size, u32 *val) +{ + unsigned long flags; + spin_lock_irqsave(&orion5x_pci_lock, flags); + + orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | + PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); + + *val = orion5x_read(PCI_CONF_DATA); + + if (size == 1) + *val = (*val >> (8*(where & 0x3))) & 0xff; + else if (size == 2) + *val = (*val >> (8*(where & 0x3))) & 0xffff; + + spin_unlock_irqrestore(&orion5x_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, + u32 where, u32 size, u32 val) +{ + unsigned long flags; + int ret = PCIBIOS_SUCCESSFUL; + + spin_lock_irqsave(&orion5x_pci_lock, flags); + + orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | + PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); + + if (size == 4) { + __raw_writel(val, PCI_CONF_DATA); + } else if (size == 2) { + __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); + } else if (size == 1) { + __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); + } else { + ret = PCIBIOS_BAD_REGISTER_NUMBER; + } + + spin_unlock_irqrestore(&orion5x_pci_lock, flags); + + return ret; +} + +static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 *val) +{ + /* + * Don't go out for local device + */ + if (bus->number == orion5x_pci_local_bus_nr() && + PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where, size, val); +} + +static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + if (bus->number == orion5x_pci_local_bus_nr() && + PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where, size, val); +} + +static struct pci_ops pci_ops = { + .read = orion5x_pci_rd_conf, + .write = orion5x_pci_wr_conf, +}; + +static void __init orion5x_pci_set_bus_nr(int nr) +{ + u32 p2p = orion5x_read(PCI_P2P_CONF); + + if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { + /* + * PCI-X mode + */ + u32 pcix_status, bus, dev; + bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; + dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; + orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); + pcix_status &= ~PCIX_STAT_BUS_MASK; + pcix_status |= (nr << PCIX_STAT_BUS_OFFS); + orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); + } else { + /* + * PCI Conventional mode + */ + p2p &= ~PCI_P2P_BUS_MASK; + p2p |= (nr << PCI_P2P_BUS_OFFS); + orion5x_write(PCI_P2P_CONF, p2p); + } +} + +static void __init orion5x_pci_master_slave_enable(void) +{ + int bus_nr, func, reg; + u32 val; + + bus_nr = orion5x_pci_local_bus_nr(); + func = PCI_CONF_FUNC_STAT_CMD; + reg = PCI_CONF_REG_STAT_CMD; + orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); + val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); +} + +static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) +{ + u32 win_enable; + int bus; + int i; + + /* + * First, disable windows. + */ + win_enable = 0xffffffff; + orion5x_write(PCI_BAR_ENABLE, win_enable); + + /* + * Setup windows for DDR banks. + */ + bus = orion5x_pci_local_bus_nr(); + + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); + u32 reg; + u32 val; + + /* + * Write DRAM bank base address register. + */ + reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); + orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); + val = (cs->base & 0xfffff000) | (val & 0xfff); + orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); + + /* + * Write DRAM bank size register. + */ + reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); + orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); + orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), + (cs->size - 1) & 0xfffff000); + orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), + cs->base & 0xfffff000); + + /* + * Enable decode window for this chip select. + */ + win_enable &= ~(1 << cs->cs_index); + } + + /* + * Re-enable decode windows. + */ + orion5x_write(PCI_BAR_ENABLE, win_enable); + + /* + * Disable automatic update of address remaping when writing to BARs. + */ + orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); +} + +static int __init pci_setup(struct pci_sys_data *sys) +{ + struct resource *res; + + /* + * Point PCI unit MBUS decode windows to DRAM space. + */ + orion5x_setup_pci_wins(&orion5x_mbus_dram_info); + + /* + * Master + Slave enable + */ + orion5x_pci_master_slave_enable(); + + /* + * Force ordering + */ + orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); + + /* + * Request resources + */ + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("pci_setup unable to alloc resources"); + + /* + * IORESOURCE_IO + */ + res[0].name = "PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = ORION5X_PCI_IO_BUS_BASE; + res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCI IO resource failed\n"); + sys->resource[0] = &res[0]; + + /* + * IORESOURCE_MEM + */ + res[1].name = "PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = ORION5X_PCI_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCI Memory resource failed\n"); + sys->resource[1] = &res[1]; + + sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +} + + +/***************************************************************************** + * General PCIe + PCI + ****************************************************************************/ +static void __devinit rc_pci_fixup(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root complex. + */ + if (dev->bus->parent == NULL && dev->devfn == 0) { + int i; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); + +int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) +{ + int ret = 0; + + if (nr == 0) { + orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); + ret = pcie_setup(sys); + } else if (nr == 1) { + orion5x_pci_set_bus_nr(sys->busnr); + ret = pci_setup(sys); + } + + return ret; +} + +struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_bus *bus; + + if (nr == 0) { + bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + } else if (nr == 1) { + bus = pci_scan_bus(sys->busnr, &pci_ops, sys); + } else { + bus = NULL; + BUG(); + } + + return bus; +} diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c new file mode 100644 index 00000000000..37e8b2dc3ed --- /dev/null +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -0,0 +1,312 @@ +/* + * arch/arm/mach-orion5x/rd88f5182-setup.c + * + * Marvell Orion-NAS Reference Design Setup + * + * Maintainer: Ronen Shitrit + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * RD-88F5182 Info + ****************************************************************************/ + +/* + * 512K NOR flash Device bus boot chip select + */ + +#define RD88F5182_NOR_BOOT_BASE 0xf4000000 +#define RD88F5182_NOR_BOOT_SIZE SZ_512K + +/* + * 16M NOR flash on Device bus chip select 1 + */ + +#define RD88F5182_NOR_BASE 0xfc000000 +#define RD88F5182_NOR_SIZE SZ_16M + +/* + * PCI + */ + +#define RD88F5182_PCI_SLOT0_OFFS 7 +#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7 +#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6 + +/* + * GPIO Debug LED + */ + +#define RD88F5182_GPIO_DBG_LED 0 + +/***************************************************************************** + * 16M NOR Flash on Device bus CS1 + ****************************************************************************/ + +static struct physmap_flash_data rd88f5182_nor_flash_data = { + .width = 1, +}; + +static struct resource rd88f5182_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = RD88F5182_NOR_BASE, + .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1, +}; + +static struct platform_device rd88f5182_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &rd88f5182_nor_flash_data, + }, + .num_resources = 1, + .resource = &rd88f5182_nor_flash_resource, +}; + +#ifdef CONFIG_LEDS + +/***************************************************************************** + * Use GPIO debug led as CPU active indication + ****************************************************************************/ + +static void rd88f5182_dbgled_event(led_event_t evt) +{ + int val; + + if (evt == led_idle_end) + val = 1; + else if (evt == led_idle_start) + val = 0; + else + return; + + gpio_set_value(RD88F5182_GPIO_DBG_LED, val); +} + +static int __init rd88f5182_dbgled_init(void) +{ + int pin; + + if (machine_is_rd88f5182()) { + pin = RD88F5182_GPIO_DBG_LED; + + if (gpio_request(pin, "DBGLED") == 0) { + if (gpio_direction_output(pin, 0) != 0) { + printk(KERN_ERR "rd88f5182_dbgled_init failed " + "to set output pin %d\n", pin); + gpio_free(pin); + return 0; + } + } else { + printk(KERN_ERR "rd88f5182_dbgled_init failed " + "to request gpio %d\n", pin); + return 0; + } + + leds_event = rd88f5182_dbgled_event; + } + return 0; +} + +__initcall(rd88f5182_dbgled_init); + +#endif + +/***************************************************************************** + * PCI + ****************************************************************************/ + +void __init rd88f5182_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; + if (gpio_request(pin, "PCI IntA") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "rd88f5182_pci_preinit faield to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); + } + + pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; + if (gpio_request(pin, "PCI IntB") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "rd88f5182_pci_preinit faield to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); + } +} + +static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* + * PCI-E isn't used on the RD2 + */ + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; + + /* + * PCI IRQs are connected via GPIOs + */ + switch (slot - RD88F5182_PCI_SLOT0_OFFS) { + case 0: + if (pin == 1) + return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN); + else + return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN); + default: + return -1; + } +} + +static struct hw_pci rd88f5182_pci __initdata = { + .nr_controllers = 2, + .preinit = rd88f5182_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = rd88f5182_pci_map_irq, +}; + +static int __init rd88f5182_pci_init(void) +{ + if (machine_is_rd88f5182()) + pci_common_init(&rd88f5182_pci); + + return 0; +} + +subsys_initcall(rd88f5182_pci_init); + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data rd88f5182_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/***************************************************************************** + * RTC DS1338 on I2C bus + ****************************************************************************/ +static struct i2c_board_info __initdata rd88f5182_i2c_rtc = { + .driver_name = "rtc-ds1307", + .type = "ds1338", + .addr = 0x68, +}; + +/***************************************************************************** + * Sata + ****************************************************************************/ +static struct mv_sata_platform_data rd88f5182_sata_data = { + .n_ports = 2, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +static struct platform_device *rd88f5182_devices[] __initdata = { + &rd88f5182_nor_flash, +}; + +static void __init rd88f5182_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + /* + * Setup the CPU address decode windows for our devices + */ + orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, + RD88F5182_NOR_BOOT_SIZE); + orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); + + /* + * Open a special address decode windows for the PCIE WA. + */ + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); + + /* + * Setup Multiplexing Pins -- + * MPP[0] Debug Led (GPIO - Out) + * MPP[1] Debug Led (GPIO - Out) + * MPP[2] N/A + * MPP[3] RTC_Int (GPIO - In) + * MPP[4] GPIO + * MPP[5] GPIO + * MPP[6] PCI_intA (GPIO - In) + * MPP[7] PCI_intB (GPIO - In) + * MPP[8-11] N/A + * MPP[12] SATA 0 presence Indication + * MPP[13] SATA 1 presence Indication + * MPP[14] SATA 0 active Indication + * MPP[15] SATA 1 active indication + * MPP[16-19] Not used + * MPP[20] PCI Clock to MV88F5182 + * MPP[21] PCI Clock to mini PCI CON11 + * MPP[22] USB 0 over current indication + * MPP[23] USB 1 over current indication + * MPP[24] USB 1 over current enable + * MPP[25] USB 0 over current enable + */ + + orion5x_write(MPP_0_7_CTRL, 0x00000003); + orion5x_write(MPP_8_15_CTRL, 0x55550000); + orion5x_write(MPP_16_19_CTRL, 0x5555); + + orion5x_gpio_set_valid_pins(0x000000fb); + + platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); + i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); + orion5x_eth_init(&rd88f5182_eth_data); + orion5x_sata_init(&rd88f5182_sata_data); +} + +MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") + /* Maintainer: Ronen Shitrit */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = rd88f5182_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, +MACHINE_END diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c new file mode 100644 index 00000000000..71b0cffa2fe --- /dev/null +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -0,0 +1,359 @@ +/* + * QNAP TS-109/TS-209 Board Setup + * + * Maintainer: Byron Bradley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 +#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M + +/**************************************************************************** + * 8MiB NOR flash. The struct mtd_partition is not in the same order as the + * partitions on the device because we want to keep compatability with + * existing QNAP firmware. + * + * Layout as used by QNAP: + * [2] 0x00000000-0x00200000 : "Kernel" + * [3] 0x00200000-0x00600000 : "RootFS1" + * [4] 0x00600000-0x00700000 : "RootFS2" + * [6] 0x00700000-0x00760000 : "NAS Config" (read-only) + * [5] 0x00760000-0x00780000 : "U-Boot Config" + * [1] 0x00780000-0x00800000 : "U-Boot" (read-only) + ***************************************************************************/ +static struct mtd_partition qnap_ts209_partitions[] = { + { + .name = "U-Boot", + .size = 0x00080000, + .offset = 0x00780000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .size = 0x00200000, + .offset = 0, + }, { + .name = "RootFS1", + .size = 0x00400000, + .offset = 0x00200000, + }, { + .name = "RootFS2", + .size = 0x00100000, + .offset = 0x00600000, + }, { + .name = "U-Boot Config", + .size = 0x00020000, + .offset = 0x00760000, + }, { + .name = "NAS Config", + .size = 0x00060000, + .offset = 0x00700000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct physmap_flash_data qnap_ts209_nor_flash_data = { + .width = 1, + .parts = qnap_ts209_partitions, + .nr_parts = ARRAY_SIZE(qnap_ts209_partitions) +}; + +static struct resource qnap_ts209_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = QNAP_TS209_NOR_BOOT_BASE, + .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device qnap_ts209_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { .platform_data = &qnap_ts209_nor_flash_data, }, + .resource = &qnap_ts209_nor_flash_resource, + .num_resources = 1, +}; + +/***************************************************************************** + * PCI + ****************************************************************************/ + +#define QNAP_TS209_PCI_SLOT0_OFFS 7 +#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6 +#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7 + +void __init qnap_ts209_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; + if (gpio_request(pin, "PCI Int1") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "qnap_ts209_pci_preinit failed to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request " + "%d\n", pin); + } + + pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; + if (gpio_request(pin, "PCI Int2") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "qnap_ts209_pci_preinit failed " + "to set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request " + "%d\n", pin); + } +} + +static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* + * PCIE IRQ is connected internally (not GPIO) + */ + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; + + /* + * PCI IRQs are connected via GPIOs + */ + switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) { + case 0: + return gpio_to_irq(QNAP_TS209_PCI_SLOT0_IRQ_PIN); + case 1: + return gpio_to_irq(QNAP_TS209_PCI_SLOT1_IRQ_PIN); + default: + return -1; + } +} + +static struct hw_pci qnap_ts209_pci __initdata = { + .nr_controllers = 2, + .preinit = qnap_ts209_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = qnap_ts209_pci_map_irq, +}; + +static int __init qnap_ts209_pci_init(void) +{ + if (machine_is_ts_x09()) + pci_common_init(&qnap_ts209_pci); + + return 0; +} + +subsys_initcall(qnap_ts209_pci_init); + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data qnap_ts209_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/***************************************************************************** + * RTC S35390A on I2C bus + ****************************************************************************/ + +#define TS209_RTC_GPIO 3 + +static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = { + .driver_name = "rtc-s35390a", + .addr = 0x30, + .irq = 0, +}; + +/**************************************************************************** + * GPIO Attached Keys + * Power button is attached to the PIC microcontroller + ****************************************************************************/ + +#define QNAP_TS209_GPIO_KEY_MEDIA 1 +#define QNAP_TS209_GPIO_KEY_RESET 2 + +static struct gpio_keys_button qnap_ts209_buttons[] = { + { + .code = KEY_RESTART, + .gpio = QNAP_TS209_GPIO_KEY_MEDIA, + .desc = "USB Copy Button", + .active_low = 1, + }, + { + .code = KEY_POWER, + .gpio = QNAP_TS209_GPIO_KEY_RESET, + .desc = "Reset Button", + .active_low = 1, + } +}; + +static struct gpio_keys_platform_data qnap_ts209_button_data = { + .buttons = qnap_ts209_buttons, + .nbuttons = ARRAY_SIZE(qnap_ts209_buttons), +}; + +static struct platform_device qnap_ts209_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { .platform_data = &qnap_ts209_button_data, }, +}; + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct mv_sata_platform_data qnap_ts209_sata_data = { + .n_ports = 2, +}; + +/***************************************************************************** + + * General Setup + ****************************************************************************/ + +static struct platform_device *qnap_ts209_devices[] __initdata = { + &qnap_ts209_nor_flash, + &qnap_ts209_button_device, +}; + +/* + * QNAP TS-[12]09 specific power off method via UART1-attached PIC + */ + +#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) + +static void qnap_ts209_power_off(void) +{ + /* 19200 baud divisor */ + const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); + + pr_info("%s: triggering power-off...\n", __func__); + + /* hijack uart1 and reset into sane state (19200,8n1) */ + orion5x_write(UART1_REG(LCR), 0x83); + orion5x_write(UART1_REG(DLL), divisor & 0xff); + orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff); + orion5x_write(UART1_REG(LCR), 0x03); + orion5x_write(UART1_REG(IER), 0x00); + orion5x_write(UART1_REG(FCR), 0x00); + orion5x_write(UART1_REG(MCR), 0x00); + + /* send the power-off command 'A' to PIC */ + orion5x_write(UART1_REG(TX), 'A'); +} + +static void __init qnap_ts209_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + /* + * Setup flash mapping + */ + orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE); + + /* + * Open a special address decode windows for the PCIE WA. + */ + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); + + /* + * Setup Multiplexing Pins -- + * MPP[0] Reserved + * MPP[1] USB copy button (0 active) + * MPP[2] Load defaults button (0 active) + * MPP[3] GPIO RTC + * MPP[4-5] Reserved + * MPP[6] PCI Int A + * MPP[7] PCI Int B + * MPP[8-11] Reserved + * MPP[12] SATA 0 presence + * MPP[13] SATA 1 presence + * MPP[14] SATA 0 active + * MPP[15] SATA 1 active + * MPP[16] UART1 RXD + * MPP[17] UART1 TXD + * MPP[18] SW_RST (0 active) + * MPP[19] Reserved + * MPP[20] PCI clock 0 + * MPP[21] PCI clock 1 + * MPP[22] USB 0 over current + * MPP[23-25] Reserved + */ + orion5x_write(MPP_0_7_CTRL, 0x3); + orion5x_write(MPP_8_15_CTRL, 0x55550000); + orion5x_write(MPP_16_19_CTRL, 0x5500); + orion5x_gpio_set_valid_pins(0x3cc0fff); + + /* register ts209 specific power-off method */ + pm_power_off = qnap_ts209_power_off; + + platform_add_devices(qnap_ts209_devices, + ARRAY_SIZE(qnap_ts209_devices)); + + /* Get RTC IRQ and register the chip */ + if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) { + if (gpio_direction_input(TS209_RTC_GPIO) == 0) + qnap_ts209_i2c_rtc.irq = gpio_to_irq(TS209_RTC_GPIO); + else + gpio_free(TS209_RTC_GPIO); + } + if (qnap_ts209_i2c_rtc.irq == 0) + pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); + i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); + + orion5x_eth_init(&qnap_ts209_eth_data); + orion5x_sata_init(&qnap_ts209_sata_data); +} + +MACHINE_START(TS209, "QNAP TS-109/TS-209") + /* Maintainer: Byron Bradley */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = qnap_ts209_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 76348f060f2..64d09244df4 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -345,7 +345,7 @@ config CPU_XSC3 # Feroceon config CPU_FEROCEON bool - depends on ARCH_ORION + depends on ARCH_ORION5X default y select CPU_32v5 select CPU_ABRT_EV5T -- cgit From c60afe1014dc4b8d2211fb6cc9dd08ebab31d00b Mon Sep 17 00:00:00 2001 From: Riku Voipio Date: Fri, 28 Mar 2008 13:08:09 +0100 Subject: [ARM] 4878/1: Add oabi shim for fstatat64 Ccoreutils and other have started using fstatat64. Thus, we need a shim for it if we want to support modern oldabi userlands (such as Debian/arm/lenny) with EABI kernels. See http://bugs.debian.org/462677 Acked-by: Nicolas Pitre Signed-off-by: Riku Voipio Signed-off-by: Russell King --- arch/arm/kernel/calls.S | 2 +- arch/arm/kernel/sys_oabi-compat.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 283e14fff99..7e97b737656 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -336,7 +336,7 @@ CALL(sys_mknodat) /* 325 */ CALL(sys_fchownat) CALL(sys_futimesat) - CALL(sys_fstatat64) + CALL(ABI(sys_fstatat64, sys_oabi_fstatat64)) CALL(sys_unlinkat) CALL(sys_renameat) /* 330 */ CALL(sys_linkat) diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index e8b98046895..96ab5f52949 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c @@ -25,6 +25,7 @@ * sys_stat64: * sys_lstat64: * sys_fstat64: + * sys_fstatat64: * * struct stat64 has different sizes and some members are shifted * Compatibility wrappers are needed for them and provided below. @@ -169,6 +170,29 @@ asmlinkage long sys_oabi_fstat64(unsigned long fd, return error; } +asmlinkage long sys_oabi_fstatat64(int dfd, + char __user *filename, + struct oldabi_stat64 __user *statbuf, + int flag) +{ + struct kstat stat; + int error = -EINVAL; + + if ((flag & ~AT_SYMLINK_NOFOLLOW) != 0) + goto out; + + if (flag & AT_SYMLINK_NOFOLLOW) + error = vfs_lstat_fd(dfd, filename, &stat); + else + error = vfs_stat_fd(dfd, filename, &stat); + + if (!error) + error = cp_oldabi_stat64(&stat, statbuf); + +out: + return error; +} + struct oabi_flock64 { short l_type; short l_whence; -- cgit From b626517751b8d78abc8465971e3120ebd686673a Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Sun, 23 Mar 2008 15:32:33 +0100 Subject: [ARM] 4873/1: Fix ITE 8152 interrupt demux This patch fixes misprints in ITE 8152 interrupt demuxing Signed-off-by: Mike Rapoport Signed-off-by: Russell King --- arch/arm/common/it8152.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index 53826224148..5fe9588db07 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -120,6 +120,7 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) time, when they all three were 0. */ bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); + bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); if (!(bits_ld | bits_lp | bits_pd)) return; } @@ -133,14 +134,14 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1); while (bits_lp) { - i = __ffs(bits_pd); + i = __ffs(bits_lp); it8152_irq(IT8152_LP_IRQ(i)); bits_lp &= ~(1 << i); } bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1); while (bits_ld) { - i = __ffs(bits_pd); + i = __ffs(bits_ld); it8152_irq(IT8152_LD_IRQ(i)); bits_ld &= ~(1 << i); } -- cgit From 3ad0920d7b11a88379ec4db186be3eee667c4278 Mon Sep 17 00:00:00 2001 From: Steve Birtles Date: Sat, 9 Feb 2008 04:49:55 +0100 Subject: [ARM] 4825/1: adds support for YL9200 board 1. Configuration file for YL9200 2. Board file fro YL9200 Adds support for the UCdragon YL9200 board available widly in China Signed-off-by: steve birtles Signed-off-by: Russell King --- arch/arm/configs/yl9200_defconfig | 1216 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-at91/board-yl-9200.c | 683 ++++++++++++++++++++ 2 files changed, 1899 insertions(+) create mode 100644 arch/arm/configs/yl9200_defconfig create mode 100755 arch/arm/mach-at91/board-yl-9200.c (limited to 'arch/arm') diff --git a/arch/arm/configs/yl9200_defconfig b/arch/arm/configs/yl9200_defconfig new file mode 100644 index 00000000000..26de37f7468 --- /dev/null +++ b/arch/arm/configs/yl9200_defconfig @@ -0,0 +1,1216 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24-rc6 +# Fri Jan 11 09:53:59 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +CONFIG_ARCH_AT91=y +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Atmel AT91 System-on-Chip +# +CONFIG_ARCH_AT91RM9200=y +# CONFIG_ARCH_AT91SAM9260 is not set +# CONFIG_ARCH_AT91SAM9261 is not set +# CONFIG_ARCH_AT91SAM9263 is not set +# CONFIG_ARCH_AT91SAM9RL is not set +# CONFIG_ARCH_AT91X40 is not set +CONFIG_AT91_PMC_UNIT=y + +# +# AT91RM9200 Board Type +# +# CONFIG_MACH_ONEARM is not set +CONFIG_ARCH_AT91RM9200DK=y +# CONFIG_MACH_AT91RM9200EK is not set +# CONFIG_MACH_CSB337 is not set +# CONFIG_MACH_CSB637 is not set +# CONFIG_MACH_CARMEVA is not set +# CONFIG_MACH_ATEB9200 is not set +# CONFIG_MACH_KB9200 is not set +# CONFIG_MACH_PICOTUX2XX is not set +# CONFIG_MACH_KAFA is not set +CONFIG_MACH_YL9200=y + +# +# AT91 Board Options +# +# CONFIG_MTD_AT91_DATAFLASH_CARD is not set + +# +# AT91 Feature Selections +# +# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM920T=y +CONFIG_CPU_32v4T=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" +# CONFIG_XIP_KERNEL is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x0000000 +CONFIG_MTD_PHYSMAP_LEN=0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +CONFIG_MTD_PLATRAM=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_AT91=y +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=3 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +CONFIG_DAVICOM_PHY=y +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_ARM_AT91_ETHER=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +CONFIG_SPI=y +CONFIG_SPI_DEBUG=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_ATMEL=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_S1D135XX=y +# CONFIG_FB_VIRTUAL is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_CORGI is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +CONFIG_USB_GADGET_M66592=y +CONFIG_USB_M66592=y +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=y +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_AT91=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_GPIO=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_AT91RM9200=y + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set + +# +# Miscellaneous filesystems +# +# CONFIG_HFSPLUS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=1 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +CONFIG_SLUB_DEBUG_ON=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_DEBUG_KOBJECT=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c new file mode 100755 index 00000000000..b5717108991 --- /dev/null +++ b/arch/arm/mach-at91/board-yl-9200.c @@ -0,0 +1,683 @@ +/* + * linux/arch/arm/mach-at91/board-yl-9200.c + * + * Adapted from: + *various board files in + * /arch/arm/mach-at91 + * modifications to convert to YL-9200 platform + * Copyright (C) 2007 S.Birtles + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +/*#include */ +#include +#include + +/*#include */ +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "generic.h" +#include + +#define YL_9200_FLASH_BASE AT91_CHIPSELECT_0 +#define YL_9200_FLASH_SIZE 0x800000 + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL + *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL + *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL + *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL + *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL + * on the YL-9200 we are sitting at the following + *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL + *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL + */ + +/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/ + +static struct at91_uart_config __initdata yl_9200_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 3, + .tty_map = { 4, 1, 0, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init yl_9200_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + /*Also initialises register clocks & gpio*/ + at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/ + + /* Setup the serial ports and console */ + at91_init_serial(&yl_9200_uart_config); + + /* Setup the LEDs D2=PB17,D3=PB16 */ + at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/ +} + +static void __init yl_9200_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata yl_9200_eth_data = { + .phy_irq_pin = AT91_PIN_PB28, + .is_rmii = 1, +}; + +static struct at91_usbh_data __initdata yl_9200_usbh_data = { + .ports = 1, /* this should be 1 not 2 for the Yl9200*/ +}; + +static struct at91_udc_data __initdata yl_9200_udc_data = { +/*on sheet 7 Schemitic rev 1.0*/ + .pullup_pin = AT91_PIN_PC4, + .vbus_pin= AT91_PIN_PC5, + .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/ + +}; +/* +static struct at91_cf_data __initdata yl_9200_cf_data = { +TODO S.BIRTLES + .det_pin = AT91_PIN_xxx, + .rst_pin = AT91_PIN_xxx, + .irq_pin = ... not connected + .vcc_pin = ... always powered + +}; +*/ +static struct at91_mmc_data __initdata yl_9200_mmc_data = { + .det_pin = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/ +/* .wp_pin = ... not connected SHEET7*/ + .slot_b = 0, + .wire4 = 1, + +}; + +/* -------------------------------------------------------------------- + * Touch screen + * -------------------------------------------------------------------- */ +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) +static int ads7843_pendown_state(void) +{ + return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */ +} + +static void __init at91_init_device_ts(void) +{ +/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C +THAT IS TO SAY THAT MISO,MOSI,SPCK AND CS are already configured +we only need to enable the other datapins which are: +PB10/RK1 BUSY +*/ +/* Touchscreen BUSY signal , pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/ +at91_set_gpio_input(AT91_PIN_PB10, 1); +} + +#else +static void __init at91_init_device_ts(void) {} +#endif + +static struct ads7846_platform_data ads_info = { + .model = 7843, + .x_min = 150, + .x_max = 3830, + .y_min = 190, + .y_max = 3830, + .vref_delay_usecs = 100, +/* for a 8" touch screen*/ + //.x_plate_ohms = 603, //= 450, S.Birtles TODO + //.y_plate_ohms = 332, //= 250, S.Birtles TODO +/*for a 10.4" touch screen*/ + //.x_plate_ohms =611, + //.y_plate_ohms =325, + + .x_plate_ohms = 576, + .y_plate_ohms = 366, + // + .pressure_max = 15000, /*generally nonsense on the 7843*/ + /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/ + .debounce_max = 1, + .debounce_rep = 0, + .debounce_tol = (~0), + .get_pendown_state = ads7843_pendown_state, +}; + +/*static struct canbus_platform_data can_info = { + .model = 2510, +}; +*/ + +static struct spi_board_info yl_9200_spi_devices[] = { +/*this sticks it at: + /sys/devices/platform/atmel_spi.0/spi0.0 + /sys/bus/platform/devices/ +Documentation/spi IIRC*/ + +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) + /*(this IS correct 04-NOV-2007)*/ + { + .modalias = "ads7846", /* because the driver is called ads7846*/ + .chip_select = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */ +/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/ + /*.controller_data =AT91_PIN_PA3 ,*/ + .max_speed_hz = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */ + .bus_num = 0, + .platform_data = &ads_info, + .irq = AT91_PIN_PB11, + }, +#endif +/*we need to put our CAN driver data here!!*/ +/*THIS IS ALL DUMMY DATA*/ +/* { + .modalias = "mcp2510", //DUMMY for MCP2510 chip + .chip_select = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */ + /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */ + /* .controller_data =AT91_PIN_PA4 , + .max_speed_hz = 25000 * 26, + .bus_num = 0, + .platform_data = &can_info, + .irq = AT91_PIN_PC0, + }, + */ + //max SPI chip needs to go here +}; + +static struct mtd_partition __initdata yl_9200_nand_partition[] = { + { + .name = "AT91 NAND partition 1, boot", + .offset = 0, + .size = 1 * SZ_256K + }, + { + .name = "AT91 NAND partition 2, kernel", + .offset = 1 * SZ_256K, + .size = 2 * SZ_1M - 1 * SZ_256K + }, + { + .name = "AT91 NAND partition 3, filesystem", + .offset = 2 * SZ_1M, + .size = 14 * SZ_1M + }, + { + .name = "AT91 NAND partition 4, storage", + .offset = 16 * SZ_1M, + .size = 16 * SZ_1M + }, + { + .name = "AT91 NAND partition 5, ext-fs", + .offset = 32 * SZ_1M, + .size = 32 * SZ_1M + }, +}; + +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(yl_9200_nand_partition); + return yl_9200_nand_partition; +} + +static struct at91_nand_data __initdata yl_9200_nand_data = { + .ale= 6, + .cle= 7, + /*.det_pin = AT91_PIN_PCxx,*/ /*we don't have a det pin because NandFlash is fixed to board*/ + .rdy_pin = AT91_PIN_PC14, /*R/!B Sheet10*/ + .enable_pin = AT91_PIN_PC15, /*!CE Sheet10 */ + .partition_info = nand_partitions, +}; + + + +/* +TODO S.Birtles +potentially a problem with the size above +physmap platform flash device: 00800000 at 10000000 +physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank +NOR chip too large to fit in mapping. Attempting to cope... + Intel/Sharp Extended Query Table at 0x0031 +Using buffer write method +cfi_cmdset_0001: Erase suspend on write enabled +Reducing visibility of 16384KiB chip to 8192KiB +*/ + +static struct mtd_partition yl_9200_flash_partitions[] = { + { + .name = "Bootloader", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_WRITEABLE /* force read-only */ + },{ + .name = "Kernel", + .size = 0x001C0000, + .offset = 0x00040000, + },{ + .name = "Filesystem", + .size = MTDPART_SIZ_FULL, + .offset = 0x00200000 + } + +}; + +static struct physmap_flash_data yl_9200_flash_data = { + .width = 2, + .parts = yl_9200_flash_partitions, + .nr_parts = ARRAY_SIZE(yl_9200_flash_partitions), +}; + +static struct resource yl_9200_flash_resources[] = { +{ + .start = YL_9200_FLASH_BASE, + .end = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device yl_9200_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &yl_9200_flash_data, + }, + .resource = yl_9200_flash_resources, + .num_resources = ARRAY_SIZE(yl_9200_flash_resources), +}; + + +static struct gpio_led yl_9200_leds[] = { +/*D2 &D3 are passed directly in via at91_init_leds*/ + { + .name = "led4", /*D4*/ + .gpio = AT91_PIN_PB15, + .active_low = 1, + .default_trigger = "heartbeat", + /*.default_trigger = "timer",*/ + }, + { + .name = "led5", /*D5*/ + .gpio = AT91_PIN_PB8, + .active_low = 1, + .default_trigger = "heartbeat", + } +}; + +//static struct gpio_sounder yl_9200_sounder[] = {*/ +/*This is a simple speaker attached to a gpo line*/ + +// { +// .name = "Speaker", /*LS1*/ +// .gpio = AT91_PIN_PA22, +// .active_low = 0, +// .default_trigger = "heartbeat", + /*.default_trigger = "timer",*/ +// }, +//}; + + + +static struct i2c_board_info __initdata yl_9200_i2c_devices[] = { + { + /*TODO*/ + I2C_BOARD_INFO("CS4334", 0x00), + } +}; + + + /* + * GPIO Buttons + */ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button yl_9200_buttons[] = { + { + .gpio = AT91_PIN_PA24, + .code = BTN_2, + .desc = "SW2", + .active_low = 1, + .wakeup = 1, + }, + { + .gpio = AT91_PIN_PB1, + .code = BTN_3, + .desc = "SW3", + .active_low = 1, + .wakeup = 1, + }, + { + .gpio = AT91_PIN_PB2, + .code = BTN_4, + .desc = "SW4", + .active_low = 1, + .wakeup = 1, + }, + { + .gpio = AT91_PIN_PB6, + .code = BTN_5, + .desc = "SW5", + .active_low = 1, + .wakeup = 1, + }, + +}; + +static struct gpio_keys_platform_data yl_9200_button_data = { + .buttons = yl_9200_buttons, + .nbuttons = ARRAY_SIZE(yl_9200_buttons), +}; + +static struct platform_device yl_9200_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &yl_9200_button_data, + } +}; + +static void __init yl_9200_add_device_buttons(void) +{ + //SW2 + at91_set_gpio_input(AT91_PIN_PA24, 0); + at91_set_deglitch(AT91_PIN_PA24, 1); + + //SW3 + at91_set_gpio_input(AT91_PIN_PB1, 0); + at91_set_deglitch(AT91_PIN_PB1, 1); + //SW4 + at91_set_gpio_input(AT91_PIN_PB2, 0); + at91_set_deglitch(AT91_PIN_PB2, 1); + + //SW5 + at91_set_gpio_input(AT91_PIN_PB6, 0); + at91_set_deglitch(AT91_PIN_PB6, 1); + + + at91_set_gpio_output(AT91_PIN_PB7, 1); /* #TURN BUTTONS ON, SHEET 5 of schematics */ + platform_device_register(&yl_9200_button_device); +} +#else +static void __init yl_9200_add_device_buttons(void) {} +#endif + +#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE) +#include