From 9cba3ccc8fe77b67aff2db8f5827d7cb752ce11f Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:03 +0100 Subject: [ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail This patch implements the recommended workaround for erratum 411920 (ARM1136, ARM1156, ARM1176). Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/cache-v6.S | 33 +++++++++++++++++++++++++++++++++ arch/arm/mm/flush.c | 23 +++++++++++++++++++++-- 2 files changed, 54 insertions(+), 2 deletions(-) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 2c6c2a7c05a..8f5c13f4c93 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -20,6 +20,31 @@ #define D_CACHE_LINE_SIZE 32 #define BTB_FLUSH_SIZE 8 +#ifdef CONFIG_ARM_ERRATA_411920 +/* + * Invalidate the entire I cache (this code is a workaround for the ARM1136 + * erratum 411920 - Invalidate Instruction Cache operation can fail. This + * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore. + * + * Registers: + * r0 - set to 0 + * r1 - corrupted + */ +ENTRY(v6_icache_inval_all) + mov r0, #0 + mrs r1, cpsr + cpsid ifa @ disable interrupts + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + msr cpsr_cx, r1 @ restore interrupts + .rept 11 @ ARM Ltd recommends at least + nop @ 11 NOPs + .endr + mov pc, lr +#endif + /* * v6_flush_cache_all() * @@ -31,7 +56,11 @@ ENTRY(v6_flush_kern_cache_all) mov r0, #0 #ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate +#ifndef CONFIG_ARM_ERRATA_411920 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate +#else + b v6_icache_inval_all +#endif #else mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate #endif @@ -103,7 +132,11 @@ ENTRY(v6_coherent_user_range) mov r0, #0 #ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c10, 4 @ drain write buffer +#ifndef CONFIG_ARM_ERRATA_411920 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate +#else + b v6_icache_inval_all +#endif #else mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB #endif diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 4e283481cee..c07222eb5ce 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -18,6 +18,10 @@ #include "mm.h" +#ifdef CONFIG_ARM_ERRATA_411920 +extern void v6_icache_inval_all(void); +#endif + #ifdef CONFIG_CPU_CACHE_VIPT #define ALIAS_FLUSH_START 0xffff4000 @@ -32,10 +36,15 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) asm( "mcrr p15, 0, %1, %0, c14\n" " mcr p15, 0, %2, c7, c10, 4\n" +#ifndef CONFIG_ARM_ERRATA_411920 " mcr p15, 0, %2, c7, c5, 0\n" +#endif : : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) : "cc"); +#ifdef CONFIG_ARM_ERRATA_411920 + v6_icache_inval_all(); +#endif } void flush_cache_mm(struct mm_struct *mm) @@ -48,11 +57,16 @@ void flush_cache_mm(struct mm_struct *mm) if (cache_is_vipt_aliasing()) { asm( "mcr p15, 0, %0, c7, c14, 0\n" + " mcr p15, 0, %0, c7, c10, 4\n" +#ifndef CONFIG_ARM_ERRATA_411920 " mcr p15, 0, %0, c7, c5, 0\n" - " mcr p15, 0, %0, c7, c10, 4" +#endif : : "r" (0) : "cc"); +#ifdef CONFIG_ARM_ERRATA_411920 + v6_icache_inval_all(); +#endif } } @@ -67,11 +81,16 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned if (cache_is_vipt_aliasing()) { asm( "mcr p15, 0, %0, c7, c14, 0\n" + " mcr p15, 0, %0, c7, c10, 4\n" +#ifndef CONFIG_ARM_ERRATA_411920 " mcr p15, 0, %0, c7, c5, 0\n" - " mcr p15, 0, %0, c7, c10, 4" +#endif : : "r" (0) : "cc"); +#ifdef CONFIG_ARM_ERRATA_411920 + v6_icache_inval_all(); +#endif } } -- cgit From 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:09 +0100 Subject: [ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch This patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum. The BTAC/BTB is now flushed at every context switch. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index d1ebec42521..fc81159596f 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -95,6 +95,9 @@ ENTRY(cpu_v7_switch_mm) mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id orr r0, r0, #TTB_FLAGS +#ifdef CONFIG_ARM_ERRATA_430973 + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB +#endif mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 @@ -180,6 +183,11 @@ __v7_setup: stmia r12, {r0-r5, r7, r9, r11, lr} bl v7_flush_dcache_all ldmia r12, {r0-r5, r7, r9, r11, lr} +#ifdef CONFIG_ARM_ERRATA_430973 + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 6) @ set IBE to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif mov r10, #0 #ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate -- cgit From 855c551f5b8cc3815d58e1056c1f1e7c461e2d24 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:15 +0100 Subject: [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created This patch adds a workaround for the 458693 Cortex-A8 (r2p0) erratum. It sets the corresponding bits in the auxiliary control register so that the PLD instruction becomes a NOP. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index fc81159596f..370baa7a0f0 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -187,6 +187,12 @@ __v7_setup: mrc p15, 0, r10, c1, c0, 1 @ read aux control register orr r10, r10, #(1 << 6) @ set IBE to 1 mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif +#ifdef CONFIG_ARM_ERRATA_458693 + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 5) @ set L1NEON to 1 + orr r10, r10, #(1 << 9) @ set PLDNOP to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register #endif mov r10, #0 #ifdef HARVARD_CACHE -- cgit From 0516e4643cd22fc9f535aef02ad1de66c382c93b Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:20 +0100 Subject: [ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It configures the L2 cache auxiliary control register so that the Write Allocate mode for the L2 cache is disabled. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 370baa7a0f0..f2305441e7d 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -193,6 +193,11 @@ __v7_setup: orr r10, r10, #(1 << 5) @ set L1NEON to 1 orr r10, r10, #(1 << 9) @ set PLDNOP to 1 mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif +#ifdef CONFIG_ARM_ERRATA_460075 + mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register + orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit + mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register #endif mov r10, #0 #ifdef HARVARD_CACHE -- cgit