From d96a980441a70168a8ead0a0f23c4c63725da5fa Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 16 Apr 2008 00:12:39 +0100 Subject: [ARM] 4986/1: S3C24XX: Simtec machines need UCLK as parent to DCLK All current Simtec designs source the DCLK outputs from the UPLL. This means the DCLK's parent must be set to UPLL so that anything enabling and disabling an UPLL sourced clock does not shutdown the DCLK due to missing open counts. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/mach-vr1000.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-s3c2410/mach-vr1000.c') diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 3aade7b78fe..c56423373ff 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -393,7 +393,7 @@ static void __init vr1000_map_io(void) { /* initialise clock sources */ - s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.parent = &clk_upll; s3c24xx_dclk0.rate = 12*1000*1000; s3c24xx_dclk1.parent = NULL; -- cgit