From b0e66522f4d86713b0450255210e26c4f11ee86b Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 30 Jul 2009 23:23:20 +0100 Subject: ARM: S3C24XX: Add BWSCON per-bank information. Add definitions and an accessor macro to deal with reading bus information from S3C2410_BWSCON for any given numbered bank. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/regs-mem.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h index 57759804e2f..7f7c5294796 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h @@ -73,6 +73,16 @@ #define S3C2410_BWSCON_WS7 (1<<30) #define S3C2410_BWSCON_ST7 (1<<31) +/* accesor functions for getting BANK(n) configuration. (n != 0) */ + +#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf) + +#define S3C2410_BWSCON_DW8 (0) +#define S3C2410_BWSCON_DW16 (1) +#define S3C2410_BWSCON_DW32 (2) +#define S3C2410_BWSCON_WS (1 << 2) +#define S3C2410_BWSCON_ST (1 << 3) + /* memory set (rom, ram) */ #define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004) #define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008) -- cgit From 25400036867fa7a135fca17810555400d176acaa Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 30 Jul 2009 23:23:36 +0100 Subject: ARM: S3C2412: Update memory register mapping and definitions Update the mapping of the memory controler registers and add the missing definitions of the register block for the SSMC. The register contents definitions can be found in the pl093 header. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/map.h | 7 +++++++ .../mach-s3c2410/include/mach/regs-s3c2412-mem.h | 23 ++++++++++++++++++++-- 2 files changed, 28 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index e99b212cb1c..11cce097550 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -67,6 +67,13 @@ #define S3C2443_PA_HSMMC (0x4A800000) #define S3C2443_SZ_HSMMC (256) +/* S3C2412 memory and IO controls */ +#define S3C2412_PA_SSMC (0x4F000000) +#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) + +#define S3C2412_PA_EBI (0x48800000) +#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000) + /* physical addresses of all the chip-select areas */ #define S3C2410_CS0 (0x00000000) diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h index a4bf2712317..fb635251509 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h @@ -14,9 +14,11 @@ #ifndef __ASM_ARM_REGS_S3C2412_MEM #define __ASM_ARM_REGS_S3C2412_MEM -#ifndef S3C2412_MEMREG #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#endif +#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) + +#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) +#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) #define S3C2412_BANKCFG S3C2412_MEMREG(0x00) #define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) @@ -26,4 +28,21 @@ #define S3C2412_REFRESH S3C2412_MEMREG(0x10) #define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) +/* EBI control registers */ + +#define S3C2412_EBI_PR S3C2412_EBIREG(0x00) +#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04) + +/* SSMC control registers */ + +#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00) +#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00) +#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04) +#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08) +#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C) +#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10) +#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14) +#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18) +#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C) + #endif /* __ASM_ARM_REGS_S3C2412_MEM */ -- cgit From 14077ea63b5aea1db0142c1085d24aa0d11b9d36 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Wed, 1 Jul 2009 17:47:06 +0200 Subject: ARM: S3C: move s3c_device_nand from plat-s3c24xx to plat-s3c Move the s3c_device_nand platform device from plat-s3c24xx to plat-s3c, now that the nand driver also support the s3c64xx devices. Signed-off-by: Peter Korsgaard Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/map.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index e99b212cb1c..e9821850065 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -103,5 +103,6 @@ #define S3C_PA_UART S3C24XX_PA_UART #define S3C_PA_USBHOST S3C2410_PA_USBHOST #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC +#define S3C_PA_NAND S3C24XX_PA_NAND #endif /* __ASM_ARCH_MAP_H */ -- cgit From d91e9a7ab93e09e5a0fbed73f3a6a330f14620a4 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 5 Aug 2009 18:29:57 +0100 Subject: ARM: S3C24XX: Add platform device for AC97 controller Move the definition of the "generic" IRQ in the process. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/irqs.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 2a2384ffa7b..6c12c6312ad 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h @@ -164,6 +164,12 @@ #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 +#ifdef CONFIG_CPU_S3C2440 +#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 +#else +#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97 +#endif + /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ #define FIQ_START IRQ_EINT0 -- cgit From a2c195fdde20772a90ee98ce3523dcfbda49eee6 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 3 Aug 2009 17:26:50 +0100 Subject: ARM: S3C24XX: Add SPI bus 1 on GPD8 through GPD10 Add configuration callback for SPI bus 1 on GPD[8..10] and ensure the correct GPIO configuration register definitions in regs-gpio.h Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 4 +++- arch/arm/mach-s3c2410/include/mach/spi.h | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index b278d0c45cc..f6e8eec879c 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -328,13 +328,15 @@ #define S3C2410_GPD8_VD16 (0x02 << 16) #define S3C2400_GPD8_TOUT3 (0x02 << 16) +#define S3C2440_GPD8_SPIMISO1 (0x03 << 16) #define S3C2410_GPD9_VD17 (0x02 << 18) #define S3C2400_GPD9_TCLK0 (0x02 << 18) -#define S3C2410_GPD9_MASK (0x03 << 18) +#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) #define S3C2410_GPD10_VD18 (0x02 << 20) #define S3C2400_GPD10_nWAIT (0x02 << 20) +#define S3C2440_GPD10_SPICLK1 (0x03 << 20) #define S3C2410_GPD11_VD19 (0x02 << 22) diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h index 1d300fb112b..193b39d654e 100644 --- a/arch/arm/mach-s3c2410/include/mach/spi.h +++ b/arch/arm/mach-s3c2410/include/mach/spi.h @@ -30,4 +30,7 @@ extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, int enable); +extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, + int enable); + #endif /* __ASM_ARCH_SPI_H */ -- cgit