From baf6332a238a680ef3add9cfb0729f136da886b8 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Mon, 12 May 2008 14:02:25 -0700 Subject: atmel_lcdfb: fix pixclock divider calculation Fix divider calculation and allow CLKVAL = 0 (divisor 2) It was not possible to get the clock value 0 (divisor 2) because the test "<=0" force the BYPASS bit to be activated instead. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Nicolas Ferre Cc: Per Hedblom Cc: Roel Kluin <12o3l@tiscali.nl> Cc: Jan Weber Cc: Andrew Victor Cc: Haavard Skinnemoen Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/video/atmel_lcdfb.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 8ffdf357876..b004036d408 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -441,14 +441,15 @@ static int atmel_lcdfb_set_par(struct fb_info *info) value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock)); - value = (value / 2) - 1; - dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", value); - - if (value <= 0) { + if (value < 2) { dev_notice(info->device, "Bypassing pixel clock divider\n"); lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); } else { - lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET); + value = (value / 2) - 1; + dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", + value); + lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, + value << ATMEL_LCDC_CLKVAL_OFFSET); info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1))); dev_dbg(info->device, " updated pixclk: %lu KHz\n", PICOS2KHZ(info->var.pixclock)); -- cgit