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* [PATCH] x86-64: clean up local_add/sub argumentsAndi Kleen2005-09-121-2/+2
| | | | Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: i386/x86-64: Fix time going twice as fast problem on ATI ↵Chuck Ebbert2005-09-122-0/+4
| | | | | | | | | | | Xpress chipsets Original patch from Bertro Simul This is probably still not quite correct, but seems to be the best solution so far. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: reduce x86-64 bug frame by 4 bytesJan Beulich2005-09-121-6/+4
| | | | | | | | As mentioned before, the size of the bug frame can be further reduced while continuing to use instructions to encode the information. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Make dmi_find_device for !DMI case inlineAndi Kleen2005-09-121-1/+1
| | | | | | | Otherwise it will generate warnings and be generated many times. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Lose constraints on cmpxchgJan Beulich2005-09-121-3/+3
| | | | | | | | | While only cosmetic for x86-64, this adjusts the cmpxchg code appearantly inherited from i386 to use more generic constraints. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Declare NMI_VECTOR and handle it in the IPI sending code.Jan Beulich2005-09-122-3/+15
| | | | | Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Remove unused vxtime.hz fieldAndi Kleen2005-09-121-1/+0
| | | | | Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Set the stack pointer correctly in init_thread and init_tssAndi Kleen2005-09-121-1/+7
| | | | | Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Safe interrupts in oops_begin/endJan Beulich2005-09-122-5/+2
| | | | | | | | | Rather than blindly re-enabling interrupts in oops_end(), save their state in oope_begin() and then restore that state. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Merge msr.c with i386 versionAndi Kleen2005-09-121-12/+27
| | | | | | | | | | The only difference was the inline assembly, so move that into asm/msr.h and merge with the i386 version. This adds some missing sysfs support code to x86-64. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Fix CFI informationJan Beulich2005-09-122-8/+23
| | | | | | | | | | | | Being the foundation for reliable stack unwinding, this fixes CFI unwind annotations in many low-level x86_64 routines, plus a config option (available to all architectures, and also present in the previously sent patch adding such annotations to i386 code) to enable them separatly rather than only along with adding full debug information. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Add dma_sync_single_range_for_{cpu,device}Andi Kleen2005-09-121-0/+5
| | | | | | | | | Currently just defined to their non range parts. Pointed out by John Linville Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] Replace extern inline with static inline in asm-x86_64/*Adrian Bunk2005-09-1210-30/+30
| | | | | | | | | They should be identical in the kernel now, but this makes it consistent with other code. Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] Increase nodemap hash.Nakul Saraiya2005-09-121-1/+1
| | | | | | | | | Needed for some newer Opteron systems with E stepping and memory relocation enabled. The node addresses are different in lower bits now so the nodemap hash function needs to be enlarged. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Fix off by one in pfn_validJim Paradis2005-09-121-1/+1
| | | | | | | When I gave proposed the fix to pfn_valid() for RHEL4, Stephen Tweedie's sharp eyes caught this: Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386: add memory clobbers to syscall macrosAndi Kleen2005-09-121-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As noted by matz@suse.de The problem is, that on i386 the syscallN macro is defined like so: long __res; \ __asm__ volatile ("int $0x80" \ : "=a" (__res) \ : "0" (__NR_##name),"b" ((long)(arg1)),"c" ((long)(arg2)), \ "d" ((long)(arg3)),"S" ((long)(arg4)),"D" ((long)(arg5))); \ If one of the arguments (in the _llseek syscall it's the arg4) is a pointer which the syscall is expected to write to (to the memory pointed to by this ptr), then this side-effect is not captured in the asm. If anyone uses this macro to define it's own version of the syscall (sometimes necessary when not using glibc) and it's inlined, then GCC doesn't know that this asm write to "*dest", when called like so for instance: out = 1; llseek (fd, bla, blubb, &out, trara) use (out); Here nobody tells GCC that "out" actually is written to (just a pointer to it is passed to the asm). Hence GCC might (and in the above bug did) copy-propagate "1" into the second use of "out". The easiest solution would be to add a "memory" clobber to the definition of this syscall macro. As this is a syscall, it shouldn't inhibit too many optimizations. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Increase TLB flush array sizeAndi Kleen2005-09-122-1/+9
| | | | | | | | | | | | | | | | | | | | | | The generic TLB flush functions kept upto 506 pages per CPU to avoid too frequent IPIs. This value was done for the L1 cache of older x86 CPUs, but with modern CPUs it does not make much sense anymore. TLB flushing is slow enough that using the L2 cache is fine. This patch increases the flush array on x86-64 to cache 5350 pages. That is roughly 20MB with 4K pages. It speeds up large munmaps in multithreaded processes on SMP considerably. The cost is roughly 42k of memory per CPU, which is reasonable. I only increased it on x86-64 for now, but it would probably make sense to increase it everywhere. Embedded architectures with SMP may keep it smaller to save some memory per CPU. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Don't include config.h in asm/timex.hAndi Kleen2005-09-121-1/+0
| | | | | | | | | asm-x86-64/timex.h does not reference CONFIG constants. Do not need to include config.h. Signed-off-by: Grant Grundler <iod00d@hp.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Some cleanup and optimization to the processor data area.Andi Kleen2005-09-123-11/+17
| | | | | | | | | - Remove unused irqrsp field - Remove pda->me - Optimize set_softirq_pending slightly Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Make remote TLB flush more scalableAndi Kleen2005-09-121-8/+9
| | | | | | | | | | | | | | | | | | | | | | | Instead of using a global spinlock to protect the state of the remote TLB flush use a lock and state for each sending CPU. To tell the receiver where to look for the state use 8 different call vectors. Each CPU uses a specific vector to trigger flushes on other CPUs. Depending on the received vector the target CPUs look into the right per cpu variable for the flush data. When the system has more than 8 CPUs they are hashed to the 8 available vectors. The limited global vector space forces us to this right now. In future when interrupts are split into per CPU domains this could be fixed, at the cost of needing more IPIs in flat mode. Also some minor cleanup in the smp flush code and remove some outdated debug code. Requires patch to move cpu_possible_map setup earlier. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Use ACPI PXM to parse PCI<->node assignmentsAndi Kleen2005-09-124-3/+6
| | | | | | | Since this is shared code I had to implement it for i386 too Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Remove redundant max_mapnr and replace with end_pfnAndi Kleen2005-09-122-3/+3
| | | | | | | | The FLATMEM people added it, but there doesn't seem a good reason because end_pfn is identical. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Avoid unnecessary double bouncing for swiotlbAndi Kleen2005-09-121-3/+3
| | | | | | | | | PCI_DMA_BUS_IS_PHYS has to be zero even when the GART IOMMU is disabled and the swiotlb is used. Otherwise the block layer does unnecessary double bouncing. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Support dualcore and 8 socket systems in k8 fallback node ↵Andi Kleen2005-09-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | parsing In particular on systems where the local APIC space and node space is very different from the Linux CPU number space. Previously the older NUMA setup code directly parsing the K8 northbridge registers had some issues on 8 socket or dual core systems. This patch fixes them. This is mainly done by fixing some confusion between Linux CPU numbers and local APIC ids. We now pass the local APIC IDs to later code, which avoids mismatches. Also add some heuristics to detect cases where the Hypertransport nodeids and the local APIC IDs don't match, but are shifted by a constant offset. This is still all quite hackish, hopefully BIOS writers fill in correct SRATs instead. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Don't cache align PDA on UP buildsAndi Kleen2005-09-121-1/+1
| | | | | | | Suggested by someone I forgot who sorry. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Don't assign CPU numbers in SRAT parsingAndi Kleen2005-09-121-0/+2
| | | | | | | | | Do that later when the CPU boots. SRAT just stores the APIC<->Node mapping node. This fixes problems on systems where the order of SRAT entries does not match the MADT. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Remove esr disable hack in APIC codeAndi Kleen2005-09-121-1/+0
| | | | | | | | This was just needed for the Numasaurus, which fortunately doesn't support x86-64 CPUs. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64: Remove obsolete APIC "write around" bug workaroundAndi Kleen2005-09-121-3/+3
| | | | | | | | | No x86-64 chipset has this bug Generated code doesn't change because it was always disabled. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] cpuset semaphore depth check optimizePaul Jackson2005-09-121-1/+0
| | | | | | | | | | | | | | | | Optimize the deadlock avoidance check on the global cpuset semaphore cpuset_sem. Instead of adding a depth counter to the task struct of each task, rather just two words are enough, one to store the depth and the other the current cpuset_sem holder. Thanks to Nikita Danilov for the idea. Signed-off-by: Paul Jackson <pj@sgi.com> [ We may want to change this further, but at least it's now a totally internal decision to the cpusets code ] Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] crc16: remove w1 specific comments.Evgeniy Polyakov2005-09-121-15/+1
| | | | | | | | | | Remove w1 comments from crc16.h and move specific constants into w1_ds2433.c where they are used. Replace %d with %zd. Signed-off-by: Evgeniy Polyakov <johnpol@2ka.mipt.ru> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/paulus/ppc64-2.6 Linus Torvalds2005-09-1210-56/+208
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| * [PATCH] ppc64: Remove unused codeAnton Blanchard2005-09-121-4/+0
| | | | | | | | | | | | | | ppc64_attention_msg and ppc64_dump_msg are not used so remove them. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [PATCH] ppc64: Add ptrace data breakpoint supportAnton Blanchard2005-09-125-0/+39
| | | | | | | | | | | | | | Add hardware data breakpoint support. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [PATCH] ppc64: Add definitions for new PTRACE callsAnton Blanchard2005-09-123-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add PTRACE_GET_DEBUGREG/PTRACE_SET_DEBUGREG. The definition is as follows: /* * Get or set a debug register. The first 16 are DABR registers and the * second 16 are IABR registers. */ #define PTRACE_GET_DEBUGREG 25 #define PTRACE_SET_DEBUGREG 26 DABR == data breakpoint and IABR = instruction breakpoint in IBM speak. We could split out the IABR into 2 more ptrace calls but I figured there was no need and 16 DABR registers should be more than enough (POWER4/POWER5 have one). - Add 2 new SIGTRAP si_codes: TRAP_HWBKPT and TRAP_BRANCH. I couldnt find any standards on either of these so I copied what ia64 is doing. Again this might be better placed in include/asm-generic/siginfo.h Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [PATCH] ppc64: ptrace cleanupsAnton Blanchard2005-09-121-52/+69
| | | | | | | | | | | | | | | | | | | | | | - Remove the PPC_REG* defines - Wrap some more stuff with ifdef __KERNEL__ - Add missing PT_TRAP, PT_DAR, PT_DSISR defines - Add PTRACE_GETEVRREGS/PTRACE_SETEVRREGS, even though we dont use it on ppc64 we dont want to allocate them for something else. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [PATCH] ppc64: Add PTRACE_{GET|SET}VRREGSRobert Jennings2005-09-121-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ptrace get and set methods for VMX/Altivec registers present in the ppc tree were missing for ppc64. This patch adds the 32-bit and 64-bit methods. Updated with the suggestions from Anton following the lines of his code snippet. Added: - flush_altivec_to_thread calls as suggested by Anton - piecewise copy of structure to preserve 32-bit vrsave data as per Anton (I consolidated the 32 and 64bit versions with 2 helper macros - Anton) Signed-off-by: Robert C Jennings <rcjenn@austin.ibm.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * ppc64: Set up PCI tree from Open Firmware device treePaul Mackerras2005-09-122-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds code which gives us the option on ppc64 of instantiating the PCI tree (the tree of pci_bus and pci_dev structs) from the Open Firmware device tree rather than by probing PCI configuration space. The OF device tree has a node for each PCI device and bridge in the system, with properties that tell us what addresses the firmware has configured for them and other details. There are a couple of reasons why this is needed. First, on systems with a hypervisor, there is a PCI-PCI bridge per slot under the PCI host bridges. These PCI-PCI bridges have special isolation features for virtualization. We can't write to their config space, and we are not supposed to be reading their config space either. The firmware tells us about the address ranges that they pass in the OF device tree. Secondly, on powermacs, the interrupt controller is in a PCI device that may be behind a PCI-PCI bridge. If we happened to take an interrupt just at the point when the device or a bridge on the path to it was disabled for probing, we would crash when we try to access the interrupt controller. I have implemented a platform-specific function which is called for each PCI bridge (host or PCI-PCI) to say whether the code should look in the device tree or use normal PCI probing for the devices under that bridge. On pSeries machines we use the device tree if we're running under a hypervisor, otherwise we use normal probing. On powermacs we use normal probing for the AGP bridge, since the device for the AGP bridge itself isn't shown in the device tree (at least on my G5), and the device tree for everything else. This has been tested on a dual G5 powermac, a partition on a POWER5 machine (running under the hypervisor), and a legacy iSeries partition. Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [PATCH] m68knommu: allow for SDRAM and GPIO differences on 5270/1 and 5274/5 ↵Greg Ungerer2005-09-111-2/+19
| | | | | | | | | | | | | | | | | | | | | | processors Allow for differences in the SDRAM controller setup and GPIO pin setup of the 5270/1 and 5274/5 parts. With separate config options for each now this no longer needs to be board specific. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] m68knommu: add SPI register definitions for 528x processorsGreg Ungerer2005-09-111-0/+112
| | | | | | | | | | | | | | | | | | Add QSPI register definitions of ColdFIre 528x processor SPI controller. Patch originally submitted by Derek Cheung <derek.cheung@sympatico.ca> Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] m68knommu: dma support for 523x processorsGreg Ungerer2005-09-111-1/+1
| | | | | | | | | | | | | | Support the DMA unit of the ColdFire 523x processor family. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] m68knommu: change addr arg to const in bitops.h/find_next_zero_bit()Greg Ungerer2005-09-111-1/+1
| | | | | | | | | | | | | | | | Change addr arg to find_next_zero_bit to be a const. Cleans up compiler warning. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] m68knommu: correct prototype args in checksum.hGreg Ungerer2005-09-111-3/+4
| | | | | | | | | | | | | | | | Bring arg types for csum_partial_copy and csum_paritial_copy_from_user prototypes into line with their actual implementation. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] m68knommu: cache support for 523x/528x processorsGreg Ungerer2005-09-111-14/+11
|/ | | | | | | | | Add support for the cache of the ColdFIre 523x family of processors. Enable the 528x cache by default now, all final shipping silicon has the cache bug fixed. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Pull sn-features into release branchTony Luck2005-09-112-9/+84
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| * [IA64-SGI] Add new vendor-specific SAL calls for:Jack Steiner2005-08-312-9/+84
| | | | | | | | | | | | | | | | | | | | | | | | - notifying the PROM of specific features that are supported by the OS. This is used to enable PROM feature if and only if the corresponding feature is implemented in the OS - fetch feature sets that are supported by the current PROM. This allows the OS to selectively enable features when the PROM support is available. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] MCA/INIT: remove obsolete unwind codeKeith Owens2005-09-111-7/+0
| | | | | | | | | | | | | | | | Delete the special case unwind code that was only used by the old MCA/INIT handler. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [PATCH] MCA/INIT: use per cpu stacksKeith Owens2005-09-112-136/+91
| | | | | | | | | | | | | | | | | | | | | | | | The bulk of the change. Use per cpu MCA/INIT stacks. Change the SAL to OS state (sos) to be per process. Do all the assembler work on the MCA/INIT stacks, leaving the original stack alone. Pass per cpu state data to the C handlers for MCA and INIT, which also means changing the mca_drv interfaces slightly. Lots of verification on whether the original stack is usable before converting it to a sleeping process. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] MCA/INIT: add an extra thread_info flagKeith Owens2005-09-112-1/+3
| | | | | | | | | | | | | | | | Add an extra thread_info flag to indicate the special MCA/INIT stacks. Mainly for debuggers. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [PATCH] MCA/INIT: scheduler hooksKeith Owens2005-09-111-0/+2
| | | | | | | | | | | | | | Scheduler hooks to see/change which process is deemed to be on a cpu. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | Merge master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband Linus Torvalds2005-09-115-5/+141
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