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kernel-crypto.git
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ncr-audit
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ncr-rhel5-patches
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ncr-userspace-crypto
User-space crypto API development for Linux
Miloslav Trmac
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path:
root
/
include
/
asm-x86
/
cpufeature.h
Commit message (
Expand
)
Author
Age
Files
Lines
*
x86_64: add pseudo-features for 32-bit compat syscall
Jeremy Fitzhardinge
2008-07-11
1
-2
/
+2
*
-
.
Merge branches 'x86/mmio', 'x86/delay', 'x86/idle', 'x86/oprofile', 'x86/debu...
Ingo Molnar
2008-07-08
1
-0
/
+1
|
\
\
|
|
*
x86: add X86_FEATURE_IBS cpu feature
Robert Richter
2008-06-24
1
-0
/
+1
|
|
/
*
/
x86: setup_force_cpu_cap(): don't do clear_bit(non-unsigned-long)
Andrew Morton
2008-05-25
1
-2
/
+2
|
/
*
x86: PAT infrastructure patch
venkatesh.pallipadi@intel.com
2008-04-17
1
-0
/
+1
*
x86: add cpu_has_arch_perfmon
stephane eranian
2008-04-17
1
-0
/
+1
*
x86: clean up cpu capabilities accesses
Ingo Molnar
2008-04-17
1
-1
/
+5
*
x86: add feature macros for the gbpages cpuid bit
Andi Kleen
2008-02-04
1
-0
/
+2
*
x86: unify CPU feature string names
H. Peter Anvin
2008-02-04
1
-3
/
+9
*
x86: convert TSC disabling to generic cpuid disable bitmap
Andi Kleen
2008-01-30
1
-0
/
+4
*
x86: add framework to disable CPUID bits on the command line
Andi Kleen
2008-01-30
1
-0
/
+4
*
x86: 64-bit, remove redundant cpu_has_ definitions
Kyle McMartin
2008-01-30
1
-15
/
+0
*
x86: remove the now unused X86_FEATURE_SYNC_RDTSC
Andi Kleen
2008-01-30
1
-1
/
+1
*
x86: Implement support to synchronize RDTSC with LFENCE on Intel CPUs
Andi Kleen
2008-01-30
1
-0
/
+1
*
x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs
Andi Kleen
2008-01-30
1
-0
/
+1
*
x86: x86-64 wired cpu_has macros
Roland McGrath
2008-01-30
1
-0
/
+12
*
x86: add set/clear_cpu_cap operations
Jeremy Fitzhardinge
2008-01-30
1
-1
/
+4
*
x86: clean up bitops-related warnings
Jeremy Fitzhardinge
2008-01-30
1
-1
/
+1
*
x86: cleanup tlbflush.h variants
Thomas Gleixner
2008-01-30
1
-0
/
+9
*
x86: unify asm/cpufeature.h
H. Peter Anvin
2008-01-30
1
-4
/
+187
*
i386/x86_64: move headers to include/asm-x86
Thomas Gleixner
2007-10-11
1
-0
/
+5