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path: root/drivers/net/tg3.h
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* [TG3]: Add indirect register method for 5703 behind ICHMichael Chan2005-08-291-0/+1
| | | | | | | | | | | | | | | | | | | | This patch adds the new workaround for 5703 A1/A2 if it is behind certain ICH bridges. The workaround disables memory and uses config. cycles only to access all registers. The 5702/03 chips can mistakenly decode the special cycles from the ICH chipsets as memory write cycles, causing corruption of register and memory space. Only certain ICH bridges will drive special cycles with non-zero data during the address phase which can fall within the 5703's address range. This is not an ICH bug as the PCI spec allows non-zero address during special cycles. However, only these ICH bridges are known to drive non-zero addresses during special cycles. The indirect_lock is also changed to spin_lock_irqsave from spin_lock_bh because it is used in irq handler when using the indirect method to disable interrupts. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add mailbox read methodMichael Chan2005-08-291-0/+1
| | | | | | | | This patch adds the mailbox read method and also adds an inline function tw32_mailbox_f() for mailbox writes that require read flush. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add basic register access function pointersMichael Chan2005-08-291-0/+8
| | | | | | | | | | | | | | This patch adds the basic function pointers to do register accesses in the fast path. This was suggested by David Miller. The idea is that various register access methods for different hardware errata can easily be implemented with these function pointers and performance will not be degraded on chips that use normal register access methods. The various register read write macros (e.g. tw32, tr32, tw32_mailbox) are redefined to call the function pointers. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add 5780 fiber supportMichael Chan2005-07-251-0/+4
| | | | | | | | | | Add 5780S support by adding a new tg3_setup_fiber_mii_phy() function and a timer function for parallel link detection. 5780S uses standard MII registers for 1000BaseX and runs in GMII mode as opposed to TBI mode on older serdes chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: consolidate all DMA water mark settingsMichael Chan2005-07-251-0/+3
| | | | | | | | Consolidate all DMA watermark settings for standard and jumbo frames on all chips in tg3_init_bufmgr_config() and add new settings for 5780. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add variable buffer size for standard ringMichael Chan2005-07-251-0/+2
| | | | | | | | Add a new rx_pkt_buf_sz to the tg3 structure to support variable buffer sizes on the standard ring. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add 5780 basic jumbo frame supportMichael Chan2005-07-251-1/+2
| | | | | | | | | | | | Add basic jumbo frames support for 5780. This chip supports jumbo frames on the standard receive ring without the jumbo ring. The TG3_FLAG_JUMBO_ENABLE is changed to TG3_FLAG_JUMBO_RING_ENABLE to indicate using the jumbo ring on 5704 and older chips. A new TG3_FLG2_JUMBO_CAPABLE flag is added to indicate jumbo frames support with or without the jumbo ring. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add 5780 basic supportMichael Chan2005-07-251-0/+3
| | | | | | | Add 5780 PCI IDs, chip IDs, and other basic support. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: support for ethtool -CMichael Chan2005-07-051-0/+10
| | | | | | | Add support for ethtool -C with verification of user parameters. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Eliminate all hw IRQ handler spinlocks.David S. Miller2005-06-241-5/+19
| | | | | | | | | | | | | | | | | | | | | Move all driver spinlocks to be taken at sw IRQ context only. This fixes the skb_copy() we were doing with hw IRQs disabled (which is illegal and triggers a BUG() with HIGHMEM enabled). It also simplifies the locking all over the driver tremendously. We accomplish this feat by creating a special sequence to synchronize with the hw IRQ handler using a binary state and synchronize_irq(). This idea is from Herbert Xu. Thanks to Michael Chan for helping to track down all of the race conditions in initial versions of this code. Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Set minimal hw interrupt mitigation.David S. Miller2005-05-181-1/+5
| | | | | | | | | | | | | | | | | | | Even though we do software interrupt mitigation via NAPI, it still helps to have some minimal hw assisted mitigation. This helps, particularly, on systems where register I/O overhead is much greater than the CPU horsepower. For example, it helps on NUMA systems. In such cases the PIO overhead to disable interrupts for NAPI accounts for the majority of the packet processing cost. The CPU is fast enough such that only a single packet is processed by each NAPI poll call. Thanks to Michael Chan for reviewing this patch. Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add tagged status support.David S. Miller2005-05-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | When supported, use the TAGGED interrupt processing support the chip provides. In this mode, instead of a "on/off" binary semaphore, an incrementing tag scheme is used to ACK interrupts. All MSI supporting chips support TAGGED mode, so the tg3_msi() interrupt handler uses it unconditionally. This invariant is verified when MSI support is tested. Since we can invoke tg3_poll() multiple times per interrupt under high packet load, we fetch a new copy of the tag value in the status block right before we actually do the work. Also, because the tagged status tells the chip exactly which work we have processed, we can make two optimizations: 1) tg3_restart_ints() need not check tg3_has_work() 2) the tg3_timer() need not poke the chip 10 times per second to keep from losing interrupt events Based upon valuable feedback from Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add msi supportMichael Chan2005-04-211-0/+1
| | | | | | | Add MSI support for 5751 C0 and 5752. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add nvram lock-out support for 5752 TPMMichael Chan2005-04-211-0/+1
| | | | | | | | Add support for the NVRAM lock-out feature for TPM in 5752. If lock-out is enabled, certain NVRAM registers cannot be written to. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add nvram detection for 5752Michael Chan2005-04-211-0/+14
| | | | | Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Add GPIO3 for 5752Michael Chan2005-04-211-0/+3
| | | | | | | | Add bit definitions for the new GPIO3 in 5752. GPIO3 must be driven as output when it is unused. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Workaround 5752 A0 chip IDMichael Chan2005-04-211-3/+3
| | | | | | | | | | The 5752 A0 chip ID is wrong in hardware. The simplest way to workaround it is to change it to the correct value in tp->pci_chip_rev_id. This way, it is easier to check for the ASIC_REV_5752 in the rest of the driver. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: Minor 5752 fixesMichael Chan2005-04-211-0/+1
| | | | | | | Some minor 5752 fixes mostly for correctness and add 5752 PHY ID. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add support for bcm5752 rev a1John W. Linville2005-04-211-1/+4
| | | | | | | | | Replace existing ASIC_REV_5752 definition with ASIC_REV_5752_A0, and add definition for ASIC_REV_5752_A1. Then, add ASIC_REV_5752_A1 to check for setting TG3_FLG2_5750_PLUS in tg3_get_invariants. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: define TG3_FLG2_5750_PLUS flagJohn W. Linville2005-04-211-0/+1
| | | | | | | | Define TG3_FLG2_5750_PLUS flag and set it in tg3_get_invariants for ASIC_REV_5750 or ASIC_REV_5752. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [TG3]: add basic bcm5752 supportJohn W. Linville2005-04-211-0/+1
| | | | | | | | | | Add ASIC_REV_5752 definition. Track-down all references to ASIC_REV_5750 and mirror them with references to the newly defined ASIC_REV_5752. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+2206
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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