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When the stacktrace simplification changes went in the function
definition on SH got skipped, fix it up so things build again.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The DMABRG is a special DMA unit within the SH7760 which does data
transfers from main memory to Audio units and USB shared memory.
It has 3 IRQ lines which generate 10 events, which have to be masked
unmasked and acked in a single 32bit register. It works independently
from the tradition SH DMAC, but blocks usage of DMAC channel 0.
This patch adds 2 functions to associate callbacks with DMABRG events
and initialization.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This adds basic support for clockevents and clocksources,
presently only implemented for TMU-based systems (which
are the majority of SH-3 and SH-4 systems).
The old NO_IDLE_HZ implementation is also dropped completely,
the only users of this were on TMU-based systems anyways.
More work needs to be done to generalize the TMU handling,
in that the current implementation is rather tied to the
notion of TMU0 and TMU1 utilization.
Additionally, as more SH timers switch over to this scheme,
we'll be able to gut most of the remaining system timer
infrastructure that existed before.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Most SH platforms aren't going to need more than a single active
region, ones that need more can pad this out as necessary.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This went in immediately after SH added the die chain notifiers,
so move over to that instead..
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Fix up the landisk build. When NR_IRQS was removed, landisk got missed
in the updates. Update the machvec for the landisk IRQs to get it
working again.
Signed-off-by: kogiidena <kogiidena@eggplant.ddo.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Currently the xloops calculation in ndelay() gets set to 0 when
calculated with HZ=250, fix up how we do the HZ factoring in order
to get this right for differing values.
Signed-off-by: kogiidena <kogiidena@eggplant.ddo.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Add a CPU flag for the CPUs that support 32-bit opcodes, which
gets passed down to userspace.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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There are a few different cases for figuring out how to
size the instruction. We read in the instruction located
at regs->pc - 4 when rewinding the opcode to figure out if
there's a 32-bit opcode before the faulting instruction, with
a default of a - 2 adjustment on a mismatch. In practice this
works for the cases where pc - 4 is just another 16-bit opcode,
or we happen to have a 32-bit and a 16-bit immediately
preceeding the pc value.
In the cases where we aren't rewinding, this is much less ugly..
We also don't bother fixing up the places where we're explicitly
dealing with 16-bit instructions, since this might lead to
confusion regarding the encoding size possibilities on other
CPU variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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SH-2A supports both 16 and 32-bit instructions, add a simple helper
for figuring out the instruction size in the places where there are
hardcoded 16-bit assumptions.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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modpost noticed that __div64_32 was being exported twice:
WARNING: lib/built-in: '__div64_32' exported twice. Previous export was
in arch/sh/kernel/built-in.ko
kill off the duplicate.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The only difference between these at the moment are the FPU
exceptions, and these are hidden away under CONFIG_SH_FPU
(which is only set for the SH-4 case anyways..).
This consolidates the two tables, and updates SH-4 to use
the updated copy.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This moves SH over to the generic quicklists. As per x86_64,
we have special mappings for the PGDs, so these go on their
own list..
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits)
ARM: OMAP: Fix GCC-reported compile time bug
ARM: OMAP: restore CONFIG_GENERIC_TIME
ARM: OMAP: partial LED fixes
ARM: OMAP: add SoSSI clock (call propagate_rate for childrens)
ARM: OMAP: FB sync with N800 tree (support for dynamic SRAM allocations)
ARM: OMAP: Sync framebuffer headers with N800 tree
ARM: OMAP: Mostly cosmetic to sync up with linux-omap tree
ARM: OMAP: Fix gpmc header
ARM: OMAP: Add mailbox support for IVA
[ARM] armv7: add Makefile and Kconfig entries
[ARM] armv7: add support for asid-tagged VIVT I-cache
[ARM] armv7: add dedicated ARMv7 barrier instructions
[ARM] armv7: Add ARMv7 cacheid macros
[ARM] armv7: add support for ARMv7 cores.
[ARM] Fix ARM branch relocation range
[ARM] 4363/1: AT91: Remove legacy PIO definitions
[ARM] 4361/1: AT91: Build error
ARM: OMAP: Sync core code with linux-omap
ARM: OMAP: Sync headers with linux-omap
ARM: OMAP: h4 must have blinky leds!!
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Fix GCC-reported compile time bug which prevents booting
when the framebuffer code is disabled.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Somehow this got lost in a merge ...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Partial fix for CONFIG_LEDS breakage ... at least allow platforms
using the debug-leds support (H4 for now) to build with the generic
LED support, and default the LED that would be the timer LED to
trigger using the "heartbeat" (timer driven, rate depends on load).
Right now only H2 and P2 seem to have working LED support; this
at least makes H4 less broken.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Clocks with the follow parent rate mode were not updating their
children at propagate rate time.
Signed-off-by: Imre Deak <imre.deak@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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- in addition to fixed FB regions - as passed by the bootloader -
allow dynamic allocations
- do some more checking against overlapping / reserved regions
- move the FB specific parts out from sram.c to fb.c
Signed-off-by: Imre Deak <imre.deak@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Mostly cosmetic to sync up with linux-omap tree
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch adds a generic mailbox interface for for DSP and IVA
(Image Video Accelerator). This patch itself doesn't contain
any IVA driver.
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch syncs omap specific core code with linux-omap.
Most of the changes are needed to fix bitrot caused by
driver updates in linux-omap tree.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This adds generic support for the "debug board" LEDs used by most of
TI's OMAP reference boards, and board-specific support for the H4.
It's derived from the not-as-generic stuff used by OMAP1 H2/H3/P2.
Those should be able to switch easily to this version, and clean up
some of the omap1-specific code.
In addition to H4 support, one key improvement is supporting not just
the "old" ARM debug LED API (with timer and idle LEDs, plus four that
can be handy for kernel debugging), but it also supports the "new"
generic LED API (most useful for usermode stuff IMO). Either or both
APIs can be enabled.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add controller platform data
Signed-off-by: Imre Deak <imre.deak@solidboot.com>
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Useful for debugging power management code.
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add DMA IRQ sanity checks
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Minor GPIO cleanups: remove needless #include, and omap_gpio_init()
should be __init, as well as all the board init code calling it.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Branches in the ARM architecture are restricted to a range of +/- 32MB.
However, the code in .../arch/arm/kernel/module.c::apply_relocate() was
checking offset against a range of +/- 64MB.
Signed-off-by: Kevin Welton <Kevin.Welton@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Close a hole in the ASID version switch, particularly the following
scenario:
CPU0 MM PID CPU1 MM PID
idle
A pid(A)
A idle(lazy tlb)
* new asid version triggered by B *
B pid(B)
A pid(A)
* MM A gets new asid version *
A idle(lazy tlb)
A pid(A)
* CPU1 doesn't see the new ASID *
The result is that CPU1 continues running with the hardware set
for the original (stale) ASID value, but mm->context.id contains
the new ASID value. The result is that the next MM fault on CPU1
updates the page table entries, but flush_tlb_page() fails due to
wrong ASID.
There is a related case with a threaded application is allocated
a new ASID on one CPU while another of its threads is running on
some different CPU. This scenario is not fixed by this commit.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Commit 86c0baf123e474b6eb404798926ecf62b426bf3a highlighted that we
may end up with the head text placed elsewhere in the kernel image.
Introduce a new .text.head section to contain the initial kernel
startup code, and always place this section at the beginning of the
kernel image.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Fix false warning:
WARNING: arch/arm/kernel/init_task.o - Section mismatch:
reference to .init.task:init_thread_union from .data between
'init_task' (at offset 0x4) and 'init_sighand'
caused by the section name starting with ".init".
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This allows the backtrace to dump the exception stack contents.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch adds the necessary lines to the Makefile and Kconfig files for
enabling the compilation of the ARMv7 CPU support.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARMv7 can have VIPT, PIPT or ASID-tagged VIVT I-cache. This patch
adds the necessary invalidation of the I-cache when the ASID numbers
are re-used.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch adds support for the ARMv7 cores.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
[POWERPC] Further fixes for the removal of 4level-fixup hack from ppc32
[POWERPC] EEH: log all PCI-X and PCI-E AER registers
[POWERPC] EEH: capture and log pci state on error
[POWERPC] EEH: Split up long error msg
[POWERPC] EEH: log error only after driver notification.
[POWERPC] fsl_soc: Make mac_addr const in fs_enet_of_init().
[POWERPC] Don't use SLAB/SLUB for PTE pages
[POWERPC] Spufs support for 64K LS mappings on 4K kernels
[POWERPC] Add ability to 4K kernel to hash in 64K pages
[POWERPC] Introduce address space "slices"
[POWERPC] Small fixes & cleanups in segment page size demotion
[POWERPC] iSeries: Make HVC_ISERIES the default
[POWERPC] iSeries: suppress build warning in lparmap.c
[POWERPC] Mark pages that don't exist as nosave
[POWERPC] swsusp: Introduce register_nosave_region_late
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Commit d1953c8888ef034b912ee33bc2ea2cce6a414402 removed the use of
4level-fixup.h for 32-bit systems under arch/powerpc. However, I
missed a few things activated on some configurations, resulting in
some warnings (at least with STRICT_MM_TYPECHECKS enabled) and build
errors in some circumstances. This fixes it.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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When an EEH event is detected, and after the device driver
has been notified, but before the device is reset, enable
MMIO to the adapter, and grab the contents of the PCI status
and command registers, the PCI-X status and command, and the
PCI-E capability 10 and AER registers. Pass these up to the
RTAS error log, and also printk them.
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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If an EEH event is observed, capture PCI config space info about
the device, wrap it up and pass it to the event logger. This
pach just slots in the basic logging function. A later patch
will provide for more through data gathering.
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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Make some minor adjustments to the EEH error messages.
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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It turns out many/most versions of firmware enable MMIO when
the slto-error-detail rtas call is made (in violation of the
architecture). Thus, it would be best to call slot-error-detail
only after notifying device drivers of a freeze, as otherwise,
a variety of strange and unexpected things may happen.
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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of_get_mac_address() returns a const pointer, so the result
should be stored in a const pointer.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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The SLUB allocator relies on struct page fields first_page and slab,
overwritten by ptl when SPLIT_PTLOCK: so the SLUB allocator cannot then
be used for the lowest level of pagetable pages. This was obstructing
SLUB on PowerPC, which uses kmem_caches for its pagetables. So convert
its pte level to use normal gfp pages (whereas pmd, pud and 64k-page pgd
want partpages, so continue to use kmem_caches for pmd, pud and pgd).
Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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This adds an option to spufs when the kernel is configured for
4K page to give it the ability to use 64K pages for SPE local store
mappings.
Currently, we are optimistic and try order 4 allocations when creating
contexts. If that fails, the code will fallback to 4K automatically.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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This adds the ability for a kernel compiled with 4K page size
to have special slices containing 64K pages and hash the right type
of hash PTEs.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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The basic issue is to be able to do what hugetlbfs does but with
different page sizes for some other special filesystems; more
specifically, my need is:
- Huge pages
- SPE local store mappings using 64K pages on a 4K base page size
kernel on Cell
- Some special 4K segments in 64K-page kernels for mapping a dodgy
type of powerpc-specific infiniband hardware that requires 4K MMU
mappings for various reasons I won't explain here.
The main issues are:
- To maintain/keep track of the page size per "segment" (as we can
only have one page size per segment on powerpc, which are 256MB
divisions of the address space).
- To make sure special mappings stay within their allotted
"segments" (including MAP_FIXED crap)
- To make sure everybody else doesn't mmap/brk/grow_stack into a
"segment" that is used for a special mapping
Some of the necessary mechanisms to handle that were present in the
hugetlbfs code, but mostly in ways not suitable for anything else.
The patch relies on some changes to the generic get_unmapped_area()
that just got merged. It still hijacks hugetlb callbacks here or
there as the generic code hasn't been entirely cleaned up yet but
that shouldn't be a problem.
So what is a slice ? Well, I re-used the mechanism used formerly by our
hugetlbfs implementation which divides the address space in
"meta-segments" which I called "slices". The division is done using
256MB slices below 4G, and 1T slices above. Thus the address space is
divided currently into 16 "low" slices and 16 "high" slices. (Special
case: high slice 0 is the area between 4G and 1T).
Doing so simplifies significantly the tracking of segments and avoids
having to keep track of all the 256MB segments in the address space.
While I used the "concepts" of hugetlbfs, I mostly re-implemented
everything in a more generic way and "ported" hugetlbfs to it.
Slices can have an associated page size, which is encoded in the mmu
context and used by the SLB miss handler to set the segment sizes. The
hash code currently doesn't care, it has a specific check for hugepages,
though I might add a mechanism to provide per-slice hash mapping
functions in the future.
The slice code provide a pair of "generic" get_unmapped_area() (bottomup
and topdown) functions that should work with any slice size. There is
some trickiness here so I would appreciate people to have a look at the
implementation of these and let me know if I got something wrong.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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The code for demoting segments to 4K had some issues, like for example,
when using _PAGE_4K_PFN flag, the first CPU to hit it would do the
demotion, but other CPUs hitting the same page wouldn't properly flush
their SLBs if mmu_ci_restriction isn't set. There are also potential
issues with hash_preload not handling _PAGE_4K_PFN. All of these are
non issues on current hardware but might bite us in the future.
This patch thus fixes it by:
- Taking the test comparing the mm and current CPU context page
sizes to decide to flush SLBs out of the mmu_ci_restrictions test
since that can also be triggered by _PAGE_4K_PFN pages
- Due to the above being done all the time, demote_segment_4k
doesn't need update the context and flush the SLB
- demote_segment_4k can be static and doesn't need an EXPORT_SYMBOL
- Making hash_preload ignore anything that has either _PAGE_4K_PFN
or _PAGE_NO_CACHE set, thus avoiding duplication of the complicated
logic in hash_page() (and possibly making hash_preload a little bit
faster for the normal case).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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This makes the new iSeries virtual console drivers (nvc_iseries) the
default and prevents viocons being built unless explicitly selected.
Also it makes no sense to have the console as a module.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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