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* [S390] kprobes: use probe_kernel_writeHeiko Carstens2009-06-121-29/+2
| | | | | | | Use proble_kernel_write() to patch the kernel. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] maccess: arch specific probe_kernel_write() implementationHeiko Carstens2009-06-122-1/+62
| | | | | | | | | | Add an s390 specific probe_kernel_write() function which allows to write to the kernel text segment even if write protection is enabled. This is implemented using the lra (load real address) and stura (store using real address) instructions. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] profile_tick called twiceMartin Schwidefsky2009-06-121-7/+0
| | | | | | | | | profile_tick is called twice for every clock comparator interrupt. The generic clock event code does it in tick_sched_timer and the s390 backend code in clock_comparator_work. That is one too many, remove the one in the arch backend code. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] vmalloc: add vmalloc kernel parameter supportHeiko Carstens2009-06-122-5/+18
| | | | | | | | | | | | | With the kernel parameter 'vmalloc=<size>' the size of the vmalloc area can be specified. This can be used to increase or decrease the size of the area. Works in the same way as on some other architectures. This can be useful for features which make excessive use of vmalloc and wouldn't work otherwise. The default sizes remain unchanged: 96MB for 31 bit kernels and 1GB for 64 bit kernels. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] uaccess: use might_fault() instead of might_sleep()Heiko Carstens2009-06-122-9/+9
| | | | | | | Adds more checking in case lockdep is turned on. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] secure computing arch backendHeiko Carstens2009-06-126-9/+51
| | | | | | | Enable secure computing on s390 as well. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] implement is_compat_taskHeiko Carstens2009-06-127-19/+36
| | | | | | | Implement is_compat_task and use it all over the place. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] add mini sclp driverHeiko Carstens2009-06-123-5/+342
| | | | | | | | | | | | This adds a mini sclp device driver for very early use. The primary and probably only use will be to emit a message to the console if the cpu doesn't provide the minimum required capabilities to run the kernel. After printing the message a disabled wait will be loaded and the machine stops operating. Printing the message is also part of this patch. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] use facility list for cpu type safety checkMartin Schwidefsky2009-06-122-15/+35
| | | | Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] implement interrupt-enabling rwlocksHeiko Carstens2009-06-122-3/+56
| | | | | | | | arch backend for f5f7eac41db827a47b2163330eecd7bb55ae9f12 "Allow rwlocks to re-enable interrupts". Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] merge cpu.h into cputime.hMartin Schwidefsky2009-06-126-36/+23
| | | | | | | All definition in cpu.h have to do with cputime accounting. Move them to cputime.h and remove the header file. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* [S390] vdso: kernel parameter syntaxMartin Schwidefsky2009-06-121-2/+13
| | | | | | | | | The syntax of the vdso kernel parameter is documented as vdso=[on|off]. The implementation uses vdso=[0|1], an invalid parameter string disables the vdso support. Fix the mismatch by adding vdso=[on|off] as additional parameter syntax. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* Merge branch 'for-linus' of ↵Linus Torvalds2009-06-111-3/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6: (87 commits) nilfs2: get rid of bd_mount_sem use from nilfs nilfs2: correct exclusion control in nilfs_remount function nilfs2: simplify remaining sget() use nilfs2: get rid of sget use for checking if current mount is present nilfs2: get rid of sget use for acquiring nilfs object nilfs2: remove meaningless EBUSY case from nilfs_get_sb function remove the call to ->write_super in __sync_filesystem nilfs2: call nilfs2_write_super from nilfs2_sync_fs jffs2: call jffs2_write_super from jffs2_sync_fs ufs: add ->sync_fs sysv: add ->sync_fs hfsplus: add ->sync_fs hfs: add ->sync_fs fat: add ->sync_fs ext2: add ->sync_fs exofs: add ->sync_fs bfs: add ->sync_fs affs: add ->sync_fs sanitize ->fsync() for affs repair bfs_write_inode(), switch bfs to simple_fsync() ...
| * Push BKL into do_mount()Al Viro2009-06-111-3/+0
| | | | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* | Merge branch 'for-linus' of ↵Linus Torvalds2009-06-1123-187/+178
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: m68knommu: remove unecessary include of thread_info.h in entry.S m68knommu: enumerate INIT_THREAD fields properly headers_check fix: m68k, swab.h arch/m68knommu: Convert #ifdef DEBUG printk(KERN_DEBUG to pr_debug( m68knommu: remove obsolete reset code m68knommu: move CPU reset code for the 5272 ColdFire into its platform code m68knommu: move CPU reset code for the 528x ColdFire into its platform code m68knommu: move CPU reset code for the 527x ColdFire into its platform code m68knommu: move CPU reset code for the 523x ColdFire into its platform code m68knommu: move CPU reset code for the 520x ColdFire into its platform code m68knommu: add CPU reset code for the 532x ColdFire m68knommu: add CPU reset code for the 5249 ColdFire m68knommu: add CPU reset code for the 5206e ColdFire m68knommu: add CPU reset code for the 5206 ColdFire m68knommu: add CPU reset code for the 5407 ColdFire m68knommu: add CPU reset code for the 5307 ColdFire m68knommu: merge system reset for code ColdFire 523x family m68knommu: fix system reset for ColdFire 527x family
| * | m68knommu: remove unecessary include of thread_info.h in entry.SGreg Ungerer2009-06-111-1/+0
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: enumerate INIT_THREAD fields properlyGreg Ungerer2009-06-111-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use proper field value setting init INIT_THREAD macro. Fixes this: arch/m68knommu/kernel/init_task.c:27: warning: excess elements in array initializer arch/m68knommu/kernel/init_task.c:27: warning: (near initialization for ‘init_task.thread.fpstate’) Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | headers_check fix: m68k, swab.hJaswinder Singh Rajput2009-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fix the following 'make headers_check' warnings: usr/include/asm-m68k/swab.h:4: include of <linux/types.h> is preferred over <asm/types.h> usr/include/asm-m68k/swab.h:10: found __[us]{8,16,32,64} type without #include <linux/types.h> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | arch/m68knommu: Convert #ifdef DEBUG printk(KERN_DEBUG to pr_debug(Joe Perches2009-06-112-12/+8
| | | | | | | | | | | | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: remove obsolete reset codeGreg Ungerer2009-06-112-105/+0
| | | | | | | | | | | | | | | | | | | | | All ColdFire and non-MMU 68k code has custom reset routines. Remove the obsolete and now un-used reset macros. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: move CPU reset code for the 5272 ColdFire into its platform codeGreg Ungerer2009-06-111-4/+14
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: move CPU reset code for the 528x ColdFire into its platform codeGreg Ungerer2009-06-112-4/+17
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: move CPU reset code for the 527x ColdFire into its platform codeGreg Ungerer2009-06-112-6/+18
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: move CPU reset code for the 523x ColdFire into its platform codeGreg Ungerer2009-06-112-6/+17
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: move CPU reset code for the 520x ColdFire into its platform codeGreg Ungerer2009-06-112-6/+18
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: add CPU reset code for the 532x ColdFireGreg Ungerer2009-06-112-3/+21
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: add CPU reset code for the 5249 ColdFireGreg Ungerer2009-06-111-6/+12
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: add CPU reset code for the 5206e ColdFireGreg Ungerer2009-06-111-6/+12
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: add CPU reset code for the 5206 ColdFireGreg Ungerer2009-06-111-6/+12
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: add CPU reset code for the 5407 ColdFireGreg Ungerer2009-06-111-4/+12
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: add CPU reset code for the 5307 ColdFireGreg Ungerer2009-06-111-4/+12
| | | | | | | | | | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: merge system reset for code ColdFire 523x familyGreg Ungerer2009-06-111-11/+2
| | | | | | | | | | | | | | | | | | | | | | | | The sofwtare reset control code for the 523x ColdFire family uses the same Reset unit hardware as the 527x and 528x ColdFire parts. So they should all use the same code. Merge them. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: fix system reset for ColdFire 527x familyGreg Ungerer2009-06-111-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | The sofwtare reset control for the 527x ColdFire family is based on the same Reset Control Unit as the 528x ColdFire family. So use the same reset code for both. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* | | x86: use zalloc_cpumask_var in arch_early_irq_initYinghai Lu2009-06-111-2/+2
| | | | | | | | | | | | | | | | | | | | | So we make sure MAXSMP gets a cleared cpumask Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | perfcounters: remove powerpc definitions of perf_counter_do_pendingStephen Rothwell2009-06-112-3/+1
| |/ |/| | | | | | | | | | | | | | | | | Commit 925d519ab82b6dd7aca9420d809ee83819c08db2 ("perf_counter: unify and fix delayed counter wakeup") added global definitions. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Paul Mackerras <paulus@samba.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'perfcounters-for-linus' of ↵Linus Torvalds2009-06-1146-72/+6814
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perfcounters-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (574 commits) perf_counter: Turn off by default perf_counter: Add counter->id to the throttle event perf_counter: Better align code perf_counter: Rename L2 to LL cache perf_counter: Standardize event names perf_counter: Rename enums perf_counter tools: Clean up u64 usage perf_counter: Rename perf_counter_limit sysctl perf_counter: More paranoia settings perf_counter: powerpc: Implement generalized cache events for POWER processors perf_counters: powerpc: Add support for POWER7 processors perf_counter: Accurate period data perf_counter: Introduce struct for sample data perf_counter tools: Normalize data using per sample period data perf_counter: Annotate exit ctx recursion perf_counter tools: Propagate signals properly perf_counter tools: Small frequency related fixes perf_counter: More aggressive frequency adjustment perf_counter/x86: Fix the model number of Intel Core2 processors perf_counter, x86: Correct some event and umask values for Intel processors ...
| * \ Merge branch 'linus' into perfcounters/coreIngo Molnar2009-06-11217-4756/+5923
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/x86/kernel/irqinit.c arch/x86/kernel/irqinit_64.c arch/x86/kernel/traps.c arch/x86/mm/fault.c include/linux/sched.h kernel/exit.c
| * | | perf_counter: Rename L2 to LL cachePeter Zijlstra2009-06-117-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The top (fastest) and last level (biggest) caches are the most interesting ones, performance wise. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> [ Fixed the Nehalem LL table to LLC Reference/Miss events ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter: Standardize event namesPeter Zijlstra2009-06-118-52/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pure renames only, to PERF_COUNT_HW_* and PERF_COUNT_SW_*. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter: powerpc: Implement generalized cache events for POWER processorsPaul Mackerras2009-06-118-6/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds tables of event codes for the generalized cache events for all the currently supported powerpc processors: POWER{4,5,5+,6,7} and PPC970*, plus powerpc-specific code to use these tables when a generalized cache event is requested. Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <18992.36430.933526.742969@drongo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counters: powerpc: Add support for POWER7 processorsPaul Mackerras2009-06-113-1/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the back-end for the PMU on POWER7 processors. POWER7 has 4 fully-programmable counters and two fixed-function counters (which do respect the freeze conditions, can generate interrupts, and are writable, unlike PMC5/6 on POWER5+/6). Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <18992.36329.189378.17992@drongo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter: Accurate period dataPeter Zijlstra2009-06-112-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently log hw.sample_period for PERF_SAMPLE_PERIOD, however this is incorrect. When we adjust the period, it will only take effect the next cycle but report it for the current cycle. So when we adjust the period for every cycle, we're always wrong. Solve this by keeping track of the last_period. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter: Introduce struct for sample dataPeter Zijlstra2009-06-112-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For easy extension of the sample data, put it in a structure. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter: More aggressive frequency adjustmentPeter Zijlstra2009-06-101-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also employ the overflow handler to adjust the frequency, this results in a stable frequency in about 40~50 samples, instead of that many ticks. This also means we can start sampling at a sample period of 1 without running head-first into the throttle. It relies on sched_clock() to accurately measure the time difference between the overflow NMIs. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter/x86: Fix the model number of Intel Core2 processorsYong Wang2009-06-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the model number of Intel Core2 processors according to the documentation: Intel Processor Identification with the CPUID Instruction: http://www.intel.com/support/processors/sb/cs-009861.htm Signed-off-by: Yong Wang <yong.y.wang@intel.com> Also-Reported-by: Arnd Bergmann <arnd@arndb.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <20090610090612.GA26580@ywang-moblin2.bj.intel.com> [ Added two more model numbers suggested by Arnd Bergmann ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter, x86: Correct some event and umask values for Intel processorsYong Wang2009-06-091-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct some event and UMASK values according to Intel SDM, in the Nehalem and Atom tables. Signed-off-by: Yong Wang <yong.y.wang@intel.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <20090609131553.GA12489@ywang-moblin2.bj.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter, x86: Clean up hw_cache_event ids copiesThomas Gleixner2009-06-081-6/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter, x86: Implement generalized cache event types, add AMD supportThomas Gleixner2009-06-081-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fill in amd_hw_cache_event_id[] with the AMD CPU specific events, for family 0x0f, 0x10 and 0x11. There's apparently no distinction between load and store events, so we only fill in the load events. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter: Clean up x86 boot messagesIngo Molnar2009-06-081-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Standardize and tidy up all the messages we print during perfcounter initialization. Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf_counter, x86: Implement generalized cache event types, add Atom supportThomas Gleixner2009-06-081-1/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fill in core2_hw_cache_event_id[] with the Atom model specific events. The events can be used in all the tools via the -e (--event) parameter, for example "-e l1-misses" or -"-e l2-accesses" or "-e l2-write-misses". ( Note: these are straight from the Intel manuals - not tested yet.) Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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