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* Merge branch 'x86/urgent' into x86/apicIngo Molnar2009-02-053-5/+20
|\ | | | | | | | | | | | | | | | | | | Conflicts: arch/x86/mach-default/setup.c Semantic merge: arch/x86/kernel/irqinit_32.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * MIPS: Read watch registers with interrupts disabled.David Daney2009-01-302-2/+12
| | | | | | | | | | | | | | | | | | | | If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: R2: Fix broken installation of cache error handler.Ralf Baechle2009-01-301-2/+6
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: SMTC: Fix build after recent creditial changes.Ralf Baechle2009-01-301-1/+2
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'x86/mm' into core/percpuIngo Molnar2009-01-211-1/+1
|\| | | | | | | | | Conflicts: arch/x86/mm/fault.c
| * [CVE-2009-0029] Rename old_readdir to sys_old_readdirHeiko Carstens2009-01-141-1/+1
| | | | | | | | | | | | This way it matches the generic system call name convention. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
| |
| \
*-. \ Merge branches 'cpus4096', 'x86/cleanups' and 'x86/urgent' into x86/percpuIngo Molnar2009-01-152-3/+5
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| * | irq: update all arches for new irq_desc, fixMike Travis2009-01-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: fix build errors Since the SPARSE IRQS changes redefined how the kstat irqs are organized, arch's must use the new accessor function: kstat_incr_irqs_this_cpu(irq, DESC); If CONFIG_SPARSE_IRQS is set, then DESC is a pointer to the irq_desc which has a pointer to the kstat_irqs. If not, then the .irqs field of struct kernel_stat is used instead. Signed-off-by: Mike Travis <travis@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | irq: update all arches for new irq_descMike Travis2009-01-122-2/+2
| |/ | | | | | | | | | | | | | | | | Impact: cleanup, update to new cpumask API Irq_desc.affinity and irq_desc.pending_mask are now cpumask_var_t's so access to them should be using the new cpumask API. Signed-off-by: Mike Travis <travis@sgi.com>
* | MIPS: Alchemy: RTC counter clocksource / clockevent support.Manuel Lauss2009-01-111-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent device. As a nice side effect, this also enables use of the 'wait' instruction for runtime idle power savings. If the counters aren't enabled/working properly, fall back on the cp0 counter clock code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: make cp0 counter clocksource/event usable as fallback.Manuel Lauss2009-01-113-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current mips clock build infrastructure lets a system only use either the MIPS cp0 counter or a SoC specific timer as a clocksource / clockevent device. This patch renames the core cp0 counter clocksource / clockevent functions from mips_* to r4k_* and updates the wrappers in asm-mips/time.h to call these renamed functions instead. Chips which can detect whether it is safe to use a chip-specific timer can now fall back on the cp0 counter if necessary and possible (e.g. Alchemy with a follow-on patch). Existing behaviour is not changed in any way. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Print irq handler descriptionManuel Lauss2009-01-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the name set by set_irq_chip_and_handler_name() to the output of /proc/interrupts, like so: db1200 ~ # cat /proc/interrupts CPU0 8: 52 Alchemy-IC0-hilevel serial 10: 171 Alchemy-IC0-hilevel au1xxx-mmc 11: 47 Alchemy-IC0-hilevel Au1xxx dbdma 18: 1 Alchemy-IC0-hilevel au1550-spi 29: 1250997 Alchemy-IC0-riseedge timer 37: 211 Alchemy-IC0-hilevel ehci_hcd:usb1, ohci_hcd:usb2 38: 0 Alchemy-IC0-hilevel lcd 72: 2623 DB1200 CPLD-level ide0 73: 257 DB1200 CPLD-level eth0 84: 1 DB1200 CPLD-level sd_insert 85: 0 DB1200 CPLD-level sd_eject ERR: 0 Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Compute branch returns for Cavium OCTEON specific branch instructions.David Daney2009-01-111-0/+33
| | | | | | | | | | | | | | | | | | For Cavium OCTEON, compute the return epc value for OCTEON specific branch instructions. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Add Cavium OCTEON specific registers to ptrace.h and asm-offsets.cDavid Daney2009-01-111-0/+31
| | | | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Hook up Cavium OCTEON in arch/mips.David Daney2009-01-111-0/+1
| | | | | | | | | | | | | | | | | | | | Take all the OCTEON specific files that were added, and hook them into the build system for the arch/mips. For versions of GCC that lack OCTEON support, override gas target architecture. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Add Cavium OCTEON processor constants and CPU probe.David Daney2009-01-111-0/+25
| | | | | | | | | | | | | | | | | | | | Add OCTEON constants to asm/cpu.h and asm/module.h. Add probe function for Cavium OCTEON CPUs and hook it up. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Override assembler target architecture for octeon.David Daney2009-01-111-0/+4
| | | | | | | | | | | | | | | | | | Gas from binutils 2.19 fails to compile some cop1 instructions with -march=octeon. Since the cop1 instructions are present in mips1, use that arch instead. This will be fixed in binutils 2.20. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.David Daney2009-01-111-0/+21
| | | | | | | | | | | | | | | | | | If on Cavium, be aware of cop2 and hwrena during do_cpu(). Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.David Daney2009-01-111-0/+506
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are the rest of the new files needed to add OCTEON processor support to the Linux kernel. Other than Makefile and Kconfig which should be obvious, we have: csrc-octeon.c -- Clock source driver for OCTEON. dma-octeon.c -- Helper functions for mapping DMA memory. flash_setup.c -- Register on-board flash with the MTD subsystem. octeon-irq.c -- OCTEON interrupt controller managment. octeon-memcpy.S -- Optimized memcpy() implementation. serial.c -- Register 8250 platform driver and early console. setup.c -- Early architecture initialization. smp.c -- OCTEON SMP support. octeon_switch.S -- Scheduler context switch for OCTEON. c-octeon.c -- OCTEON cache controller support. cex-oct.S -- OCTEON cache exception handler. asm/mach-cavium-octeon/*.h -- Architecture include files. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/cavium-octeon/Kconfig create mode 100644 arch/mips/cavium-octeon/Makefile create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c create mode 100644 arch/mips/cavium-octeon/dma-octeon.c create mode 100644 arch/mips/cavium-octeon/flash_setup.c create mode 100644 arch/mips/cavium-octeon/octeon-irq.c create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S create mode 100644 arch/mips/cavium-octeon/serial.c create mode 100644 arch/mips/cavium-octeon/setup.c create mode 100644 arch/mips/cavium-octeon/smp.c create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h create mode 100644 arch/mips/include/asm/octeon/octeon.h create mode 100644 arch/mips/kernel/octeon_switch.S create mode 100644 arch/mips/mm/c-octeon.c create mode 100644 arch/mips/mm/cex-oct.S
* | MIPS: 64-bit: Use generic 32-bit ptrace compat code.Anirban Sinha2009-01-111-63/+1
|/ | | | | Signed-off-by: Anirban Sinha <asinha@zeugmasystems.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'proc-linus' of ↵Linus Torvalds2009-01-071-6/+18
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/adobriyan/proc * 'proc-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/adobriyan/proc: proc: remove write-only variable in proc_pident_lookup() proc: fix sparse warning proc: add /proc/*/stack proc: remove '##' usage proc: remove useless WARN_ONs proc: stop using BKL
| * proc: add /proc/*/stackKen Chen2009-01-051-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | /proc/*/stack adds the ability to query a task's stack trace. It is more useful than /proc/*/wchan as it provides full stack trace instead of single depth. Example output: $ cat /proc/self/stack [<c010a271>] save_stack_trace_tsk+0x17/0x35 [<c01827b4>] proc_pid_stack+0x4a/0x76 [<c018312d>] proc_single_show+0x4a/0x5e [<c016bdec>] seq_read+0xf3/0x29f [<c015a004>] vfs_read+0x6d/0x91 [<c015a0c1>] sys_read+0x3b/0x60 [<c0102eda>] syscall_call+0x7/0xb [<ffffffff>] 0xffffffff [add save_stack_trace_tsk() on mips, ACK Ralf --adobriyan] Signed-off-by: Ken Chen <kenchen@google.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
* | mips: struct device - replace bus_id with dev_name(), dev_set_name()Kay Sievers2009-01-061-1/+1
|/ | | | | | Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* Merge branch 'cpus4096-for-linus-2' of ↵Linus Torvalds2009-01-0213-26/+21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'cpus4096-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (66 commits) x86: export vector_used_by_percpu_irq x86: use logical apicid in x2apic_cluster's x2apic_cpu_mask_to_apicid_and() sched: nominate preferred wakeup cpu, fix x86: fix lguest used_vectors breakage, -v2 x86: fix warning in arch/x86/kernel/io_apic.c sched: fix warning in kernel/sched.c sched: move test_sd_parent() to an SMP section of sched.h sched: add SD_BALANCE_NEWIDLE at MC and CPU level for sched_mc>0 sched: activate active load balancing in new idle cpus sched: bias task wakeups to preferred semi-idle packages sched: nominate preferred wakeup cpu sched: favour lower logical cpu number for sched_mc balance sched: framework for sched_mc/smt_power_savings=N sched: convert BALANCE_FOR_xx_POWER to inline functions x86: use possible_cpus=NUM to extend the possible cpus allowed x86: fix cpu_mask_to_apicid_and to include cpu_online_mask x86: update io_apic.c to the new cpumask code x86: Introduce topology_core_cpumask()/topology_thread_cpumask() x86: xen: use smp_call_function_many() x86: use work_on_cpu in x86/kernel/cpu/mcheck/mce_amd_64.c ... Fixed up trivial conflict in kernel/time/tick-sched.c manually
| * cpumask: convert struct clock_event_device to cpumask pointers.Rusty Russell2008-12-138-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Impact: change calling convention of existing clock_event APIs struct clock_event_timer's cpumask field gets changed to take pointer, as does the ->broadcast function. Another single-patch change. For safety, we BUG_ON() in clockevents_register_device() if it's not set. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Cc: Ingo Molnar <mingo@elte.hu>
| * cpumask: make irq_set_affinity() take a const struct cpumaskRusty Russell2008-12-133-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: change existing irq_chip API Not much point with gentle transition here: the struct irq_chip's setaffinity method signature needs to change. Fortunately, not widely used code, but hits a few architectures. Note: In irq_select_affinity() I save a temporary in by mangling irq_desc[irq].affinity directly. Ingo, does this break anything? (Folded in fix from KOSAKI Motohiro) Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Mike Travis <travis@sgi.com> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Acked-by: Ingo Molnar <mingo@redhat.com> Cc: ralf@linux-mips.org Cc: grundler@parisc-linux.org Cc: jeremy@xensource.com Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
| * cpumask: change cpumask_scnprintf, cpumask_parse_user, cpulist_parse, and ↵Rusty Russell2008-12-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpulist_scnprintf to take pointers. Impact: change calling convention of existing cpumask APIs Most cpumask functions started with cpus_: these have been replaced by cpumask_ ones which take struct cpumask pointers as expected. These four functions don't have good replacement names; fortunately they're rarely used, so we just change them over. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Mike Travis <travis@sgi.com> Acked-by: Ingo Molnar <mingo@elte.hu> Cc: paulus@samba.org Cc: mingo@redhat.com Cc: tony.luck@intel.com Cc: ralf@linux-mips.org Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: cl@linux-foundation.org Cc: srostedt@redhat.com
| * cpumask: centralize cpu_online_map and cpu_possible_mapRusty Russell2008-12-134-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: cleanup Each SMP arch defines these themselves. Move them to a central location. Twists: 1) Some archs (m32, parisc, s390) set possible_map to all 1, so we add a CONFIG_INIT_ALL_POSSIBLE for this rather than break them. 2) mips and sparc32 '#define cpu_possible_map phys_cpu_present_map'. Those archs simply have phys_cpu_present_map replaced everywhere. 3) Alpha defined cpu_possible_map to cpu_present_map; this is tricky so I just manipulate them both in sync. 4) IA64, cris and m32r have gratuitous 'extern cpumask_t cpu_possible_map' declarations. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Tested-by: Tony Luck <tony.luck@intel.com> Acked-by: Ingo Molnar <mingo@elte.hu> Cc: Mike Travis <travis@sgi.com> Cc: ink@jurassic.park.msu.ru Cc: rmk@arm.linux.org.uk Cc: starvik@axis.com Cc: tony.luck@intel.com Cc: takata@linux-m32r.org Cc: ralf@linux-mips.org Cc: grundler@parisc-linux.org Cc: paulus@samba.org Cc: schwidefsky@de.ibm.com Cc: lethal@linux-sh.org Cc: wli@holomorphy.com Cc: davem@davemloft.net Cc: jdike@addtoit.com Cc: mingo@redhat.com
* | take init_fs to saner placeAl Viro2008-12-311-1/+0
| | | | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* | Merge branch 'next' into for-linusJames Morris2008-12-253-6/+7
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| * Merge branch 'master' into nextJames Morris2008-12-041-1/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: fs/nfsd/nfs4recover.c Manually fixed above to use new creds API functions, e.g. nfs4_save_creds(). Signed-off-by: James Morris <jmorris@namei.org>
| * | CRED: Use creds in file structsDavid Howells2008-11-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Attach creds to file structs and discard f_uid/f_gid. file_operations::open() methods (such as hppfs_open()) should use file->f_cred rather than current_cred(). At the moment file->f_cred will be current_cred() at this point. Signed-off-by: David Howells <dhowells@redhat.com> Reviewed-by: James Morris <jmorris@namei.org> Signed-off-by: James Morris <jmorris@namei.org>
| * | CRED: Separate task security context from task_structDavid Howells2008-11-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Separate the task security context from task_struct. At this point, the security data is temporarily embedded in the task_struct with two pointers pointing to it. Note that the Alpha arch is altered as it refers to (E)UID and (E)GID in entry.S via asm-offsets. With comment fixes Signed-off-by: Marc Dionne <marc.c.dionne@gmail.com> Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: James Morris <jmorris@namei.org> Acked-by: Serge Hallyn <serue@us.ibm.com> Signed-off-by: James Morris <jmorris@namei.org>
| * | CRED: Wrap task credential accesses in the MIPS archDavid Howells2008-11-141-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wrap access to task credentials so that they can be separated more easily from the task_struct during the introduction of COW creds. Change most current->(|e|s|fs)[ug]id to current_(|e|s|fs)[ug]id(). Change some task->e?[ug]id to task_e?[ug]id(). In some places it makes more sense to use RCU directly rather than a convenient wrapper; these will be addressed by later patches. Signed-off-by: David Howells <dhowells@redhat.com> Reviewed-by: James Morris <jmorris@namei.org> Acked-by: Serge Hallyn <serue@us.ibm.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: James Morris <jmorris@namei.org>
* | | MIPS: Fix incorrect use of loose in vpe.cNick Andrew2008-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | | It should be 'lose', not 'loose'. Signed-off-by: Nick Andrew <nick@nick-andrew.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Return ENOSYS from sys32_syscall on 64bit kernels like elsewhere.David Daney2008-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | When the o32 errno was changed to ENOSYS, we forgot to update the code for 64bit kernels. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: 64-bit: vmsplice needs to use the compat wrapper for o32 and N32.Ralf Baechle2008-12-042-2/+2
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: o32: Fix number of arguments to splice(2).Ralf Baechle2008-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The syscall code was assuming splice only takes 4 arguments so no stack arguments were being copied from the userspace stack to the kernel stack. As the result splice was likely to fail with EINVAL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Fix potential DOS by untrusted user app.Vlad Malov2008-12-042-11/+6
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | On a 64 bit kernel if an o32 syscall was made with a syscall number less than 4000, we would read the function from outside of the bounds of the syscall table. This led to non-deterministic behavior including system crashes. While we were at it we reworked the 32 bit version as well to use fewer instructions. Both 32 and 64 bit versions are use the same code now. Signed-off-by: Vlad Malov <Vlad.Malov@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: csrc-r4k: Fix spelling mistake.Ralf Baechle2008-11-201-1/+1
|/ | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Sort out CPU type to name translation.Ralf Baechle2008-10-301-127/+98
| | | | | | | | | | | | | As noticed by David Daney <ddaney@caviumnetworks.com>, the old long switch statement did not comply with the Linux C coding style. It was also yet another place of code to be changed when adding a new processor type leading to annoying bugs for example in /proc/cpuinfo. Fixed by moving the setting of the CPU type string into the core of the probing code and a few BUG_ON() test to ensure the CPU probing code indeed did its job and removing multiple now redundant tests. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Probe for watch registers on cores of all vendors, not just MTI.Ralf Baechle2008-10-301-10/+12
| | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: David Daney <ddaney@caviumnetworks.com>
* MIPS: Switch FPU emulator trap to BREAK instruction.Ralf Baechle2008-10-302-12/+16
| | | | | | | | | | | | Arguably using the address error handler has always been ugly. But with processors that handle unaligned loads and stores in hardware the current mechanism ceases to work so switch it to a BREAK instruction and allocate break code 514 to the FPU emulator. Yoichi Yuasa provided a build fix for CONFIG_BUG=n. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* MIPS: SMP: Do not initialize __cpu_number_map/__cpu_logical_map for CPU 0.Ralf Baechle2008-10-301-6/+0
| | | | | | | | | A system isn't necessarily booted on physical processor 0 as this code assumes. Also the array happens to be allocated in .bss so it's zero initialized anyway. Systems which need to override this can do so in their mp_ops->smp_setup() method. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Consider value of c0_ebase when computing value of exception base.David Daney2008-10-301-4/+9
| | | | | | | | | | | | It just so happens to be zero on all currently supported systems so this hasn't bitten yet ... [Ralf: Original patch from Cavium; handling of set_uncached_handler() and de-ifdef'ed trap_init() implementation by me.] Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processorsShinya Kuribayashi2008-10-271-0/+1
| | | | | | | | | | | | We already have sufficient infrastructure to support VR5500 and VR5500A series processors. Here's a Makefile support to make it selectable by ports, and enable it for NEC EMMA2RH Markeins board. This patch also fixes a confused target help, and adds 1Gb PageMask bits supported by VR5500 and its variants. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Set ENOSYS to errno on illegal system call number for syscall(2)Atsushi Nemoto2008-10-271-1/+1
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Set positive error number to errno on illegal_syscallAtsushi Nemoto2008-10-272-2/+2
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SMP: Don't reenable interrupts in stop_this_cpu; use WAIT instruction.Ralf Baechle2008-10-271-2/+4
| | | | | | Noticed by Anirban Sinha <ASinha@zeugmasystems.com>; patch by me. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix debugfs_create_*'s error checking method for mips/kernel/Zhaolei2008-10-272-6/+6
| | | | | | | | | debugfs_create_*() returns NULL on error. Make its callers return -ENODEV on error. Signed-off-by: Zhao Lei <zhaolei@cn.fujitsu.com> Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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