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* [ARM] 3734/1: Fix the unused variable warning in __iounmap()Catalin Marinas2006-07-291-0/+2
| | | | | | | | | | Patch from Catalin Marinas This patch adds #ifdef around some variables in the arch/arm/mm/ioremap.c file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3737/1: Export ARM copy/clear_user_page symbolsGeorge G. Davis2006-07-291-0/+8
| | | | | | | | | | | | | | | | | Patch from George G. Davis As reported by various folks on the ARM Linux kernel mailing list, the video-buf.ko driver has undefined references on all ARM machines which use it as observed during `make modules`: Warning: "v4wb_clear_user_page" [drivers/media/video/video-buf.ko] undefined! Similar warnings exist for all ARM machines which use this driver. So this change adds the missing EXPORT_SYMBOLs to allow using this driver as a module. Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3736/1: xscale: don't mis-report 80219 as an iop32xLennert Buytenhek2006-07-291-1/+29
| | | | | | | | | | | | | | | Patch from Lennert Buytenhek The IOP 80219 xscale CPU is a stripped down version of the IOP32x. But the fact that the 80219 and IOP32x are very similar doesn't mean that they need to share a cpu table entry. It's also somewhat confusing for the end user to see the 80219 reported as an IOP32x, so this patch splits the IOP32x cpu table entry to make a separate entry for the 80219. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix warning in consistent.cRussell King2006-07-031-2/+1
| | | | | | | | No need for 'cr' to be a local variable, which is unused in the SMP case, and only used once in the UP case. Just call get_cr() directly. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix bad asm instruction in proc-arm925.SRussell King2006-07-031-1/+2
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] More missing proc-macros.S includesRussell King2006-07-034-0/+8
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3708/2: fix SMP build after section ioremap changesLennert Buytenhek2006-07-031-0/+2
| | | | | | | | | | Patch from Lennert Buytenhek Commit ff0daca525dde796382b9ccd563f169df2571211 broke the SMP build, this patch fixes it up again. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Fixup missing includes in arch/arm/mm/proc-<cputype>.SThomas Gleixner2006-07-023-0/+6
| | | | | | | | For several proc-<cputype>.S files the include of proc-macros.S is missing. Make it compile and work again. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2006-07-0219-264/+480
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
| * [ARM] 3541/2: workaround for PXA27x erratum E7Nicolas Pitre2006-07-011-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Nicolas Pitre According to the Intel PXA27x Processor Family Specification Update document (doc.nr. 280071-009) erratum E7, some care must be taken to locate the disabling and re-enabling of the MMU to the beginning of a cache line to avoid problems in some circumstances. Credits to Simon Vogl <simon.vogl@researchstudios.at> for bringing this up. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * Merge nommu branchRussell King2006-07-0115-125/+101
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| | * [ARM] nommu: provide a way for correct control register value selectionRussell King2006-06-2915-125/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 3705/1: add supersection support to ioremap()Lennert Buytenhek2006-07-011-3/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek Analogous to the previous patch that allows ioremap() to use section mappings, this patch allows ioremap() to use supersection mappings. Original patch by Deepak Saxena. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Add section support to ioremapRussell King2006-06-291-4/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow section mappings to be setup using ioremap() and torn down with iounmap(). This requires additional support in the MM context switch to ensure that mappings are properly synchronised when mapped in. Based an original implementation by Deepak Saxena, reworked and ARMv6 support added by rmk. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Set bit 4 on section mappings correctly depending on CPURussell King2006-06-2916-17/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 3675/2: Preparing for AT91SAM926 supportAndrew Victor2006-06-291-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Andrew Victor This prepares the way for adding support for the new Atmel AT91SAM926x processors. Major changes: - Rename time.c to at91rm9200_time.c - Rename common.c to at91rm9200.c - Introduce ARCH_AT91, of which ARCH_AT91RM9200, ARCH_AT91SAM9260 and ARCH_AT91SAM9261 are dependent. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Remove yucky ifdefs to print "id(wb)BRR" suffix on CPU nameRussell King2006-06-297-115/+7
| | | | | | | | | | | | | | | | | | The "id(wb)BRR" suffix reports which CPU debugging options were (or were not) selected at kernel build time. Rather than have every proc-*.S file implement this, report the control register value, from which this information can be deduced. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivialLinus Torvalds2006-06-3014-14/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: Remove obsolete #include <linux/config.h> remove obsolete swsusp_encrypt arch/arm26/Kconfig typos Documentation/IPMI typos Kconfig: Typos in net/sched/Kconfig v9fs: do not include linux/version.h Documentation/DocBook/mtdnand.tmpl: typo fixes typo fixes: specfic -> specific typo fixes in Documentation/networking/pktgen.txt typo fixes: occuring -> occurring typo fixes: infomation -> information typo fixes: disadvantadge -> disadvantage typo fixes: aquire -> acquire typo fixes: mecanism -> mechanism typo fixes: bandwith -> bandwidth fix a typo in the RTC_CLASS help text smb is no longer maintained Manually merged trivial conflict in arch/um/kernel/vmlinux.lds.S
| * | Remove obsolete #include <linux/config.h>Jörn Engel2006-06-3014-14/+0
| |/ | | | | | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* / [PATCH] zoned vm counters: conversion of nr_pagetables to per zone counterChristoph Lameter2006-06-301-1/+1
|/ | | | | | | | | Conversion of nr_page_table_pages to a per zone counter [akpm@osdl.org: bugfix] Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [ARM] nommu: Initial uCLinux support for MMU-based CPUsHyok S. Choi2006-06-2813-0/+129
| | | | | | | | | | In noMMU mode, various of functions which are defined in mm/proc-*.S is not valid or needed to be avoided. i.g. switch_mm is not needed, just returns and this makes the I & D caches are valid which shows great improvement of performance including task switching and IPC. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: export flush_dcache_page()Hyok S. Choi2006-06-281-0/+1
| | | | | | | This is a trivial patch to export flush_dcache_page in mm/nommu.c. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: remove fault-armv, mmap and mm-armv files from nommu buildRussell King2006-06-281-4/+4
| | | | | | | | | | | | | | Remove fault-armv.o, mmap.o and mm-armv.o from uclinux builds - these are concerned with MMU-ful operations, and as such are redundant for uclinux. Since this also removes iotable_init() and iotable_init() is used extensively in the platform support files, just make it a no-op. Based upon a couple of patches by Hyok. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove TABLE_SIZE, and several unused function prototypesRussell King2006-06-281-2/+0
| | | | | | | TABLE_SIZE is never used in arch/arm/mm/init.c. create_memmap_holes(), memtable_init, and setup_io_desc() no longer exist in the kernel. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: Provide a simple flush_dcache_page implementationRussell King2006-06-282-2/+10
| | | | | | | | nommu doesn't require a complex flush_dcache_page implementation like the MMU-ful CPUs do, so provide a simplified version in nommu.c and omit flush.c from the build as appropriate. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: add stubs for ioremap and friendsRussell King2006-06-284-48/+92
| | | | | | | | | | | nommu doesn't have any form of remapping support, so ioremap, etc become stubs which just return the casted address, doing nothing else. Move ioport_map(), ioport_unmap(), pci_iomap(), pci_iounmap() into a separate file which is always built. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: avoid selecting TLB and CPU specific copy codeHyok S. Choi2006-06-281-29/+32
| | | | | | | | | | | Since uclinux doesn't make use of the TLB, including the TLB maintainence and CPU-optimised copypage functions does not make sense. Remove them. (This is part of one of Hyok's patches.) Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: we need the TLS register emulation for nommu modeRussell King2006-06-281-3/+3
| | | | | | | | | | | Since there can be no fixed location for the TLS value with nommu systems, we must provide TLS register emulation in order to support TLS binaries on CPUs without the thread register. Part of a patch from Hyok S. Choi, and cleaned up by rmk. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove partial non-v6 binutils compatibilityRussell King2006-06-251-32/+0
| | | | | | | | | proc-v6 contains some compatibility to be able to use the V6 "cps" instruction. However, the kernel makes use of this instruction elsewhere extensively, so there's no point keeping this compatibility anymore. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove LOADREGS macroRussell King2006-06-251-1/+1
| | | | | | | As for RETINSTR, LOADREGS is a left-over from the 26-bit days. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3636/1: S3C2412: Add selection of CPU_ARM926Ben Dooks2006-06-241-5/+5
| | | | | | | | | | Patch from Ben Dooks Select CONFIG_CPU_ARM926 when CONFIG_CPU_S3C2412 is selected. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3567/2: arm: base support for Hilscher netXSascha Hauer2006-06-191-2/+2
| | | | | | | | | | | Patch from Sascha Hauer This patch adds the base support for Hilscher's netX network processors. Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip supportVitaly Wool2006-06-181-2/+2
| | | | | | | | | | | | Patch from Vitaly Wool This patch adds basic chip support for PNX4008 ARM platform. It's basically the same as the previous one, but with the rmk's comments taken into account. Signed-off-by: Vitaly Wool <vwool@ru.mvista.com> Signed-off-by: Dmitry Pervushin <dpervushin@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Fix XScale PMD settingDeepak Saxena2006-05-311-2/+2
| | | | | | | | | | | | The ARM Architecture Reference Manual lists bit 4 of the PMD as "implementation defined" and it must be set to zero on Intel XScale CPUs or the cache does not behave properly. Found by Mike Rapoport while debugging a flash issue on the PXA255: http://marc.10east.com/?l=linux-arm-kernel&m=114845287600782&w=1 Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] ARM: explicitly disable BTB on ixp2350Deepak Saxena2006-05-301-1/+2
| | | | | | | | | | | | We don't enable the BTB on the ixp2350 as that can cause weird crashes (erratum #42.) However, some bootloaders enable the BTB, which means that we have to disable the BTB explicitly. Found thanks to Tom Rini. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [ARM] 3526/1: ioremap should use vunmap instead of vfree on ARMCatalin Marinas2006-05-161-2/+2
| | | | | | | | | | Patch from Catalin Marinas This patch modifies the __ioremap_pfn and __iounmap functions in arch/arm/mm/ioremap.c to use vunmap instead of vfree. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix SA110/SA1100 cache flushingRussell King2006-04-073-58/+30
| | | | | | | | We had two implementations for flushing the cache, which meant StrongARM caches weren't being correctly flushed. Fix this by always using the v4wb_flush_kern_cache_all method, rather than duplicating it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Move FLUSH_BASE macros to asm/arch/memory.hRussell King2006-04-071-3/+4
| | | | | | | | | FLUSH_BASE must be visible to arch/arm/mm/init.c in order for the memory region to be setup. Move these definitions from asm-arm/arch-*/hardware.h into asm-arm/arch-*/memory.h where mm stuff can see them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3439/2: xsc3: add I/O coherency supportLennert Buytenhek2006-04-023-1/+29
| | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek This patch adds support for the I/O coherent cache available on the xsc3. The approach is to provide a simple API to determine whether the chipset supports coherency by calling arch_is_coherent() and then setting the appropriate system memory PTE and PMD bits. In addition, we call this API on dma_alloc_coherent() and dma_map_single() calls. A generic version exists that will compile out all the coherency-related code that is not needed on the majority of ARM systems. Note that we do not check for coherency in the dma_alloc_writecombine() function as that still requires a special PTE setting. We also don't touch dma_mmap_coherent() as that is a special ARM-only API that is by definition only used on non-coherent system. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3425/1: xsc3: need to include pgtable-hwdef.hLennert Buytenhek2006-03-301-0/+1
| | | | | | | | | | Patch from Lennert Buytenhek Adapt xsc3 to the changes in 74945c8616a50074277e18641baaae7464006766 (xsc3 was written before but merged after the latter went in.) Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3377/2: add support for intel xsc3 coreLennert Buytenhek2006-03-285-2/+617
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX.Russell King2006-03-271-4/+12
| | | | | | | Mark page table walks with outer-cacheable attribute, and enable no-execute in page tables. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge nommu treeRussell King2006-03-2515-2/+20
|\ | | | | | | | | | | Fix merge conflict in arch/arm/mm/proc-xscale.S Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHGRussell King2006-03-211-2/+6
| | | | | | | | | | | | | | Rather than having a growing dependency line, use select to set these configuration symbols. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.hRussell King2006-03-2114-0/+14
| | | | | | | | | | | | | | Move the hardware PMD and PTE page table definitions from pgtable.h into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2006-03-2211-11/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits) [ARM] 3389/1: typo and grammar fix [ARM] 3386/1: AT91RM9200 Clock update [ARM] 3384/1: AT91RM9200: Timer [ARM] 3382/1: ixp2000: unify defconfigs [ARM] 3381/1: ixp2000: fix slowport write timing control register fields [ARM] 3380/1: ixp2000: simplify ixdp2x00_master_npu() check [ARM] 3379/1: ixp2000: use generic 8250 debug macros [ARM] 3378/1: ixp2000: fix gpio interrupt handling [ARM] Quieten spurious IRQ detection [ARM] Use kcalloc to allocate counter_config array rather than kmalloc [ARM] Oprofile: dynamically allocate counter_config [ARM] Oprofile: Convert semaphore to mutex [ARM] 3376/2: S3C2410 - update defconfig [ARM] 3375/1: S3C2440 - fix osiris machine build [ARM] 3374/1: ep93xx: gpio interrupt support [ARM] 3361/1: S3C24XX - add USB bus clock source [ARM] 3360/1: S3C2440 - add set rate methods and camera clock [ARM] 3359/1: S3C24XX - add support for clk_set_rate [ARM] Convert kmalloc+memset to kzalloc [ARM] 3373/1: move uengine loader to arch/arm/common ...
| * | [ARM] 3369/1: ep93xx: add core cirrus ep93xx supportLennert Buytenhek2006-03-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek This patch adds support for the Cirrus ep93xx series of CPUs. The ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs, IrDA, MaverickCrunch floating point coprocessor, between 24 and 64 GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster engine, graphics accelerator, IDE controller and a bunch of other stuff. This patch adds the core ep93xx support code, and support for the Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Remove unnecessary asm/hardware.h includesRussell King2006-03-2110-10/+0
| |/ | | | | | | | | | | | | | | | | asm/hardware.h is not required for the majority of processor support files, ioremap support, mm initialisation, acorn IO support, nor the debug code (which picks up its machine specific includes via debug-macros.S) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [PATCH] remove set_page_count() outside mm/Nick Piggin2006-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | set_page_count usage outside mm/ is limited to setting the refcount to 1. Remove set_page_count from outside mm/, and replace those users with init_page_count() and set_page_refcounted(). This allows more debug checking, and tighter control on how code is allowed to play around with page->_count. Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] mm: split highorder pagesNick Piggin2006-03-221-2/+2
|/ | | | | | | | | | | | | | | | | Have an explicit mm call to split higher order pages into individual pages. Should help to avoid bugs and be more explicit about the code's intention. Signed-off-by: Nick Piggin <npiggin@suse.de> Cc: Russell King <rmk@arm.linux.org.uk> Cc: David Howells <dhowells@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mundt <lethal@linux-sh.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Chris Zankel <chris@zankel.net> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
generated by cgit (git 2.34.1) at 2024-09-22 01:58:01 +0000