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* x86: remove conflicting nx6325 and nx6125 quirksRafael J. Wysocki2008-07-121-47/+0
| | | | | | | | | | | | | | We have two conflicting DMA-based quirks in there for the same set of boxes (HP nx6325 and nx6125) and one of them actually breaks my box. So remove the extra code. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: =?iso-8859-1?q?T=F6r=F6k_Edwin?= <edwintorok@gmail.com> Cc: Vegard Nossum <vegard.nossum@gmail.com> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Merge branch 'x86/generalize-visws' into x86/coreIngo Molnar2008-07-1136-909/+865
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| * x86, VisWS: fix pci_direct_conf1 dependencyIngo Molnar2008-07-101-1/+1
| | | | | | | | | | | | | | | | | | fix: arch/x86/pci/built-in.o: In function `pci_subsys_init': visws.c:(.init.text+0xfc5): undefined reference to `pci_direct_conf1' Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: build fixIngo Molnar2008-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | fix: arch/x86/kernel/built-in.o: In function `visws_early_detect': : undefined reference to `mach_get_smp_config_quirk' arch/x86/kernel/built-in.o: In function `visws_early_detect': : undefined reference to `mach_find_smp_config_quirk' Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: build fixIngo Molnar2008-07-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | fix: arch/x86/kernel/visws_quirks.c: In function ‘visws_early_detect’: arch/x86/kernel/visws_quirks.c:293: error: ‘no_broadcast’ undeclared (first use in this function) arch/x86/kernel/visws_quirks.c:293: error: (Each undeclared identifier is reported only once arch/x86/kernel/visws_quirks.c:293: error: for each function it appears in.) make[1]: *** [arch/x86/kernel/visws_quirks.o] Error 1 make: *** [arch/x86/kernel/visws_quirks.o] Error 2 Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: do not allow VisWS for VoyagerIngo Molnar2008-07-101-1/+1
| | | | | | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, update include file changeIngo Molnar2008-07-101-1/+1
| | | | | | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86/pci: fix warnings in subsys_initcall functionsRobert Richter2008-07-101-0/+2
| | | | | | | | | | | | Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86/pci merge: fixing numaq initializationRobert Richter2008-07-103-9/+5
| | | | | | | | | | | | | | | | | | | | Patch d49c4288 (tip/x86/mpparse) introduced some changes in calling subsys_init calls if CONFIG_X86_NUMAQ option is set. This patch updates subsystem initalization according to this changes. Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, eliminate Kconfig specialsIngo Molnar2008-07-104-4/+3
| | | | | | | | | | | | remove leftover traces of various VISWS related Kconfig specials. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, remove leftover filesIngo Molnar2008-07-107-884/+0
| | | | | | | | | | | | remove leftover arch/x86/mach-visws/* files. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, clean upIngo Molnar2008-07-104-369/+372
| | | | | | | | | | | | | | | | merge traps_visws.c and apic_visws.c into visws_quirks.c. (no code changed) Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, clean upIngo Molnar2008-07-102-1/+1
| | | | | | | | | | | | rename setup_visws.c to visws_quirks.c. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, IO-APIC setup fixIngo Molnar2008-07-101-0/+7
| | | | | | | | | | | | skip IO-APIC setup on a VISWS if it's enabled. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, clean upIngo Molnar2008-07-101-15/+15
| | | | | | | | | | | | | | remove VISWS Kconfig complications, now that it's supported by the generic architecture. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, flip over VISWS to generic archIngo Molnar2008-07-103-15/+16
| | | | | | | | | | | | | | | | | | this is the big move: flip over VISWS to generic arch support. From this commit on CONFIG_X86_VISWS is just another (default-disabled) option that turns on certain quirks - no other complications. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, copy visws filesIngo Molnar2008-07-103-0/+697
| | | | | | | | | | | | | | | | copy arch/x86/mach-visws/setup_visws.c, apic_visws.c and traps_visws.c files to arch/x86/kernel/, in preparation of the switchover to a non-subarch setup for VISWS. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, add early quirks to default architecturesIngo Molnar2008-07-101-0/+30
| | | | | | | | | | | | | | | | | | add early quirk support to the generic architecture code. this allows VISWS to be supported by the generic code and allows us to remove the VISWS subarch. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, add NR_IRQS quirkIngo Molnar2008-07-101-2/+2
| | | | | | | | | | | | | | | | | | NR_IRQS: let VISWS be just a sub-case of the generic code. This can create a somewhat larger irq_desc[] array if NR_CPUS is high but that should not worry VisWS which has 4 CPUs at most. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, eliminate ↵Ingo Molnar2008-07-101-3/+1
| | | | | | | | | | | | | | | | include/asm-x86/mach-visws/setup_arch.h use the generic version of setup_arch.h - it's the same. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, move definitionsIngo Molnar2008-07-103-5/+6
| | | | | | | | | | | | | | | | move the SGIVW definitions from setup_arch.h into its own header file. preparation for turning VISWS into a generic PC architecture. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, create include/asm-x86/visws/Ingo Molnar2008-07-107-9/+8
| | | | | | | | | | | | | | | | | | | | move the include/asm-x86/mach-visws/ VISWS specific hardware details include files into include/asm-x86/visws, to be used from generic code. No code changed. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, eliminate asm-x86/mach-visws/mach_apicdef.hIngo Molnar2008-07-101-24/+1
| | | | | | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, update asm-x86/mach-visws/mach_apicdef.hIngo Molnar2008-07-101-5/+17
| | | | | | | | | | | | | | | | | | update asm-x86/mach-visws/mach_apicdef.h to the generic version. This should work fine as VISWS has a standard local APIC and thus its mach_apicdef.h copy is just an ancient version of the generic code. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, eliminate ↵Ingo Molnar2008-07-101-59/+1
| | | | | | | | | | | | | | | | | | | | include/asm-x86/mach-visws/smpboot_hooks.h now that include/asm-x86/mach-visws/smpboot_hooks.h equals to the default file in ../mach-default/smpboot_hooks.h, simply include it instead of maintaining a copy. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, update ↵Ingo Molnar2008-07-101-7/+38
| | | | | | | | | | | | | | | | | | | | | | | | include/asm-x86/mach-visws/smpboot_hooks.h update include/asm-x86/mach-visws/smpboot_hooks.h to include/asm-x86/mach-default/smpboot_hooks.h (the generic version). this _should_ work, because VISWS sets skip_ioapic_setup, but it should be tested on a real VISWS to make sure. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, enhance ↵Ingo Molnar2008-07-101-0/+6
| | | | | | | | | | | | | | | | | | | | include/asm-x86/mach-default/smpboot_hooks.h Allow the generic smpboot quirks code to be built with ONFIG_X86_IO_APIC disabled. This way VISWS will be able to use it as-is. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, eliminate ↵Ingo Molnar2008-07-101-141/+1
| | | | | | | | | | | | | | | | | | | | include/asm-x86/mach-visws/mach_apic.h now that include/asm-x86/mach-visws/mach_apic.h equals to include/asm-x86/mach-default/mach_apic.h, simply start using the generic one. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, update asm-x86/mach-visws/mach_apic.hIngo Molnar2008-07-101-33/+71
| | | | | | | | | | | | update asm-x86/mach-visws/mach_apic.h to the generic version. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, install proper PCI quirkIngo Molnar2008-07-103-1/+13
| | | | | | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, use generic mpparse codeIngo Molnar2008-07-104-95/+102
| | | | | | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, add early init quirksIngo Molnar2008-07-1010-63/+274
| | | | | | | | | | | | | | add early init quirks for VisWS. This gradually turns the VISWS subarch into a generic PC architecture. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86, VisWS: turn into generic arch, make VisWS boot on a regular PCIngo Molnar2008-07-108-155/+119
| | | | | | | | | | | | | | | | | | | | | | first step: make the VISWS subarch boot on a regular PC. We take various shortcuts for that. We copy the generic arch setup file over into the VISWS setup file. This is the only step that is not expected to boot on a real VISWS. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: add early quirk supportIngo Molnar2008-07-104-2/+47
| | | | | | | | | | | | | | | | | | | | Add early quirks support. In preparation of enabling the generic architecture to boot on a VISWS. This will allow us to remove the VISWS subarch and all its complications. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * Merge branch 'x86/core' into x86/generalize-viswsIngo Molnar2008-07-10387-15581/+23418
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* | | x86: Recover timer_ack lost in the merge of the NMI watchdogMaciej W. Rozycki2008-07-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the course of the recent unification of the NMI watchdog an assignment to timer_ack to switch off unnecesary POLL commands to the 8259A in the case of a watchdog failure has been accidentally removed. The statement used to be limited to the 32-bit variation as since the rewrite of the timer code it has been relevant for the 82489DX only. This change brings it back. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: I/O APIC: Never configure IRQ2Maciej W. Rozycki2008-07-112-18/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no such entity as ISA IRQ2. The ACPI spec does not make it explicitly clear, but does not preclude it either -- all it says is ISA legacy interrupts are identity mapped by default (subject to overrides), but it does not state whether IRQ2 exists or not. As a result if there is no IRQ0 override, then IRQ2 is normally initialised as an ISA interrupt, which implies an edge-triggered line, which is unmasked by default as this is what we do for edge-triggered I/O APIC interrupts so as not to miss an edge. To the best of my knowledge it is useless, as IRQ2 has not been in use since the PC/AT as back then it was taken by the 8259A cascade interrupt to the slave, with the line position in the slot rerouted to newly-created IRQ9. No device could thus make use of this line with the pair of 8259A chips. Now in theory INTIN2 of the I/O APIC may be usable, but the interrupt of the device wired to it would not be available in the PIC mode at all, so I seriously doubt if anybody decided to reuse it for a regular device. However there are two common uses of INTIN2. One is for IRQ0, with an ACPI interrupt override (or its equivalent in the MP table). But in this case IRQ2 is gone entirely with INTIN0 left vacant. The other one is for an 8959A ExtINTA cascade. In this case IRQ0 goes to INTIN0 and if ACPI is used INTIN2 is assumed to be IRQ2 (there is no override and ACPI has no way to report ExtINTA interrupts). This is where a problem happens. The problem is INTIN2 is configured as a native APIC interrupt, with a vector assigned and the mask cleared. And the line may indeed get active and inject interrupts if the master 8959A has its timer interrupt enabled (it might happen for other interrupts too, but they are normally masked in the process of rerouting them to the I/O APIC). There are two cases where it will happen: * When the I/O APIC NMI watchdog is enabled. This is actually a misnomer as the watchdog pulses are delivered through the 8259A to the LINT0 inputs of all the local APICs in the system. The implication is the output of the master 8259A goes high and low repeatedly, signalling interrupts to INTIN2 which is enabled too! [The origin of the name is I think for a brief period during the development we had a capability in our code to configure the watchdog to use an I/O APIC input; that would be INTIN2 in this scenario.] * When the native route of IRQ0 via INTIN0 fails for whatever reason -- as it happens with the system considered here. In this scenario the timer pulse is delivered through the 8259A to LINT0 input of the local APIC of the bootstrap processor, quite similarly to how is done for the watchdog described above. The result is, again, INTIN2 receives these pulses too. Rafael's system used to escape this scenario, because an incorrect IRQ0 override would occupy INTIN2 and prevent it from being unmasked. My conclusion is IRQ2 should be excluded from configuration in all the cases and the current exception for ACPI systems should be lifted. The reason being the exception not only being useless, but harmful as well. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: Matthew Garrett <mjg59@srcf.ucam.org> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: L-APIC: Always fully configure IRQ0Maciej W. Rozycki2008-07-112-18/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike the 32-bit one, the 64-bit variation of the LVT0 setup code for the "8259A Virtual Wire" through the local APIC timer configuration does not fully configure the relevant irq_chip structure. Instead it relies on the preceding I/O APIC code to have set it up, which does not happen if the I/O APIC variants have not been tried. The patch includes corresponding changes to the 32-bit variation too which make them both the same, barring a small syntactic difference involving sequence of functions in the source. That should work as an aid with the upcoming merge. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: Matthew Garrett <mjg59@srcf.ucam.org> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: L-APIC: Set IRQ0 as edge-triggeredMaciej W. Rozycki2008-07-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IRQ0 is edge-triggered, but the "8259A Virtual Wire" through the local APIC configuration in the 32-bit version uses the "fasteoi" handler suitable for level-triggered APIC interrupt. Rewrite code so that the "edge" handler is used. The 64-bit version uses different code and is unaffected. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: Matthew Garrett <mjg59@srcf.ucam.org> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: merge dwarf2 headersGlauber Costa2008-07-113-122/+59
| | | | | | | | | | | | | | | | | | | | | Merge dwarf2_32.h and dwarf2_64.h into dwarf2.h. Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: use AS_CFI instead of UNWIND_INFOGlauber Costa2008-07-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In dwarf2_32.h, test for CONFIG_AS_CFI instead of CONFIG_UNWIND_INFO. Turns out that searching for UNWIND_INFO returns no match in any Kconfig or Makefile, so we're really just throwing everything away regarding dwarf frames for i386. The test that generates CONFIG_AS_CFI does not have anything x86_64-specific, and right now, checking V=1 builds shows me that the flags is there anyway, although unused. Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: use ignore macro instead of hash commentGlauber Costa2008-07-111-15/+17
| | | | | | | | | | | | | | | | | | | | | | | | In dwarf_64.h header, use the "ignore" macro the way i386 does. Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: use matching CFI_ENDPROCGlauber Costa2008-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The RING0_INT_FRAME macro defines a CFI_STARTPROC. So we should really be using CFI_ENDPROC after it. Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: fix savesegment() bug causing crashes on 64-bitIngo Molnar2008-07-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i spent a fair amount of time chasing a 64-bit bootup crash that manifested itself as bootup segfaults: S10network[1825]: segfault at 7f3e2b5d16b8 ip 00000031108748c9 sp 00007fffb9c14c70 error 4 in libc-2.7.so[3110800000+14d000] eventually causing init to die and panic the system: Kernel panic - not syncing: Attempted to kill init! Pid: 1, comm: init Not tainted 2.6.26-rc9-tip #13878 after a maratonic bisection session, the bad commit turned out to be: | b7675791859075418199c7af86a116ea34eaf5bd is first bad commit | commit b7675791859075418199c7af86a116ea34eaf5bd | Author: Jeremy Fitzhardinge <jeremy@goop.org> | Date: Wed Jun 25 00:19:00 2008 -0400 | | x86: remove open-coded save/load segment operations | | This removes a pile of buggy open-coded implementations of savesegment | and loadsegment. after some more bisection of this patch itself, it turns out that what makes the difference are the savesegment() changes to __switch_to(). Taking a look at this portion of arch/x86/kernel/process_64.o revealed this crutial difference: | good: 99c: 8c e0 mov %fs,%eax | 99e: 89 45 cc mov %eax,-0x34(%rbp) | | bad: 99c: 8c 65 cc mov %fs,-0x34(%rbp) which is due to: | unsigned fsindex; | - asm volatile("movl %%fs,%0" : "=r" (fsindex)); | + savesegment(fs, fsindex); savesegment() is implemented as: #define savesegment(seg, value) \ asm("mov %%" #seg ",%0":"=rm" (value) : : "memory") note the "m" modifier - it allows GCC to generate the segment move into a memory operand as well. But regarding segment operands there's a subtle detail in the x86 instruction set: the above 16-bit moves are zero-extend, but only if it goes to a register. If it goes to a memory operand, -0x34(%rbp) in the above case, there's no zero-extend to 32-bit and the instruction will only save 16 bits instead of the intended 32-bit. The other 16 bits is random data - which can cause problems when that value is used later on. The solution is to only allow segment operands to go to registers. This fix allows my test-system to boot up without crashing. Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86_64: vdso32 cleanup using feature flagsJeremy Fitzhardinge2008-07-111-10/+1
| | | | | | | | | | | | | | | | | | | | | Use the X86_FEATURE_SYSENTER32 to remove hard-coded CPU vendor check. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86_64: add pseudo-features for 32-bit compat syscallJeremy Fitzhardinge2008-07-114-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add pseudo-feature bits to describe whether the CPU supports sysenter and/or syscall from ia32-compat userspace. This removes a hardcoded test in vdso32-setup. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: fix tsc unification buglet with ftrace and stackprotectorIngo Molnar2008-07-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Yinghai Lu reported crashes on 64-bit x86: BUG: unable to handle kernel NULL pointer dereference at 0000000000000000 IP: [<ffffffff80253b17>] hrtick_start_fair+0x89/0x173 [...] And with a long session of debugging and a lot of difficulty, tracked it down to this commit: ---------------> 8fbbc4b45ce3e4c0eeb15004c79c72b6896a79c2 is first bad commit commit 8fbbc4b45ce3e4c0eeb15004c79c72b6896a79c2 Author: Alok Kataria <akataria@vmware.com> Date: Tue Jul 1 11:43:34 2008 -0700 x86: merge tsc_init and clocksource code <-------------- The problem is that the TSC unification missed these Makefile rules in arch/x86/kernel/Makefile: # Do not profile debug and lowlevel utilities CFLAGS_REMOVE_tsc_64.o = -pg CFLAGS_REMOVE_tsc_32.o = -pg ... CFLAGS_tsc_64.o := $(nostackp) ... which rules make sure that various instrumentation and debugging facilities are disabled for code that might end up in a VDSO - such as the TSC code. Reported-and-bisected-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Conflicts: Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: introduce max_low_pfn_mapped for 64-bitYinghai Lu2008-07-1112-17/+74
| | | | | | | | | | | | | | | | | | | | | | | | when more than 4g memory is installed, don't map the big hole below 4g. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: reserve SLITYinghai Lu2008-07-111-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | save the SLIT, in case we are using fixmap to read it, and that fixmap could be cleared by others. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | x86: e820: user-defined memory maps: remove the range instead of update it ↵Yinghai Lu2008-07-111-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to reserved also let mem= to print out modified e820 map too Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Bernhard Walle <bwalle@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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