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| * [SPARC64]: Fix and re-enable dynamic TSB sizing.David S. Miller2006-03-205-118/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is good for up to %50 performance improvement of some test cases. The problem has been the race conditions, and hopefully I've plugged them all up here. 1) There was a serious race in switch_mm() wrt. lazy TLB switching to and from kernel threads. We could erroneously skip a tsb_context_switch() and thus use a stale TSB across a TSB grow event. There is a big comment now in that function describing exactly how it can happen. 2) All code paths that do something with the TSB need to be guarded with the mm->context.lock spinlock. This makes page table flushing paths properly synchronize with both TSB growing and TLB context changes. 3) TSB growing events are moved to the end of successful fault processing. Previously it was in update_mmu_cache() but that is deadlock prone. At the end of do_sparc64_fault() we hold no spinlocks that could deadlock the TSB grow sequence. We also have dropped the address space semaphore. While we're here, add prefetching to the copy_tsb() routine and put it in assembler into the tsb.S file. This piece of code is quite time critical. There are some small negative side effects to this code which can be improved upon. In particular we grab the mm->context.lock even for the tsb insert done by update_mmu_cache() now and that's a bit excessive. We can get rid of that locking, and the same lock taking in flush_tsb_user(), by disabling PSTATE_IE around the whole operation including the capturing of the tsb pointer and tsb_nentries value. That would work because anyone growing the TSB won't free up the old TSB until all cpus respond to the TSB change cross call. I'm not quite so confident in that optimization to put it in right now, but eventually we might be able to and the description is here for reference. This code seems very solid now. It passes several parallel GCC bootstrap builds, and our favorite "nut cruncher" stress test which is a full "make -j8192" build of a "make allmodconfig" kernel. That puts about 256 processes on each cpu's run queue, makes lots of process cpu migrations occur, causes lots of page table and TLB flushing activity, incurs many context version number changes, and it swaps the machine real far out to disk even though there is 16GB of ram on this test system. :-) Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SUNSU]: Fix missing spinlock initialization.David S. Miller2006-03-201-0/+2
| | | | | | | | | | | | Caught by CONFIG_DEBUG_SPINLOCK. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [TG3]: Do not try to access NIC_SRAM_DATA_SIG on Sun parts.David S. Miller2006-03-201-0/+4
| | | | | | | | | | | | | | Sun does't put an SEEPROM behind the tigon3 chip, among other things, so accesses to these areas just give bus timeouts. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: First cut at VIS simulator for Niagara.David S. Miller2006-03-203-1/+901
| | | | | | | | | | | | | | Niagara does not implement some of the VIS instructions in hardware, so we have to emulate them. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix system type in /proc/cpuinfo and remove bogus OBP check.David S. Miller2006-03-204-90/+12
| | | | | | | | | | | | | | | | | | | | Report 'sun4v' when appropriate in /proc/cpuinfo Remove all the verifications of the OBP version string. Just make sure it's there, and report it raw in the bootup logs and via /proc/cpuinfo. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add SMT scheduling support for Niagara.David S. Miller2006-03-203-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | The mapping is a simple "(cpuid >> 2) == core" for now. Later we'll add more sophisticated code that will walk the sun4v machine description and figure this out from there. We should also add core mappings for jaguar and panther processors. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix 32-bit truncation which broke sparsemem.David S. Miller2006-03-201-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The page->flags manipulations done by the D-cache dirty state tracking was broken because the constants were not marked with "UL" to make them 64-bit, which means we were clobbering the upper 32-bits of page->flags all the time. This doesn't jive well with sparsemem which stores the section and indexing information in the top 32-bits of page->flags. This is yet another sparc64 bug which has been with us forever. While we're here, tidy up some things in bootmem_init() and paginig_init(): 1) Pass min_low_pfn to init_bootmem_node(), it's identical to (phys_base >> PAGE_SHIFT) but we should use consistent with the variable names we print in CONFIG_BOOTMEM_DEBUG 2) max_mapnr, although no longer used, was being set inaccurately, we shouldn't subtract pfn_base any more. 3) All the games with phys_base in the zones_*[] arrays we pass to free_area_init_node() are no longer necessary. Thanks to Josh Grebe and Fabbione for the bug reports and testing. Fix also verified locally on an SB2500 which had a memory layout that triggered the same problem. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Move over to sparsemem.David S. Miller2006-03-207-54/+123
| | | | | | | | | | | | | | | | This has been pending for a long time, and the fact that we waste a ton of ram on some configurations kind of pushed things over the edge. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix new context version SMP handling.David S. Miller2006-03-2010-46/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't piggy back the SMP receive signal code to do the context version change handling. Instead allocate another fixed PIL number for this asynchronous cross-call. We can't use smp_call_function() because this thing is invoked with interrupts disabled and a few spinlocks held. Also, fix smp_call_function_mask() to count "cpus" correctly. There is no guarentee that the local cpu is in the mask yet that is exactly what this code was assuming. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Bulletproof MMU context locking.David S. Miller2006-03-203-5/+7
| | | | | | | | | | | | | | | | | | | | | | 1) Always spin_lock_init() in init_context(). The caller essentially clears it out, or copies the mm info from the parent. In both cases we need to explicitly initialize the spinlock. 2) Always do explicit IRQ disabling while taking mm->context.lock and ctx_alloc_lock. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: kzalloc() conversionEric Sesterhenn2006-03-2011-58/+27
| | | | | | | | | | | | | | | | this patch converts arch/sparc64 to kzalloc usage. Crosscompile tested with allyesconfig. Signed-off-by: Eric Sesterhenn <snakebyte@gmx.de> Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix loop termination in mark_kpte_bitmap()David S. Miller2006-03-201-1/+4
| | | | | | | | | | | | | | | | | | If we were aligned, but didn't have at least 256MB left to process, we would loop forever. Thanks to fabbione for the report and testing the fix. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Simplify TSB insert checks.David S. Miller2006-03-202-23/+6
| | | | | | | | | | | | | | | | | | | | | | | | Don't try to avoid putting non-base page sized entries into the user TSB. It actually costs us more to check this than it helps. Eventually we'll have a multiple TSB scheme for user processes. Once a process starts using larger pages, we'll allocate and use such a TSB. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: More SUN4V cpu mondo bug fixing.David S. Miller2006-03-201-16/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This cpu mondo sending interface isn't all that easy to use correctly... We were clearing out the wrong bits from the "mask" after getting something other than EOK from the hypervisor. It turns out the hypervisor can just be resent the same cpu_list[] array, with the 0xffff "done" entries still in there, and it will do the right thing. So don't update or try to rebuild the cpu_list[] array to condense it. This requires the "forward_progress" check to be done slightly differently, but this new scheme is less bug prone than what we were doing before. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix sun4v mna winfixup handling.David S. Miller2006-03-201-4/+4
| | | | | | | | | | | | | | We were clobbering a base register before we were done using it. Fix a comment typo while we're here. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix mini RTC driver reading.David S. Miller2006-03-201-0/+2
| | | | | | | | | | | | | | Need to subtract 1900 from year and 1 from month before giving it back to userspace. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Do not allow mapping pages within 4GB of 64-bit VA hole.David S. Miller2006-03-203-24/+73
| | | | | | | | | | | | | | | | | | | | The UltraSPARC T1 manual recommends this because the chip could instruction prefetch into the VA hole, and this would also make decoding certain kinds of memory access traps more difficult (because the chip sign extends certain pieces of trap state). Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix _PAGE_EXEC handling.David S. Miller2006-03-203-8/+15
| | | | | | | | | | | | | | | | | | | | | | First of all, use the known _PAGE_EXEC_{4U,4V} value instead of loading _PAGE_EXEC from memory. We either know which one to use by context, or we can code patch the test. Next, we need to check executability of a PTE in the generic TSB miss handler. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix typo in SUN4V D-TLB miss handler.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | Should put FAULT_CODE_DTLB into %g3 not FAULT_CODE_ITLB. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Kill bogus function externs in asm/pgtable.hDavid S. Miller2006-03-201-24/+0
| | | | | | | | | | | | These are all implemented inline earlier in the file. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add mini-RTC driver for Starfire and SUN4V.David S. Miller2006-03-201-0/+279
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix bugs in SUN4V cpu mondo dispatch.David S. Miller2006-03-203-57/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were several bugs in the SUN4V cpu mondo dispatch code. In fact, if we ever got a EWOULDBLOCK or other error from the hypervisor call, we'd potentially send a cpu mondo multiple times to the same cpu and even worse we could loop until the timeout resending the same mondo over and over to such cpus. So let's bulletproof this thing as follows: 1) Implement cpu_mondo_send() and cpu_state() hypervisor calls in arch/sparc64/kernel/entry.S, add prototypes to asm/hypervisor.h 2) Don't build and update the cpulist using inline functions, this was causing the cpu mask to not get updated in the caller. 3) Disable interrupts during the entire mondo send, otherwise our cpu list and/or mondo block could get overwritten if we take an interrupt and do a cpu mondo send on the current cpu. 4) Check for all possible error return types from the cpu_mondo_send() hypervisor call. In particular: HV_EOK) Our work is done, all cpus have received the mondo. HV_CPUERROR) One or more of the cpus in the cpu list we passed to the hypervisor are in error state. Use cpu_state() calls over the entries in the cpu list to see which ones. Record them in "error_mask" and report this after we are done sending the mondo to cpus which are not in error state. HV_EWOULDBLOCK) We need to keep trying. Any other error we consider fatal, we report the event and exit immediately. 5) We only timeout if forward progress is not made. Forward progress is defined as having at least one cpu get the mondo successfully in a given cpu_mondo_send() call. Otherwise we bump a counter and delay a little. If the counter hits a limit, we signal an error and report the event. Also, smp_call_function_mask() error handling reports the number of cpus incorrectly. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix bugs in SMP TLB context version expiration handling.David S. Miller2006-03-201-6/+10
| | | | | | | | | | | | | | | | | | 1) We must flush the TLB, duh. 2) Even if the sw context was seen to be valid, the local cpu's hw context can be out of date, so reload it unconditionally. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix indexing into kpte_linear_bitmap.David S. Miller2006-03-201-0/+1
| | | | | | | | | | | | | | Need to shift back up by 3 bits to get 8-byte entry index. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Use 13-bit context size always.David S. Miller2006-03-201-13/+1
| | | | | | | | | | | | | | We no longer have the problems that require using the smaller sizes. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Avoid dcache-dirty page state management on sun4v.David S. Miller2006-03-202-23/+30
| | | | | | | | | | | | | | It is totally wasted work, since we have no D-cache aliasing issues on sun4v. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Bulletproof hypervisor TLB flushing.David S. Miller2006-03-202-26/+80
| | | | | | | | | | | | | | | | | | | | | | Check TLB flush hypervisor calls for errors and report them. Pass HV_MMU_ALL always for now, we can add back the optimization to avoid the I-TLB flush later. Always explicitly page align the virtual address arguments. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Report mondo error correctly in hypervisor_xcall_deliver().David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | It's in "arg0" not "func". Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Niagara optimized XOR functions for RAID.David S. Miller2006-03-203-5/+342
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix binfmt_aout32.c build.Andrew Morton2006-03-201-1/+1
| | | | | | | | | | Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: destroy_context() needs to disable interrupts.David S. Miller2006-03-201-2/+3
| | | | | | | | | | | | | | | | | | | | get_new_mmu_context() can be invoked from interrupt context now for the new SMP version wrap handling. So disable interrupt while taking ctx_alloc_lock in destroy_context() so we don't deadlock. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix TLB context allocation with SMT style shared TLBs.David S. Miller2006-03-204-25/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The context allocation scheme we use depends upon there being a 1<-->1 mapping from cpu to physical TLB for correctness. Chips like Niagara break this assumption. So what we do is notify all cpus with a cross call when the context version number changes, and if necessary this makes them allocate a valid context for the address space they are running at the time. Stress tested with make -j1024, make -j2048, and make -j4096 kernel builds on a 32-strand, 8 core, T2000 with 16GB of ram. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Put syscall tables after trap table.David S. Miller2006-03-201-1/+2
| | | | | | | | | | | | | | Otherwise with too much stuff enabled in the kernel config we can end up with an unaligned trap table. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Export _PAGE_E and _PAGE_CACHE to modules.David S. Miller2006-03-201-0/+4
| | | | | | | | | | | | | | | | SBUS flash driver needs it. Noticed by Fabbione. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix %tstate ASI handling in start_thread{,32}()David S. Miller2006-03-201-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Niagara helps us find a ancient bug in the sparc64 port :-) The ASI_* values are plain constant defines, thus signed 32-bit on sparc64. To put shift this into the regs->tstate value we were doing or'ing "(ASI_PNF << 24)" into there. ASI_PNF is 0x82 and shifted left by 24 makes that topmost bit the sign bit in a 32-bit value. This would get sign extended to 64-bits and thus corrupt the top-half of the reg->tstate value. This never caused problems in pre-Niagara cpus because the only thing up there were the condition code values. But Niagara has the global register level field, and this all 1's value is illegal there so Niagara gives an illegal instruction trap due to this bug. I'm pretty sure this bug is about as old as the sparc64 port itself. This also points out that we weren't setting ASI_PNF for 32-bit tasks. We should, so fix that while we're here. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Drop %gl to 0 before re-enabling PSTATE_IE in rtrapDavid S. Miller2006-03-201-1/+2
| | | | | | | | | | | | | | | | If we take a window fault, on SUN4V set %gl to zero before we turn PSTATE_IE back on in %pstate. Otherwise if we take an interrupt we'll end up with corrupt register state. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.David S. Miller2006-03-203-6/+48
| | | | | | | | | | | | | | | | | | | | It can map all of the linear kernel mappings with zero TSB hash conflicts for systems with 16GB or less ram. In such cases, on SUN4V, once we load up this TSB the first time with all the mappings, we never take a linear kernel mapping TLB miss ever again, the hypervisor handles them all. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Make use of Niagara 256MB PTEs for kernel mappings.David S. Miller2006-03-202-15/+96
| | | | | | | | | | | | | | | | | | | | | | We use a bitmap, one bit for every 256MB of memory. If the bit is set we can use a 256MB PTE for linear mappings, else we have to use a 4MB PTE. SUN4V support is there, and we can very easily add support for Panther cpu 256MB PTEs in the future. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Use sun4v_cpu_idle() in cpu_idle() on SUN4V.David S. Miller2006-03-201-49/+32
| | | | | | | | | | | | | | | | | | | | | | We have to turn off the "polling nrflag" bit when we sleep the cpu like this, so that we'll get a cross-cpu interrupt to wake the processor up from the yield. We also have to disable PSTATE_IE in %pstate around the yield call and recheck need_resched() in order to avoid any races. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64] math-emu: Delete debugging printk left by previous commit.David S. Miller2006-03-201-1/+0
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add sun4v_cpu_yield().David S. Miller2006-03-202-0/+12
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Kill cpudata->idle_volume.David S. Miller2006-03-203-11/+3
| | | | | | | | | | | | | | | | | | Set, but never used. We used to use this for dynamic IRQ retargetting, but that code died a long time ago. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Niagara optimized memset/bzero/clear_user.David S. Miller2006-03-203-1/+165
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Pass multiple CPUs at once to hypervisor cross-call API.David S. Miller2006-03-201-54/+0
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Args to SUNW,set-trap-table are 64-bit.David S. Miller2006-03-201-2/+7
| | | | | | | | | | | | | | | | They were getting truncated to 32-bit and this is very bad when your MMU fault status area is in physical memory above 4GB on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Handle unimplemented FPU square-root on Niagara.David S. Miller2006-03-201-2/+23
| | | | | | | | | | | | | | | | The math-emu code only expects unfinished fpop traps when emulating FPU sqrt instructions on pre-Niagara chips. On Niagara we can get unimplemented fpop, so handle that. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC] serial: Make sure sysfs nodes get named correctly.David S. Miller2006-03-204-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Because we play this trick where we use ttyS? in increasing minor numbers for different sunfoo.c drivers, we have to inform the TTY layer of this. Do so by setting the tty->name_base appropriately. Probably there should be a generic way to do this in the serial core, but for now... Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Typo in sun4v_data_access_exception log message.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | Should be "Dax" not "Iax". Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Handle zero-length map requests in pci_sun4v.cDavid S. Miller2006-03-201-2/+2
| | | | | | | | | | | | | | By simply changing the do-while loop into a plain while loop. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Kill stray PGLIST_NENTS check in pci_sun4v.cDavid S. Miller2006-03-201-2/+0
| | | | | | | | | | | | | | I forgot to remove the one in pci_4v_map_sg() during the iommu batching commit. Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit (git 2.34.1) at 2024-11-14 17:24:49 +0000