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-rw-r--r--arch/mips/mm/page.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 1417c649485..48060c635ac 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void)
*/
cache_line_size = cpu_dcache_line_size();
switch (current_cpu_type()) {
+ case CPU_R5500:
case CPU_TX49XX:
- /* TX49 supports only Pref_Load */
+ /* These processors only support the Pref_Load. */
pref_bias_copy_load = 256;
break;