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| author | Kyungmin Park <kyungmin.park@samsung.com> | 2006-05-12 17:03:07 +0300 |
|---|---|---|
| committer | Jarkko Lavinen <lavinen@pentafluge.infradead.org> | 2006-05-12 15:35:50 +0100 |
| commit | 493c646077ef0b8668ed71b8057f81cb7454af87 (patch) | |
| tree | e05992a8d8c9ba911e5a9809dc0678ca50e96c76 /include | |
| parent | 3cecf69ecde22199699c4f0e609dfed2a487b674 (diff) | |
| download | kernel-crypto-493c646077ef0b8668ed71b8057f81cb7454af87.tar.gz kernel-crypto-493c646077ef0b8668ed71b8057f81cb7454af87.tar.xz kernel-crypto-493c646077ef0b8668ed71b8057f81cb7454af87.zip | |
OneNAND: One-Time Programmable (OTP) support
One Block of the NAND Flash Array memory is reserved as
a One-Time Programmable Block memory area.
Also, 1st Block of NAND Flash Array can be used as OTP.
The OTP block can be read, programmed and locked using the same
operations as any other NAND Flash Array memory block.
OTP block cannot be erased.
OTP block is fully-guaranteed to be a valid block.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mtd/onenand.h | 2 | ||||
| -rw-r--r-- | include/linux/mtd/onenand_regs.h | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 22322c8a772..3f5919f2e9d 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -35,6 +35,8 @@ typedef enum { FL_SYNCING, FL_UNLOCKING, FL_LOCKING, + FL_RESETING, + FL_OTPING, FL_PM_SUSPENDED, } onenand_state_t; diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index d7832ef8ed6..4a72818d254 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -112,6 +112,7 @@ #define ONENAND_CMD_LOCK_TIGHT (0x2C) #define ONENAND_CMD_ERASE (0x94) #define ONENAND_CMD_RESET (0xF0) +#define ONENAND_CMD_OTP_ACCESS (0x65) #define ONENAND_CMD_READID (0x90) /* NOTE: Those are not *REAL* commands */ @@ -152,6 +153,8 @@ #define ONENAND_CTRL_ERASE (1 << 11) #define ONENAND_CTRL_ERROR (1 << 10) #define ONENAND_CTRL_RSTB (1 << 7) +#define ONENAND_CTRL_OTP_L (1 << 6) +#define ONENAND_CTRL_OTP_BL (1 << 5) /* * Interrupt Status Register F241h (R) @@ -177,4 +180,9 @@ #define ONENAND_ECC_2BIT (1 << 1) #define ONENAND_ECC_2BIT_ALL (0xAAAA) +/* + * One-Time Programmable (OTP) + */ +#define ONENAND_OTP_LOCK_OFFSET (14) + #endif /* __ONENAND_REG_H */ |