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| author | David Woodhouse <dwmw2@infradead.org> | 2007-01-18 10:34:51 +1100 |
|---|---|---|
| committer | David Woodhouse <dwmw2@infradead.org> | 2007-01-18 10:34:51 +1100 |
| commit | 9cdf083f981b8d37b3212400a359368661385099 (patch) | |
| tree | aa15a6a08ad87e650dea40fb59b3180bef0d345b /include/asm-xtensa/cache.h | |
| parent | e499e01d234a31d59679b7b1e1cf628d917ba49a (diff) | |
| parent | a8b3485287731978899ced11f24628c927890e78 (diff) | |
| download | kernel-crypto-9cdf083f981b8d37b3212400a359368661385099.tar.gz kernel-crypto-9cdf083f981b8d37b3212400a359368661385099.tar.xz kernel-crypto-9cdf083f981b8d37b3212400a359368661385099.zip | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-xtensa/cache.h')
| -rw-r--r-- | include/asm-xtensa/cache.h | 20 |
1 files changed, 6 insertions, 14 deletions
diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h index 1e79c0e2746..1c4a78f29ae 100644 --- a/include/asm-xtensa/cache.h +++ b/include/asm-xtensa/cache.h @@ -4,7 +4,6 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * 2 of the License, or (at your option) any later version. * * (C) 2001 - 2005 Tensilica Inc. */ @@ -12,21 +11,14 @@ #ifndef _XTENSA_CACHE_H #define _XTENSA_CACHE_H -#include <xtensa/config/core.h> +#include <asm/variant/core.h> -#if XCHAL_ICACHE_SIZE > 0 -# if (XCHAL_ICACHE_SIZE % (XCHAL_ICACHE_LINESIZE*XCHAL_ICACHE_WAYS*4)) != 0 -# error cache configuration outside expected/supported range! -# endif -#endif +#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH +#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE +#define SMP_CACHE_BYTES L1_CACHE_BYTES -#if XCHAL_DCACHE_SIZE > 0 -# if (XCHAL_DCACHE_SIZE % (XCHAL_DCACHE_LINESIZE*XCHAL_DCACHE_WAYS*4)) != 0 -# error cache configuration outside expected/supported range! -# endif -#endif +#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) +#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) -#define L1_CACHE_SHIFT XCHAL_CACHE_LINEWIDTH_MAX -#define L1_CACHE_BYTES XCHAL_CACHE_LINESIZE_MAX #endif /* _XTENSA_CACHE_H */ |