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| author | Stephane Eranian <eranian@hpl.hp.com> | 2006-12-07 02:14:02 +0100 |
|---|---|---|
| committer | Andi Kleen <andi@basil.nowhere.org> | 2006-12-07 02:14:02 +0100 |
| commit | 86efef50cfff9905c4e4ec64f3d3d3b299226674 (patch) | |
| tree | e60029ca0b888b1f01a049d9e512ef524b2279e3 /include/asm-x86_64 | |
| parent | fa5cecd111d235819a1d807d43216ae459a0dd6f (diff) | |
| download | kernel-crypto-86efef50cfff9905c4e4ec64f3d3d3b299226674.tar.gz kernel-crypto-86efef50cfff9905c4e4ec64f3d3d3b299226674.tar.xz kernel-crypto-86efef50cfff9905c4e4ec64f3d3d3b299226674.zip | |
[PATCH] x86-64: x86-64 add Intel Core related PMU MSRs definitions
Add o the x86-64 tree a bunch of MSRs related to performance
monitoring for the processors based on Intel Core microarchitecture.
It also adds some architectural MSRs for PEBS. A similar patch for i386 will
follow.
changelog:
- add Intel Precise-Event Based sampling (PEBS) related MSR
- add Intel Data Save (DS) Area related MSR
- add Intel Core microarchitecure performance counter MSRs
Signed-off-by: stephane eranian <eranian@hpl.hp.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'include/asm-x86_64')
| -rw-r--r-- | include/asm-x86_64/msr.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h index 37e194169fa..a745c5008a6 100644 --- a/include/asm-x86_64/msr.h +++ b/include/asm-x86_64/msr.h @@ -210,6 +210,10 @@ static inline unsigned int cpuid_edx(unsigned int op) #define MSR_IA32_LASTINTFROMIP 0x1dd #define MSR_IA32_LASTINTTOIP 0x1de +#define MSR_IA32_PEBS_ENABLE 0x3f1 +#define MSR_IA32_DS_AREA 0x600 +#define MSR_IA32_PERF_CAPABILITIES 0x345 + #define MSR_MTRRfix64K_00000 0x250 #define MSR_MTRRfix16K_80000 0x258 #define MSR_MTRRfix16K_A0000 0x259 @@ -407,4 +411,13 @@ static inline unsigned int cpuid_edx(unsigned int op) #define MSR_P4_U2L_ESCR0 0x3b0 #define MSR_P4_U2L_ESCR1 0x3b1 +/* Intel Core-based CPU performance counters */ +#define MSR_CORE_PERF_FIXED_CTR0 0x309 +#define MSR_CORE_PERF_FIXED_CTR1 0x30a +#define MSR_CORE_PERF_FIXED_CTR2 0x30b +#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d +#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e +#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f +#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 + #endif |