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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-22 10:38:44 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-22 22:09:00 +0100 |
| commit | d04533650f64fe3367e180f3e488d92205152cd3 (patch) | |
| tree | 5f183668d97d9655a8517e61afd46bfa2f80b101 /include/asm-mips | |
| parent | 06d428d719dece96c01532b62df4140f4e69a308 (diff) | |
| download | kernel-crypto-d04533650f64fe3367e180f3e488d92205152cd3.tar.gz kernel-crypto-d04533650f64fe3367e180f3e488d92205152cd3.tar.xz kernel-crypto-d04533650f64fe3367e180f3e488d92205152cd3.zip | |
[MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.
The BCM148 has 4 cores but there are also just 4 generic timers available
so use the ZBbus cycle counter instead of it. In addition the ZBbus
counter also offers a much higher resolution and 64-bit counting so I'm
considering a later complete conversion to it once I figure out if all
members of the Sibyte SOC family support it - the docs seem to agree but
the headers files seem to disagree ...
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
| -rw-r--r-- | include/asm-mips/sibyte/sb1250.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h index 494aa65dcfb..0dad844a3b5 100644 --- a/include/asm-mips/sibyte/sb1250.h +++ b/include/asm-mips/sibyte/sb1250.h @@ -45,13 +45,11 @@ extern unsigned int soc_type; extern unsigned int periph_rev; extern unsigned int zbbus_mhz; -extern void sb1250_hpt_setup(void); extern void sb1250_time_init(void); extern void sb1250_mask_irq(int cpu, int irq); extern void sb1250_unmask_irq(int cpu, int irq); extern void sb1250_smp_finish(void); -extern void bcm1480_hpt_setup(void); extern void bcm1480_time_init(void); extern void bcm1480_mask_irq(int cpu, int irq); extern void bcm1480_unmask_irq(int cpu, int irq); |